CN104460816A - Parallel machine voltage stabilizing circuit of integrated UPS - Google Patents
Parallel machine voltage stabilizing circuit of integrated UPS Download PDFInfo
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- CN104460816A CN104460816A CN201310439065.1A CN201310439065A CN104460816A CN 104460816 A CN104460816 A CN 104460816A CN 201310439065 A CN201310439065 A CN 201310439065A CN 104460816 A CN104460816 A CN 104460816A
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- effect transistor
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Abstract
The invention discloses a parallel machine voltage stabilizing circuit of an integrated UPS. The parallel machine voltage stabilizing circuit comprises a first UPS, a second UPS, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a first field-effect tube, a second field-effect tube, a first current dividing tube, a second current dividing tube, a first light-emitting diode, a second light-emitting diode, a first voltage stabilizer, a second voltage stabilizer, a first operational amplifier and a second operational amplifier. The parallel machine voltage stabilizing circuit has the advantages of being simple in structure, fewer in adopted elements, small in size, low in cost, easy to manufacture and the like; the parallel machine voltage stabilizing circuit is good in voltage stabilizing effect, and the compatible power supplies have the advantages of being low in internal resistance, low in noise and the like.
Description
Technical field
The present invention relates to a kind of mu balanced circuit, particularly relate to the parallel operation mu balanced circuit of a kind of integrated power supply UPS.
Background technology
Power parallel machine mu balanced circuit of the prior art, complex structure, employing element are many, bulky, cost of manufacture high and be not easy make, and when two uninterrupted power source parallel operation compatible in circuit time, often occur that the internal resistance of source increases, the problems such as working power noise ratio is larger, the especially voltage fluctuation of mu balanced circuit are comparatively large, can not high-speed cruising.
Summary of the invention
Object of the present invention is just the parallel operation mu balanced circuit providing a kind of integrated power supply UPS in order to solve the problem.
The present invention is achieved through the following technical solutions above-mentioned purpose:
The present invention includes the first uninterrupted power source, second uninterrupted power source, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, first field effect transistor, second field effect transistor, first isocon, second isocon, first light emitting diode, second light emitting diode, first voltage stabilizer, second voltage stabilizer, first operational amplifier and the second operational amplifier, the positive pole of described first uninterrupted power source is connected with the input end of described first voltage stabilizer, the negative pole of described first uninterrupted power source is connected with the first end of described second resistance and the voltage-regulation end of described second voltage stabilizer simultaneously, with the first end of described 4th electric capacity while of the positive pole of described second uninterrupted power source, the first end of described 3rd electric capacity, the first end of described 5th resistance, the emitter of described first isocon, the power end of described first operational amplifier, the source electrode of described first field effect transistor, the first end of described first resistance is connected with the voltage-regulation end of described first voltage stabilizer, the negative pole of described second uninterrupted power source simultaneously with the first end of described 6th electric capacity, the first end of described 5th electric capacity, the first end of described 8th resistance, the emitter of described second isocon, the power end of described second operational amplifier, the negative pole of described second light emitting diode, the first end of described second electric capacity is connected with the input end of described second voltage stabilizer, the output terminal of described first voltage stabilizer is connected with the second end of described first resistance, the output terminal of described second voltage stabilizer is connected with the second end of described second resistance, the drain electrode of described first field effect transistor is connected with the positive pole of described first light emitting diode, the drain electrode of described second field effect transistor is connected with the positive pole of described second light emitting diode, the grid of described first field effect transistor is connected with the first end of described first electric capacity and the positive input of described first operational amplifier simultaneously, the grid of described second field effect transistor is connected with the second end of described second electric capacity and the direction input end of described second operational amplifier simultaneously, with the negative pole of described first light emitting diode while of the second end of described first electric capacity, the source electrode of described second field effect transistor, the earth terminal of described first operational amplifier, the earth terminal of described second operational amplifier, the emitter of described first isocon, the collector of described second isocon, the first end of described 6th resistance, the first end of described 7th resistance, second end of described 3rd electric capacity, second end of described 5th electric capacity, second end of described 4th electric capacity is connected with the second end of described 6th electric capacity, the output terminal of described first operational amplifier is connected with the first end of described 3rd resistance, the output terminal of described second operational amplifier is connected with the first end of described 4th resistance, the reverse input end of described first operational amplifier is connected with the second end of described 6th resistance and the second end of described 5th resistance simultaneously, the positive input of described second operational amplifier is connected with the second end of described 7th resistance and the second end of described 8th resistance simultaneously, second end of described 3rd resistance is connected with the base stage of described first isocon, and the second end of described 4th resistance is connected with the base stage of described second isocon.
Beneficial effect of the present invention is:
The present invention is the parallel operation mu balanced circuit of a kind of integrated power supply UPS, not only structure simple, adopt that element is few, volume is little, cost is low and the advantage such as easy making, and the voltage voltage regulation result of power parallel machine mu balanced circuit is fine, compatible power supply has the advantages such as low internal resistance, low noise.
Accompanying drawing explanation
Fig. 1 is circuit structure schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
As shown in Figure 1: the present invention includes the first uninterrupted power source UPS1, second uninterrupted power source UPS2, first resistance R1, second resistance R2, 3rd resistance R3, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 8th resistance R8, first electric capacity C1, second electric capacity C2, 3rd electric capacity C3, 4th electric capacity C4, 5th electric capacity C5, 6th electric capacity C6, first field effect transistor VT1, second field effect transistor VT2, first isocon VT3, second isocon VT4, first light emitting diode VD1, second light emitting diode VD2, first voltage stabilizer VC1, second voltage stabilizer VC2, first operational amplifier A 1 and the second operational amplifier A 2, the positive pole of the first uninterrupted power source UPS1 is connected with the input end of the first voltage stabilizer VC1, the negative pole of the first uninterrupted power source UPS1 is connected with the first end of the second resistance R2 and the voltage-regulation end of the second voltage stabilizer VC2 simultaneously, with the first end of the 4th electric capacity C4 while of the positive pole of the second uninterrupted power source UPS2, the first end of the 3rd electric capacity C3, the first end of the 5th resistance R5, the emitter of the first isocon VT3, the power end of the first operational amplifier A 1, the source electrode of the first field effect transistor VT1, the first end of the first resistance R1 is connected with the voltage-regulation end of the first voltage stabilizer VC1, the negative pole of the second uninterrupted power source UPS2 simultaneously with the first end of the 6th electric capacity C6, the first end of the 5th electric capacity C5, the first end of the 8th resistance R8, the emitter of the second isocon VT4, the power end of the second operational amplifier A 2, the negative pole of the second light emitting diode VD2, the first end of the second electric capacity C2 is connected with the input end of the second voltage stabilizer VC2, the output terminal of the first voltage stabilizer VC1 is connected with second end of the first resistance R1, the output terminal of the second voltage stabilizer VC2 is connected with second end of the second resistance R2, the drain electrode of the first field effect transistor VT1 is connected with the positive pole of described first light emitting diode VD1, the drain electrode of the second field effect transistor VT2 is connected with the positive pole of the second light emitting diode VD2 diode, the grid of the first field effect transistor VT1 is connected with the first end of the first electric capacity C1 and the positive input of the first operational amplifier A 1 simultaneously, the grid of the second field effect transistor VT2 is connected with second end of the second electric capacity C2 and the direction input end of the second operational amplifier A 2 simultaneously, with the negative pole of described first light emitting diode VD1 while of second end of the first electric capacity C1, the source electrode of the second field effect transistor VT2, the earth terminal of the first operational amplifier A 1, the earth terminal of the second operational amplifier A 2, the emitter of the first isocon VT3, the collector of the collector VT4 of the second isocon, the first end of the 6th resistance R6, the first end of the 7th resistance R7, second end of the 3rd electric capacity C3, second end of the 5th electric capacity C5, second end of the 4th electric capacity C4 is connected with second end of the 6th electric capacity C6, the output terminal of the first operational amplifier A 1 is connected with the first end of the 3rd resistance R3, the output terminal of the second operational amplifier A 2 is connected with the first end of the 4th resistance R4, the reverse input end of the first operational amplifier A 1 is connected with second end of the 6th resistance R6 and second end of the 5th resistance R5 simultaneously, the positive input of the second operational amplifier A 2 is connected with second end of the 7th resistance R7 and second end of the 8th resistance R8 simultaneously, second end of the 3rd resistance R3 is connected with the base stage of the first isocon VT3, and second end of the 4th resistance R4 is connected with the base stage of the second isocon VT4.Wherein, A, B point is the access point of consumer.
As shown in Figure 1: it is the constant-current circuit of 560mA that the first voltage stabilizer VC1 and the second voltage stabilizer VC2 forms a constant current value with the first resistance R1 and the second resistance R2 respectively, provides the total current in whole loop; First field effect transistor VT1 and the second field effect transistor VT2 is respectively the first light emitting diode VD1 and the second light emitting diode VD2 provides a steady current, obtains the very low stable reference voltage of a noise at the two ends of the first light emitting diode VD1 and the second light emitting diode VD2.First operational amplifier A 1 and the second operational amplifier A 2 control the electric current of the first isocon VT3 and the second isocon VT4 respectively, thus make output voltage constant in a certain setting value.The components and parts that circuit is selected, have several place to note: the steady current about 3 ~ 6mA of (1) first field effect transistor VT1 and the second field effect transistor VT2, require to match up and down, and parameter value is consistent as far as possible.(2) first light emitting diode VD1 and the second light emitting diode VD2 are with Φ 5mm, and pressure drop is 1.6-1.65V, requires to match up and down, parameter value is consistent as far as possible.The β value of (3) first isocon VT3 and the second isocon VT4 is chosen larger as far as possible, ites is desirable to be greater than 60, and heating radiator is also enough large.(4) the 5th resistance R5 will guarantee stability to the 8th R8.(5) power of the transformer T of adapted should not be less than 40W, adopts toroidal transformer T even more ideal.
Claims (1)
1. a parallel operation mu balanced circuit of integrated power supply UPS, is characterized in that: comprise the first uninterrupted power source, second uninterrupted power source, first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, first electric capacity, second electric capacity, 3rd electric capacity, 4th electric capacity, 5th electric capacity, 6th electric capacity, first field effect transistor, second field effect transistor, first isocon, second isocon, first light emitting diode, second light emitting diode, first voltage stabilizer, second voltage stabilizer, first operational amplifier and the second operational amplifier, the positive pole of described first uninterrupted power source is connected with the input end of described first voltage stabilizer, the negative pole of described first uninterrupted power source is connected with the first end of described second resistance and the voltage-regulation end of described second voltage stabilizer simultaneously, with the first end of described 4th electric capacity while of the positive pole of described second uninterrupted power source, the first end of described 3rd electric capacity, the first end of described 5th resistance, the emitter of described first isocon, the power end of described first operational amplifier, the source electrode of described first field effect transistor, the first end of described first resistance is connected with the voltage-regulation end of described first voltage stabilizer, the negative pole of described second uninterrupted power source simultaneously with the first end of described 6th electric capacity, the first end of described 5th electric capacity, the first end of described 8th resistance, the emitter of described second isocon, the power end of described second operational amplifier, the negative pole of described second light emitting diode, the first end of described second electric capacity is connected with the input end of described second voltage stabilizer, the output terminal of described first voltage stabilizer is connected with the second end of described first resistance, the output terminal of described second voltage stabilizer is connected with the second end of described second resistance, the drain electrode of described first field effect transistor is connected with the positive pole of described first light emitting diode, the drain electrode of described second field effect transistor is connected with the positive pole of described second light emitting diode, the grid of described first field effect transistor is connected with the first end of described first electric capacity and the positive input of described first operational amplifier simultaneously, the grid of described second field effect transistor is connected with the second end of described second electric capacity and the direction input end of described second operational amplifier simultaneously, with the negative pole of described first light emitting diode while of the second end of described first electric capacity, the source electrode of described second field effect transistor, the earth terminal of described first operational amplifier, the earth terminal of described second operational amplifier, the emitter of described first isocon, the collector of described second isocon, the first end of described 6th resistance, the first end of described 7th resistance, second end of described 3rd electric capacity, second end of described 5th electric capacity, second end of described 4th electric capacity is connected with the second end of described 6th electric capacity, the output terminal of described first operational amplifier is connected with the first end of described 3rd resistance, the output terminal of described second operational amplifier is connected with the first end of described 4th resistance, the reverse input end of described first operational amplifier is connected with the second end of described 6th resistance and the second end of described 5th resistance simultaneously, the positive input of described second operational amplifier is connected with the second end of described 7th resistance and the second end of described 8th resistance simultaneously, second end of described 3rd resistance is connected with the base stage of described first isocon, and the second end of described 4th resistance is connected with the base stage of described second isocon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310439065.1A CN104460816A (en) | 2013-09-24 | 2013-09-24 | Parallel machine voltage stabilizing circuit of integrated UPS |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310439065.1A CN104460816A (en) | 2013-09-24 | 2013-09-24 | Parallel machine voltage stabilizing circuit of integrated UPS |
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| CN104460816A true CN104460816A (en) | 2015-03-25 |
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| CN201310439065.1A Pending CN104460816A (en) | 2013-09-24 | 2013-09-24 | Parallel machine voltage stabilizing circuit of integrated UPS |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108806216A (en) * | 2018-08-01 | 2018-11-13 | 合肥阅辞科技有限公司 | Intelligent safety prevention warning system |
| CN108958147A (en) * | 2018-08-01 | 2018-12-07 | 合肥阅辞科技有限公司 | Domestic intelligent safety defense monitoring system |
-
2013
- 2013-09-24 CN CN201310439065.1A patent/CN104460816A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108806216A (en) * | 2018-08-01 | 2018-11-13 | 合肥阅辞科技有限公司 | Intelligent safety prevention warning system |
| CN108958147A (en) * | 2018-08-01 | 2018-12-07 | 合肥阅辞科技有限公司 | Domestic intelligent safety defense monitoring system |
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Application publication date: 20150325 |
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