CN104426548A - A/D (Analog/Digital) conversion sampling circuit and metering chip - Google Patents
A/D (Analog/Digital) conversion sampling circuit and metering chip Download PDFInfo
- Publication number
- CN104426548A CN104426548A CN201310400984.8A CN201310400984A CN104426548A CN 104426548 A CN104426548 A CN 104426548A CN 201310400984 A CN201310400984 A CN 201310400984A CN 104426548 A CN104426548 A CN 104426548A
- Authority
- CN
- China
- Prior art keywords
- output
- input
- data selector
- connects
- live wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides an A/D (Analog/Digital) conversion sampling circuit and a metering chip. The A/D conversion sampling circuit comprises a modulator, a digital filtering and extracting unit and a phase correction circuit, wherein the phase correction circuit comprises a first delay unit and a second delay unit; the first delay unit is respectively connected with the output end of the modulator and the input end of the digital filtering and extracting unit; the second delay unit is connected with the output end of the digital filtering and extracting unit. According to the A/D conversion sampling circuit and the metering chip disclosed by the invention, a digital signal outputted by the modulator and a digital signal outputted by the digital filtering and extracting unit are respectively subjected to delay processing, so that the area of the A/D conversion sampling circuit is reduced, and the manufacturing difficulty, the cost and power consumption of the A/D conversion sampling circuit are reduced.
Description
Technical field
The present invention relates to metering field, particularly relate to a kind of analog-to-digital conversion sample circuit and computation chip.
Background technology
China is an electric energy meter application big country, and annual national demand about 3,000 ten thousand, the electric energy meter of current China mainly contains stem-winder, Mechatronics energy meter and all-electronin electric energy meter.The metering device of all-electronin electric energy meter is mainly made up of special computation chip and peripheral associated hardware circuitry, along with the development and progression of electronic technology and the development of electric energy meter technology, the reliability of special computation chip, stability, economy are all greatly improved.
The electric energy computation chip of current main flow, the inner structure adopting analog to digital converter (Analog to DigitalConverter is called for short ADC) sample circuit, logical circuit of arithmetic and control circuit.The signal of the electric current that computation chip uses logical circuit of arithmetic process analog-to-digital conversion sample circuit to gather and voltage, and obtain corresponding power, effective value and other electric parameter information, export the pulse signal relevant to electric flux simultaneously.
Usually, analog-to-digital conversion sample circuit comprises: modulator, digital filtering and extracting unit, delay unit.Wherein, delay unit is for adjusting the phase place of the digital signal of modulator output, in order to realize phasing accurately, the minimum interval that delay unit corrects is equal with the sampling clock cycle of modulator, simultaneously in order to meet the demand that maximum phase corrects, it is very huge that time-delay unit circuit in analog-to-digital conversion sample circuit designs, and makes the area of analog-to-digital conversion sample circuit, the difficulty of manufacture and cost all larger.
At present, the logical circuit of arithmetic in computation chip mainly comprises electric voltage frequency and phase angle measurement circuit, power-measuring circuit and voltage, current effective value measuring circuit.Wherein, electric voltage frequency and phase angle measurement many employings software mode realize, the separate setting of the measuring circuit of power, voltage, current effective value measures different electric parameters respectively, and a large amount of electric parameter metering circuit makes the area of computation chip and power consumption all larger, and cost is higher.
Summary of the invention
The invention provides a kind of analog-to-digital conversion sample circuit and computation chip, the problem that computation chip area, power consumption, manufacture difficulty and cost that in the huge and computation chip of the time-delay unit circuit in order to solve existing analog-to-digital conversion sample circuit, numerous measuring circuits causes are all larger.
One aspect of the present invention provides a kind of analog-to-digital conversion sample circuit, it is characterized in that, comprising: modulator, digital filtering and extracting unit, phase-correcting circuit; Described phase-correcting circuit comprises the first delay unit and the second delay unit, described first delay unit is connected with the input of the output of described modulator, described digital filtering and extracting unit respectively, and described second delay unit is connected with the output of described digital filtering and extracting unit.
Another aspect of the present invention provides a kind of computation chip, it is characterized in that, comprising: three analog-to-digital conversion sample circuits, the first electric parameter metering circuit be connected with described three analog-to-digital conversion sample circuits respectively;
Described three analog-to-digital conversion sample circuits, for sampling to the voltage signal inputted, live wire current signal, neutral line current signal respectively, and the voltage signal obtained sampling, live wire current signal, neutral line current signal output to voltage output end, live wire current output terminal, neutral line current output respectively;
Described first electric parameter metering circuit, voltage signal, live wire current signal, neutral line current signal for obtaining according to described sampling calculate, and obtain the respective value of the phase angle of the respective value of the phase angle of the respective value of electric voltage frequency, voltage and live wire electric current, voltage and neutral line current.
Analog-to-digital conversion sample circuit provided by the invention, by carrying out delays time to control to the digital signal of modulator and digital filtering and extracting unit output respectively, make it possible to the quantity of the time-delay trigger reduced in analog-to-digital conversion sample circuit, and then reduce the area of analog-to-digital conversion sample circuit, reduce the manufacture difficulty of analog-to-digital conversion sample circuit, cost and power consumption, in addition, computation chip provided by the invention adopts hardware circuit to realize the measurement of electric voltage frequency and phase angle, reduce the manufacture difficulty of computation chip, save the manufacturing cost of computation chip.
Accompanying drawing explanation
The analog-to-digital conversion sample circuit structural representation that Fig. 1 provides for prior art;
Fig. 2 is analog-to-digital conversion sampling circuit embodiment structural representation provided by the invention;
Fig. 3 is computation chip embodiment one structural representation provided by the invention;
Fig. 4 is the structural representation of the first electric parameter metering circuit in the computation chip embodiment one shown in Fig. 3;
Figure 5 shows that the signal principle figure of the first electric parameter metering circuit shown in Fig. 4;
Figure 6 shows that the structural representation of computation chip embodiment two provided by the invention;
Fig. 7 is the structural representation of the second electric parameter metering circuit in the computation chip embodiment two shown in Fig. 6;
Figure 8 shows that the structural representation of computation chip embodiment three provided by the invention;
Fig. 9 is the structural representation of the 3rd electric parameter metering circuit in the computation chip embodiment three shown in Fig. 8;
Figure 10 shows that the structural representation of computation chip embodiment four provided by the invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The analog-to-digital conversion sample circuit structural representation that Fig. 1 provides for prior art.As shown in Figure 1, this analog-to-digital conversion sample circuit comprises: modulator 10, digital filtering and extracting unit 11, delay unit 12.Wherein, modulator input input analog signal, the output of modulator connects the input of delay unit, and the output of delay unit connects the input of digital filtering and extracting unit.Modulator is used for digital signal analog signal being modulated into 1; Delay unit is used for carrying out phasing according to the phase correcting value stored in register in the control circuit (not shown in figure 1) in computation chip and communication module, adjusted the phase place of digital signal by time delay, be usually made up of some structures, time-delay trigger that function is identical; Digital filtering and extracting unit circuit are used for converting the digital signal of 1 to N position digital signal, and the digital signal of N position is carried out filtering extraction, to improve described analog-to-digital conversion sample circuit signal to noise ratio, wherein, N is described analog-to-digital conversion sample circuit actual design bit wide.
Fig. 2 is analog-to-digital conversion sampling circuit embodiment structural representation provided by the invention, and as shown in Figure 2, this analog-to-digital conversion sample circuit comprises: modulator 20, digital filtering and extracting unit 21, phase-correcting circuit 22; Described phase-correcting circuit comprises the first delay unit 220 and the second delay unit 221, described first delay unit is connected with the input of the output of described modulator, described digital filtering and extracting unit respectively, and described second delay unit is connected with the output of described digital filtering and extracting unit.
In the present embodiment, described modulator is used for digital signal analog signal being modulated into L position; Described phase-correcting circuit is used for by carrying out to digital signal the phase place that delays time to control adjusts digital signal, particularly, first delay unit is for adjusting the phase place of the digital signal of modulator output, and the second delay unit is for adjusting the phase place of the digital signal of digital filtering and extracting unit output; Described digital filtering and extracting unit are used for carrying out down-sampled process to the digital signal of input, export the digital signal equal with the bit wide that analog-to-digital conversion sample circuit designs.
Particularly, described first delay unit comprises M time-delay trigger, and described second delay unit comprises K time-delay trigger, M=(X-1) * L, X are the down-sampled multiple of described digital filtering and extracting unit, and L is the figure place of the digital signal that described modulator exports, K=Y*N, N is the figure place of the digital signal that described digital filtering and extracting unit export, and Y is the time-delay trigger number that the bits per inch word signal in N position digital signal is corresponding respectively, M, K, X, N, L, Y are positive integer.
In a kind of feasible implementation, the time-delay trigger that first delay unit is identical by structure with the second delay unit is formed, the L position digital signal that first delay unit is used for modulator exports carries out delays time to control, and the N position digital signal that the second delay unit is used for digital filtering and extracting unit export carries out delays time to control.
Further, the minimum interval that the first delay unit corrects equals the sampling clock cycle of modulator, and the minimum interval that the second delay unit corrects equals the clock cycle of digital filtering and extracting unit.For example, if the sample frequency of modulator is f
s, the down-sampled multiple of digital filtering and extracting unit is X, and namely the frequency of digital filtering and extracting unit is f
s/ X, then the minimum interval that the first delay unit corrects is 1/f
s, the minimum interval that the second delay unit corrects is X/f
s, can find out, what the first delay unit realized is smart phasing, and the second delay unit realization is thick phasing.
Usually, to modulator export L position digital signal carry out delay process time, at least need L time-delay trigger to process this L position digital signal simultaneously, and in order to this L position digital signal at X/f
scan carry out delays time to control in time, then in the first delay unit, the quantity M of time-delay trigger need be designed to down-sampled multiple (X-1) the individual L of digital filtering and extracting unit, i.e. M=(X-1) * L; Similarly, to digital filtering and extracting unit export for N position digital signal carry out delay process time, at least need N number of time-delay trigger to process this N position digital signal simultaneously, in order to realize the delay process in full time range to this N position digital signal, in second delay unit, the number needs of time-delay trigger is set to the integral multiple of N, i.e. K=Y*N, Y represents and is respectively the number that N is the time-delay trigger of bits per inch word signal setting in digital signal, Y is positive integer, Y according to the clock cycle of digital filtering and extracting unit in conjunction with different application occasion value.
Preferably, L=1, modulator herein can be sigma-delta modulator, and the modulator that also can export one bit digital signal for other, the present embodiment does not limit this.For realizing analog signal to the high-precision conversion of digital signal, the sample frequency of modulator is usually much larger than Nyquist rate, and namely the sample frequency of modulator is much larger than the bandwidth of the analog signal of 2 times.Correspondingly, the one bit digital signal that first delay unit is used for modulator exports carries out delay process, digital filtering and extracting unit are used for converting the one bit digital signal that the first delay unit exports to N position digital signal, and the digital signal of N position is carried out filtering extraction, to improve the signal to noise ratio of analog-to-digital conversion sampling.
Particularly, the usage quantity of each delay unit is determined by the phase correcting value stored in register in computation chip control circuit and communication module, and the minimum interval that phase correcting value is corrected by phase deviation and each delay unit is determined.Be 1 for modulator output signal, design bit wide is the analog-to-digital conversion sample circuit of N position, when delay time t corresponding to the phase value needing to correct is between 1/f
sand X/f
sbetween time, in circuit access ［ t*f
stime-delay trigger in individual first delay unit; The delay time t corresponding when the phase value needing to correct equals X/f
stime circuit in access N number of time-delay trigger in the second delay unit; When delay time t corresponding to phase value needing to correct is between X/f
sand 2*X/f
stime, access the N number of time-delay trigger in the second delay unit and the ［ (t-X/f in the first delay unit in circuit
s) * f
sindividual time-delay trigger, the like, when t is greater than R*X/f
stime, access R*N time-delay trigger in the second delay unit and the ［ (t-R*X/f in the first delay unit in circuit
s) * f
sindividual time-delay trigger.For example, assuming that be 2.048 megahertzes (MHz) containing the clock frequency of the analog-to-digital conversion sample circuit of sigma-delta modulator, bit wide is 20, through the digital filterings of 256 times with after extracting, the clock frequency exporting data is 8 KHz (kHz), cycle is 125 microseconds (μ s), according to the solution of the present invention, in the quantity of the first delay unit, time-delay trigger is designed to 255, in the present embodiment, be that bits per inch word signal in 20 position digital signals arranges 2 time-delay triggers respectively, namely in the second delay unit, the quantity of time-delay trigger is 40, if desired the phase value corrected is 3.6 °, for 50Hz industrial-frequency alternating current, the time quantum that need correct is 200 μ s, between 125 μ s and 250 μ s, then during actual use, the quantity of the time-delay trigger in place in circuit in the second delay unit is 20, the quantity of the time-delay trigger of the first delay unit is that ［ (200-125) * 2.048 ］ is individual, namely 154 time, make signal lag 3.6035 °, required precision can be met.If by the solution of the present invention, the attainable maximum correction scope of the phase-correcting circuit be made up of the first delay unit and the second delay unit is 2*125 μ s+125 μ s=375 μ s, if by prior art, for arriving by the identical maximum correction scope of the delay unit of the solution of the present invention design, in delay unit, the number needs of time-delay trigger is designed to: 375 μ s/ (1/2.048MHz)=768.If prior art is in order to realize the correction accuracy identical with the present invention during use, the phase error correcting 3.6 ° needs 410 time-delay triggers altogether.Can find out, be that much more many design or the actual quantity of time-delay trigger in prior art delay unit that uses is all than the quantity of technical scheme of the present invention.
The analog-to-digital conversion sample circuit that the present embodiment provides, by carrying out delay process to the digital signal of modulator output and the digital signal of digital filtering and extracting unit output respectively, decrease the quantity of the time-delay trigger in analog-to-digital conversion sample circuit, the area reducing analog-to-digital conversion sample circuit, the manufacture difficulty reducing circuit, cost and power consumption.
Figure 3 shows that the structural representation of computation chip embodiment one provided by the invention, as shown in Figure 3, this computation chip comprises: three analog-to-digital conversion sample circuits 30,31,32, the first electric parameter metering circuit 33 be connected with described three analog-to-digital conversion sample circuits respectively; Wherein, described three analog-to-digital conversion sample circuits, for sampling to the voltage signal inputted, live wire current signal, neutral line current signal respectively, and the voltage signal obtained sampling, live wire current signal, neutral line current signal output to voltage output end, live wire current output terminal, neutral line current output respectively; Described first electric parameter metering circuit, voltage signal, live wire current signal, neutral line current signal for obtaining according to described sampling calculate, and obtain the respective value of the phase angle of the respective value of the phase angle of the respective value of electric voltage frequency, voltage and live wire electric current, voltage and neutral line current.
Preferably, in the present embodiment, described three analog-to-digital conversion sample circuits can adopt analog-to-digital conversion sample circuit provided by the invention.
Fig. 4 is the structural representation of the first electric parameter metering circuit in the computation chip embodiment one shown in Fig. 3, as shown in Figure 4, the first electric parameter metering circuit 33 comprises: the first low pass filter 400, second low pass filter 401, the 3rd low pass filter 402, first zero-crossing pulse generator 403, second zero-crossing pulse generator 404, the 3rd zero-crossing pulse generator 405, electric voltage frequency counter 406, first-phase angle counter 407, second-phase angle counter 408;
The input of described first low pass filter connects described voltage output end, the output of described first low pass filter connects the input of described first zero-crossing pulse generator, the output of described first zero-crossing pulse generator connects input, the first input end of first-phase angle counter, the first input end of second-phase angle counter of described electric voltage frequency counter, and the output of described electric voltage frequency counter is used for the respective value of output voltage frequency;
The input of described second low pass filter connects described live wire current output terminal, the output of described second low pass filter connects the input of described second zero-crossing pulse generator, the output of described second zero-crossing pulse generator connects the second input of described first-phase angle counter, and the output of described first-phase angle counter is used for the respective value of output voltage and live wire current phase angle;
The input of described 3rd low pass filter connects described neutral line current output, the output of described 3rd low pass filter connects the input of described 3rd zero-crossing pulse generator, the output of described 3rd zero-crossing pulse generator connects the second input of described second-phase angle counter, and the output of described second-phase angle counter is used for the respective value of output voltage and neutral line current phase angle.
In the present embodiment, the voltage signal that analog-to-digital conversion sampling circuit samples obtains is after the first low pass filter filtering harmonic component signal, input to the first zero-crossing pulse generator again, first zero-crossing pulse generator voltage signal from negative value be changed on the occasion of time produce a pulse signal, electric voltage frequency counter is using the zero-crossing pulse signal of adjacent voltage signal as the starting point and ending point of a count cycle, and a count cycle count value is the respective value of electric voltage frequency.
Particularly, counting is started when a voltage zero-cross pulse signal carrys out interim electric voltage frequency counter, stop counting to next voltage zero-cross pulse signal temporarily and export the count value of now electric voltage frequency counter, be the respective value of electric voltage frequency, and then by counter O reset and restart counting, wait for voltage zero-cross pulse signal next time, back and forth carry out the respective value of calculating voltage frequency continuously with this, the frequency of voltage on power line can be calculated according to the count value of electric voltage frequency and the count frequency of electric voltage frequency counter.
Correspondingly, live wire current signal, neutral line current signal is respectively through the second low pass filter, after 3rd low pass filter filtering harmonic component signal, again through the second zero-crossing pulse generator, 3rd zero-crossing pulse generator, respectively at live wire current signal, neutral line current signal from negative value be changed on the occasion of time produce a pulse signal, first-phase angle counter is using voltage signal as the starting point of count cycle, using the zero-crossing pulse signal of adjacent live wire current signal as the terminating point of count cycle, counting can draw the respective value of voltage and live wire current phase angle, second-phase angle counter is using voltage signal as the starting point of count cycle, using the zero-crossing pulse signal of adjacent neutral line current signal as the terminating point of count cycle, counting can draw the correspondence of voltage and neutral line current phase angle.
Particularly, counting is started when a voltage zero-cross pulse signal carrys out interim first-phase angle counter, until adjacent live wire current over-zero pulse signal stops counting and exports the count value of first-phase angle counter temporarily, be the respective value of voltage and live wire current phase angle, and then first-phase angle counter is reset, wait for that voltage zero-cross pulse signal starts counting after arriving next time, continues this process, back and forth carrys out the respective value of calculating voltage and live wire current phase angle continuously with this.The phase angle of voltage and live wire electric current can be calculated according to voltage and the respective value of live wire current phase angle and the respective value of electric voltage frequency.
Correspondingly, counting is started when a voltage zero-cross pulse signal carrys out interim second-phase angle counter, until next neutral line current zero-crossing pulse signal stops counting and exports the count value of second-phase angle counter temporarily, be the respective value of voltage and neutral line current phase angle, and then second-phase angle counter is reset, wait for that voltage zero-cross pulse signal starts counting after arriving next time, continues this process, back and forth carrys out the phase angle respective value of calculating voltage and neutral line current continuously with this.The phase angle of voltage and neutral line current can be calculated according to voltage and the respective value of neutral line current phase angle and the respective value of electric voltage frequency.
Figure 5 shows that the signal principle figure of the first electric parameter metering circuit shown in Fig. 4.As shown in Figure 5, a is the voltage signal figure of input, b is the live wire current signal figure of input, c is the neutral line current signal graph of input, and d is the voltage zero-cross pulse signal that the first zero-crossing pulse generator produces, and e is the live wire current over-zero pulse signal that the second zero-crossing pulse generator produces, f is the neutral line current zero-crossing pulse signal that the 3rd zero-crossing pulse generator produces, g is the counting diagram of electric voltage frequency counter, and h is the counting diagram of first-phase angle counter, and j is the counting diagram of second-phase angle counter.
The count value of electric voltage frequency counter within a count cycle is D as shown in Figure 5
1, namely the respective value of electric voltage frequency is D
1, the count value of first-phase angle counter within a count cycle is D
2,, namely the respective value of voltage and live wire current phase angle is D
2, the count value of second-phase angle counter within a count cycle is D
3,, namely the respective value of voltage and neutral line current phase angle is D
3if the count frequency of electric voltage frequency counter is f, then electric voltage frequency actual value is (f/D
1) Hz, voltage and live wire current phase angle actual value are (D
2/ D
1) × 360 °, voltage and neutral line current phase angle actual value are (D
3/ D
1) × 360 °.
The computation chip that the present embodiment provides, hardware circuit is adopted to realize the survey calculation of the respective value of respective value, voltage and neutral line current phase angle to the respective value of electric voltage frequency, voltage and live wire current phase angle, compared to the method that prior art adopts software to calculate, simplify the circuit structure of computation chip, reduce the manufacturing cost of computation chip.
Fig. 6 is computation chip embodiment two structural representation provided by the invention.As shown in Figure 6, on the basis of the computation chip embodiment one shown in Fig. 3, computation chip embodiment two provided by the invention also comprises the second electric parameter metering circuit 34 be connected with described three analog-to-digital conversion sample circuits respectively.
Fig. 7 is the structural representation of the second electric parameter metering circuit in the computation chip embodiment two shown in Fig. 6.As shown in Figure 7, the second electric parameter metering circuit comprises: the first counter 700,90-degree phase shifter 701, first data selector 702, second data selector 703, the 3rd data selector 704, the 4th data selector 705, first multiplier 706, the 4th low pass filter 707, first adder 708, second multiplier 709, first decoder 710;
First input end, the 3rd input of described first data selector all connect described live wire current output terminal, second input, the four-input terminal of described first data selector all connect described neutral line current output, and the output of described first data selector is connected to the first input end of described first multiplier;
First input end, second input of described second data selector all connect described voltage output end, 3rd input of described second data selector, four-input terminal all connect the output of described 90-degree phase shifter, the input of described 90-degree phase shifter connects described voltage output end, and the output of described second data selector is connected to the second input of described first multiplier;
The output of described first multiplier connects the input of described 4th low pass filter, and the output of described 4th low pass filter connects the first input end of described first adder;
The first input end of described 3rd data selector connects live wire active power compensatory control end, second input section of described 3rd data selector connects zero line active power compensatory control end, 3rd input of described 3rd data selector connects live wire reactive power compensation control end, the four-input terminal of described 3rd data selector connects zero line reactive power compensation control end, and the output of described 3rd data selector is connected to the second input of described first adder;
The output of described first adder connects the first input end of described second multiplier;
The first input end of described 4th data selector connects live wire active power gain control end, second input section of described 4th data selector connects zero line active power gain control end, 3rd input of described 4th data selector connects live wire reactive power gain control end, the four-input terminal of described 4th data selector connects zero line reactive power gain control end, and the output of described 4th data selector is connected to the second input of described second multiplier;
The input of described first decoder connects the output of described second multiplier;
The selection signal end of described first data selector, the second data selector, the 3rd data selector, the 4th data selector, the first decoder is all connected with the output of described first counter, and the first output of described first decoder, the second output, the 3rd output, the 4th output are successively for exporting respective value, the respective value of zero line active power, the respective value of live wire reactive power, the respective value of zero line reactive power of live wire active power.
In the present embodiment, each data selector and the first decoder can build realization by simple gate circuit, and the first counter can realize with up counter or subtract counter, and the present embodiment does not limit this.
The figure place of the first counter is determined according to each data selector input quantity and the first decoder output quantity.For example, in the present embodiment, each data selector all has four inputs, the first decoder has four outputs, and the up counter of 22 systems can be selected to control the data of each data selector and the selection of the first decoder.First counter input be the clock signal of fixed frequency, the different count status number that the frequency of this clock signal is exported by the first counter is determined with the signal frequency of input the second electric parameter metering circuit, usually, the clock signal frequency inputting the first counter is the product of the count status number that the signal frequency of input second electric parameter metering circuit is different from the first counter.In the present embodiment, the different count status that the up counter of 22 systems that the first counter adopts exports have 00,01,10,11,4 count status, then the clock signal frequency inputting the first counter is 4 times of the signal frequency of input second electric parameter metering circuit, the voltage even inputted, live wire electric current, neutral line current signal frequency are 8kHz, and the first counter then comes each data selector of switching controls and the first decoder with the frequency of 32kHz.Each multiplier in second electric parameter metering circuit and the operating frequency of first adder are determined according to the frequency of the signal inputting each multiplier and first adder, and the operating frequency of usual each multiplier and first adder is greater than the clock signal frequency of input first counter.For example, when the first rolling counters forward is 00, each data selector selects the data of first input end, and corresponding first decoder selects the first output to export data, the respective value of circuit counting live wire active power; During first clock signal input, the first rolling counters forward is 01, and each data selector selects the data of the second input, and corresponding first decoder selects the second output to export data, the respective value of circuit counting zero line active power; During second clock signal input, the first rolling counters forward is 10, and each data selector selects the data of the 3rd input, and corresponding first decoder selects the 3rd output to export data, the respective value of circuit counting live wire reactive power; During the 3rd clock signal input, the first rolling counters forward is 11, and each data selector selects the data of four-input terminal, and corresponding first decoder selects the 4th output to export data, the respective value of circuit counting zero line reactive power; During the 4th clock signal input, the first rolling counters forward is 00, the respective value of circuit counting live wire active power; The switching controls to each data selector, the first decoder and computing circuit is back and forth realized with this.
In the present embodiment, live wire active power compensatory control end, zero line active power compensatory control end, live wire reactive power compensation control end, live wire reactive power compensation control end, live wire active power gain control end, zero line active power gain control end, live wire reactive power gain control end and zero line reactive power gain control end are corresponding with the corresponding output end of the register in computation chip control circuit and communication module respectively, for the respective value of live wire active power measured computation chip, the respective value of zero line active power, the respective value of live wire reactive power and the respective value of zero line reactive power compensate and gain calibration, to eliminate the error in circuit.
Particularly, when the first rolling counters forward is 00, the second electric parameter metering circuit counting be active power respective value on live wire.Correspondingly, first data selector selects live wire current signal, second data selector selects voltage signal, 3rd data selector selects live wire active power compensating signal, 4th data selector selects live wire active power gain signal, first decoder selects the first output to export live wire active power respective value, accordingly, live wire electric current and voltage are carried out multiplying by the first multiplier, the product drawn inputs to first adder after the 4th low pass filter filtering, the product of filtered live wire electric current and voltage is added with the live wire active power compensating signal that the 3rd data selector inputs and compensates the product of described live wire electric current and voltage by first adder, live wire electric current after compensating and the product of voltage and live wire active power multiplied by gains are calculated the respective value of live wire active power and are exported by the first output of the first decoder by the second multiplier.
Correspondingly, when the first rolling counters forward is 01, the second electric parameter metering circuit counting be active power respective value on zero line.
Further, when the first rolling counters forward is 10, the second electric parameter metering circuit counting be reactive power respective value on live wire.Especially, the first multiplier carries out multiplying by by the voltage signal after 90 ° of phase shifter phase shifts and live wire current signal, through the 4th low pass filter, is exported after first adder and the second multiplier by the first decoder the 3rd output; Similarly, when the first rolling counters forward is 11, the second electric parameter metering circuit counting be reactive power respective value on zero line.
Further, the described live wire active power respective value in the present embodiment, zero line active power respective value, live wire reactive power respective value, zero line reactive power respective value are carried out simple arithmetic and can be drawn actual live wire active power value, zero line active power value, live wire reactive power value, zero line reactive power value.
The second electric parameter metering circuit that the present embodiment provides, in the circuit measuring the respective value of live wire active power, the respective value of live wire reactive power, the respective value of zero line active power, the respective value of zero line reactive power, to the mode adopting the computing circuit of identical algorithms to adopt time-sharing multiplex, with prior art, independently circuit simplified in comparison circuit structure is all adopted to the measurement of every parameter, improve the utilance of computing circuit, reduce the area of circuit, power consumption and manufacturing cost.
Fig. 8 is computation chip embodiment three structural representation provided by the invention.As shown in Figure 8, on the basis of the computation chip embodiment two shown in Fig. 6, computation chip embodiment three provided by the invention, also comprises: the 3rd electric parameter metering circuit 35 be connected with described three analog-to-digital conversion sample circuits respectively.
Fig. 9 is the structural representation of the 3rd electric parameter metering circuit in the computation chip embodiment three shown in Fig. 8.As shown in Figure 9, described 3rd electric parameter metering circuit comprises: the second counter 900, the 5th data selector 901, the 6th data selector 902, the 7th data selector 903, the 3rd multiplier 904, the 5th low pass filter 905, square root calculation device 906, second adder 907, the 4th multiplier 908, second decoder 909;
The first input end of described 5th data selector connects live wire current output terminal, second input of described 5th data selector connects neutral line current output, 3rd input of described 5th data selector connects voltage output end, and the output of described 5th data selector connects two inputs of described 3rd multiplier;
The output of described 3rd multiplier connects the input of described 5th low pass filter;
The output of described 5th low pass bandpass filter connects described square root calculation device input;
Described square root calculation device output connects the first input end of described second adder;
The first input end of described 6th data selector connects live wire current effective value compensatory control end, second input of described 6th data selector connects neutral line current effective value compensatory control end, 3rd input of described 6th data selector connects voltage effective value compensatory control end, and the output of described 6th data selector connects the second input of described second adder;
The output of described second adder connects the first input end of described 4th multiplier;
The first input end of described 7th data selector connects live wire current effective value gain control end, second input of described 7th data selector connects neutral line current rms gain control end, 3rd input of described 7th data selector connects voltage effective value gain control end, and the output of described 7th data selector connects the second input of described 4th multiplier;
The output of described 4th multiplier connects the input of described second decoder;
The control end of described 5th data selector, the 6th data selector, the 7th data selector, the second decoder is all connected with the output of described second counter, and the first output of described second decoder, the second output, the 3rd output are successively for exporting respective value, the respective value of neutral line current effective value, the respective value of voltage effective value of live wire current effective value.
In the present embodiment, each data selector and the second decoder can build realization by simple gate circuit, and the second counter can realize with up counter or subtract counter, and the present embodiment does not limit this.
The figure place of the second counter is determined according to data selector input quantity each in the 3rd electric parameter metering circuit and the second decoder output quantity, consider that circuit design selects the minimum principle of part category, the data that the second counter herein can equally with the first counter in the second electric parameter metering circuit select the up counter of 22 systems to select to control each data selector and the second decoder.The input of the second counter is the clock signal of fixed frequency, the different count status number that the frequency of this clock signal is exported by the second counter is determined with the signal frequency of input the 3rd electric parameter metering circuit, usually, the clock signal frequency inputting the second counter is the signal frequency of input the 3rd electric parameter metering circuit and the product of the different count status number of the second counter.In the present embodiment, the different count status that the second counter exports are 00,01,10,11, and totally 4 different count status, then the clock signal frequency inputting the second counter is 4 times of the signal frequency of input the 3rd electric parameter metering circuit.Concrete, if the voltage of input, live wire electric current, neutral line current signal frequency are 8kHz, the second counter then comes each data selector of switching controls and the second decoder with the frequency of 32kHz.Each multiplier operating frequency in 3rd electric parameter metering circuit is determined according to the frequency of the signal of input each multiplier, square root calculation device and second adder, usually, the operating frequency of each multiplier, square root calculation device and second adder is greater than the clock signal frequency of input second counter.For example, when the second rolling counters forward is 00, each data selector selects the data of first input end, and corresponding second decoder selects the first output to export data, the respective value of circuit counting live wire current effective value; During first clock signal input, the second rolling counters forward is 01, and each data selector selects the data of the second input, and corresponding second decoder selects the second output to export data, the respective value of circuit counting neutral line current effective value; During second clock signal input, the second rolling counters forward is 10, and each data selector selects the data of the 3rd input, and corresponding second decoder selects the 3rd output to export data, the respective value of circuit counting voltage effective value; During the 3rd clock signal input, second rolling counters forward is 11, circuit does not do any action, during the 4th clock signal input, second rolling counters forward is 00, the respective value of circuit counting live wire current effective value, back and forth realizes the switching controls to each data selector, the second decoder and computing circuit with this.
In the present embodiment, live wire current effective value compensatory control end, neutral line current effective value compensatory control end, voltage effective value compensatory control end, live wire current effective value gain control end, neutral line current rms gain control end, voltage effective value gain control end are corresponding with the corresponding output end of the register in computation chip control circuit and communication module respectively, for respective value, the respective value of neutral line current effective value of live wire current effective value measured computation chip with the respective value of voltage effective value compensates and gain calibration, to eliminate the error in circuit.
Particularly, when the second rolling counters forward is 00, the 3rd electric parameter metering circuit counting be the respective value of live wire current effective value.Correspondingly, 5th data selector selects live wire current signal, 6th data selector selects live wire current effective value compensating control signal, 7th data selector selects live wire current effective value gain signal, second decoder selects the first output to export the respective value of live wire current effective value, accordingly, live wire electric current is carried out square operation by the 3rd multiplier, the product drawn inputs to square root calculation device and carries out extracting operation after the 5th low pass filter filtering, the square root of the live wire current effective value after evolution is inputed to second adder by square root calculation device, the live wire current effective value compensating signal that the square root of live wire electric current and the 6th data selector input is added and compensates described live wire current effective value by second adder, live wire current effective value after compensation and live wire current effective value multiplied by gains are calculated the respective value of live wire current effective value and are exported by the first output of the second decoder by the 4th multiplier.
Further, when the second rolling counters forward is 10, the 3rd electric parameter metering circuit counting be the respective value of neutral line current effective value, when the second rolling counters forward is 10, the 3rd electric parameter metering circuit counting be the respective value of voltage effective value.
Further, the respective value of the described live wire current effective value in the present embodiment, the respective value of neutral line current effective value, the respective value of voltage effective value are carried out simple arithmetic and can be drawn actual live wire current effective value, neutral line current effective value, voltage effective value.
Preferably, the second counter in the present embodiment can be same counter with the first counter in the second electric parameter metering circuit.
The 3rd electric parameter metering circuit that the present embodiment provides, in the circuit of the respective value of the respective value of measuring voltage effective value, the respective value of live wire current effective value and neutral line current effective value, to the mode adopting the computing circuit of identical algorithms to adopt time-sharing multiplex, with prior art, independently circuit simplified in comparison circuit structure is all adopted to the measurement of every parameter, improve the utilance of computing circuit, reduce the area of circuit, power consumption and manufacturing cost.
Figure 10 is the structural representation of a kind of computation chip embodiment four provided by the invention.As shown in Figure 10, this computation chip comprises: analog signal sampling module 100, digital signal processing module 101, control and communication module 102; Wherein, analog signal sampling module 100 comprises: three analog-to-digital conversion sample circuits 30,31,32, and digital signal processing module 101 comprises: the first electric parameter metering circuit 33, second electric parameter metering circuit 34, the 3rd electric parameter metering circuit 35; Control and communication module 102 comprise: pulse output control module 36, register and communication module 37, interruption/Super-zero control module 38.
In the present embodiment, analog signal sampling module is used for converting the voltage of input, live wire electric current, neutral line current to digital signal, and the digital signal obtained sampling enters horizontal phasing control according to the phase correcting value controlled and communication module inputs.
Further, digital signal processing module is used for carrying out real-time calculating and relevant electric energy detection to the voltage signal inputted, live wire current signal, neutral line current signal, as respective value, the respective value of live wire active power, the respective value of zero line reactive power of calculating voltage effective value, detect Voltage Drop, interruption, zero passage, anti-electricity-theft, start shunt running etc.Control and communication module, for the micro control unit MCU(Micro Control Unit in metering device, be called for short MCU) carry out data exchange communications, and control electrical energy pulse output, interrupt the output etc. of zero cross signal.
Particularly, register and communication module are for preserving the correction of MCU write, compensating parameter, in use for analog-to-digital conversion sample circuit and each electric parameter metering circuit provide correction, compensatory control, make the variable of computation chip closer to actual value, in addition, register and communication module are also for preserving the respective value of each measured value that each electric parameter metering circuit exports, and export to MCU, the respective value of each electric parameter of input is carried out simple arithmetic by MCU can obtain actual live wire active power value, zero line active power value, live wire reactive power value, zero line reactive power value, voltage effective value, live wire current effective value and neutral line current effective value, pulse output control module is used for the control signal according to register and communication module, the pulse signal that the respective value of the respective value of output zero line active power, the respective value of zero line reactive power, live wire active power, the respective value of live wire reactive power are corresponding, calculates power consumption to make MCU according to number of pulses, interruption/Super-zero control module is used for exporting interrupt requests and voltage zero-cross pulse signal according to the control signal of register and communication module to MCU, make MCU judge whether enable interrupt event occurs according to the interrupt requests of input, carry out the disposal of some events according to the voltage zero-cross pulse signal of input.
In the present embodiment, the specific implementation of analog-to-digital conversion sample circuit and first, second, third electric parameter metering circuit illustrates see the embodiment of above-mentioned each circuit, repeats no more herein.
One of ordinary skill in the art will appreciate that: although the present invention is completed by hardware circuit, all or part of step realizing above-mentioned each embodiment of the method also can control relevant hardware by program command and come.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit, the description of each electric parameter metering circuit is only the explanation and improvement carried out measuring circuit representative in computation chip above, what it will be appreciated by those skilled in the art that is that method of the present invention can be used for all and above-mentioned measuring circuit and has in the circuit of analog structure to solve identical problem, although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or equivalent replacement is carried out to wherein some or all of technical characteristic, and these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. an analog-to-digital conversion sample circuit, is characterized in that, comprising: modulator, digital filtering and extracting unit, phase-correcting circuit; Described phase-correcting circuit comprises the first delay unit and the second delay unit, described first delay unit is connected with the input of the output of described modulator, described digital filtering and extracting unit respectively, and described second delay unit is connected with the output of described digital filtering and extracting unit.
2. analog-to-digital conversion sample circuit according to claim 1, it is characterized in that, described first delay unit comprises M time-delay trigger, described second delay unit comprises K time-delay trigger, M=(X-1) * L, X is the down-sampled multiple of described digital filtering and extracting unit, L is the figure place of the digital signal that described modulator exports, and K=Y*N, N are the figure place of the digital signal that described digital filtering and extracting unit export, Y is the time-delay trigger number that the bits per inch word signal in N position digital signal is corresponding respectively, M, K, X, N, L, Y are positive integer.
3. analog-to-digital conversion sample circuit according to claim 2, is characterized in that, L=1.
4. a computation chip, is characterized in that, comprising: three analog-to-digital conversion sample circuits, the first electric parameter metering circuit be connected with described three analog-to-digital conversion sample circuits respectively;
Described three analog-to-digital conversion sample circuits, for sampling to the voltage signal inputted, live wire current signal, neutral line current signal respectively, and the voltage signal obtained sampling, live wire current signal, neutral line current signal output to voltage output end, live wire current output terminal, neutral line current output respectively;
Described first electric parameter metering circuit, voltage signal, live wire current signal, neutral line current signal for obtaining according to described sampling calculate, and obtain the respective value of the phase angle of the respective value of the phase angle of the respective value of electric voltage frequency, voltage and live wire electric current, voltage and neutral line current.
5. computation chip according to claim 4, it is characterized in that, described first electric parameter metering circuit comprises: the first low pass filter, the second low pass filter, the 3rd low pass filter, the first zero-crossing pulse generator, the second zero-crossing pulse generator, the 3rd zero-crossing pulse generator, electric voltage frequency counter, first-phase angle counter, second-phase angle counter;
The input of described first low pass filter connects described voltage output end, the output of described first low pass filter connects the input of described first zero-crossing pulse generator, the output of described first zero-crossing pulse generator connects input, the first input end of first-phase angle counter, the first input end of second-phase angle counter of described electric voltage frequency counter, and the output of described electric voltage frequency counter is used for the respective value of output voltage frequency;
The input of described second low pass filter connects described live wire current output terminal, the output of described second low pass filter connects the input of described second zero-crossing pulse generator, the output of described second zero-crossing pulse generator connects the second input of described first-phase angle counter, and the output of described first-phase angle counter is used for the respective value of output voltage and live wire current phase angle;
The input of described 3rd low pass filter connects described neutral line current output, the output of described 3rd low pass filter connects the input of described 3rd zero-crossing pulse generator, the output of described 3rd zero-crossing pulse generator connects the second input of described second-phase angle counter, and the output of described second-phase angle counter is used for the respective value of output voltage and neutral line current phase angle.
6. computation chip according to claim 4, is characterized in that, also comprises: the second electric parameter metering circuit be connected with described three analog-to-digital conversion sample circuits respectively;
Described second electric parameter metering circuit comprises: the first counter, 90-degree phase shifter, the first data selector, the second data selector, the 3rd data selector, the 4th data selector, the first multiplier, the 4th low pass filter, first adder, the second multiplier, the first decoder;
First input end, the 3rd input of described first data selector all connect described live wire current output terminal, second input, the four-input terminal of described first data selector all connect described neutral line current output, and the output of described first data selector is connected to the first input end of described first multiplier;
First input end, second input of described second data selector all connect described voltage output end, 3rd input of described second data selector, four-input terminal all connect the output of described 90-degree phase shifter, the input of described 90-degree phase shifter connects described voltage output end, and the output of described second data selector is connected to the second input of described first multiplier;
The output of described first multiplier connects the input of described 4th low pass filter, and the output of described 4th low pass filter connects the first input end of described first adder;
The first input end of described 3rd data selector connects live wire active power compensatory control end, second input of described 3rd data selector connects zero line active power compensatory control end, 3rd input of described 3rd data selector connects live wire reactive power compensation control end, the four-input terminal of described 3rd data selector connects zero line reactive power compensation control end, and the output of described 3rd data selector is connected to the second input of described first adder;
The output of described first adder connects the first input end of described second multiplier;
The first input end of described 4th data selector connects live wire active power gain control end, second input section of described 4th data selector connects zero line active power gain control end, 3rd input of described 4th data selector connects live wire reactive power gain control end, the four-input terminal of described 4th data selector connects zero line reactive power gain control end, and the output of described 4th data selector is connected to the second input of described second multiplier;
The input of described first decoder connects the output of described second multiplier;
The control end of described first data selector, the second data selector, the 3rd data selector, the 4th data selector, the first decoder is all connected with the output of described first counter, and the first output of described first decoder, the second output, the 3rd output, the 4th output are successively for exporting respective value, the respective value of zero line active power, the respective value of live wire reactive power, the respective value of zero line reactive power of live wire active power.
7. computation chip according to claim 6, is characterized in that, also comprises: the 3rd electric parameter metering circuit be connected with described three analog-to-digital conversion sample circuits respectively;
Described 3rd electric parameter metering circuit comprises: the second counter, the 5th data selector, the 6th data selector, the 7th data selector, the 3rd multiplier, the 5th low pass filter, square root calculation device, second adder, the 4th multiplier, the second decoder;
The first input end of described 5th data selector connects live wire current output terminal, second input of described 5th data selector connects neutral line current output, 3rd input of described 5th data selector connects voltage output end, and the output of described 5th data selector connects two inputs of described first multiplier;
The output of described 3rd multiplier connects the input of described 5th low pass filter; The output of described 5th low pass bandpass filter connects described square root calculation device input;
Described square root calculation device output connects the first input end of described second adder;
The first input end of described 6th data selector connects live wire current effective value compensatory control end, second input of described 6th data selector connects neutral line current effective value compensatory control end, 3rd input of described 6th data selector connects voltage effective value compensatory control end, and the output of described 6th data selector connects the second input of described adder;
The output of described second adder connects the first input end of described 4th multiplier;
The first input end of described 7th data selector connects live wire current effective value gain control end, second input of described 7th data selector connects neutral line current rms gain control end, 3rd input of described 7th data selector connects voltage effective value gain control end, and the output of described 7th data selector connects the second input of described four multipliers;
The output of described 4th multiplier connects the input of described second decoder;
The control end of described 5th data selector, the 6th data selector, the 7th data selector, the second decoder is all connected with the output of described second counter, and the first output of described second decoder, the second output, the 3rd output are successively for exporting respective value, the respective value of neutral line current effective value, the respective value of voltage effective value of live wire current effective value.
8. according to described computation chip arbitrary in claim 4 ~ 7, it is characterized in that, described three analog-to-digital conversion sample circuits are as the analog-to-digital conversion sample circuit as described in arbitrary in claims 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310400984.8A CN104426548B (en) | 2013-09-05 | 2013-09-05 | A kind of analog-to-digital conversion sample circuit and computation chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310400984.8A CN104426548B (en) | 2013-09-05 | 2013-09-05 | A kind of analog-to-digital conversion sample circuit and computation chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104426548A true CN104426548A (en) | 2015-03-18 |
| CN104426548B CN104426548B (en) | 2017-07-28 |
Family
ID=52974618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310400984.8A Active CN104426548B (en) | 2013-09-05 | 2013-09-05 | A kind of analog-to-digital conversion sample circuit and computation chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104426548B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566204A (en) * | 2018-04-19 | 2018-09-21 | 南通大学 | A kind of adaptive power frequency type double integration A/D converter of integration period for accurate fields of measurement |
| CN109406873A (en) * | 2018-12-11 | 2019-03-01 | 上海贝岭股份有限公司 | Electric energy computation chip and intelligent electric meter |
| CN112286846A (en) * | 2019-07-25 | 2021-01-29 | 珠海格力电器股份有限公司 | Method and equipment for processing interrupt event |
| CN114325085A (en) * | 2021-12-30 | 2022-04-12 | 江苏林洋能源股份有限公司 | Electric energy meter and method supporting dynamic energy consumption management |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2650387Y (en) * | 2003-08-22 | 2004-10-20 | 金以城 | Self power-supply device for intelligent light-modulating switch |
| CN1964188A (en) * | 2006-12-06 | 2007-05-16 | 北京中星微电子有限公司 | A draw-off filter device of increment modulation type conversion |
| CN101803202A (en) * | 2007-03-28 | 2010-08-11 | 美国思睿逻辑有限公司 | Low-delay signal processing based on highly oversampled digital processing |
| US20110068961A1 (en) * | 2008-05-30 | 2011-03-24 | Olympus Corporation | A/d conversion device and servo control device |
| CN102714503A (en) * | 2011-01-20 | 2012-10-03 | 联发科技（新加坡）私人有限公司 | Continuous-time oversampled converter having enhanced immunity to noise |
| CN102751991A (en) * | 2012-07-30 | 2012-10-24 | 哈尔滨工业大学 | Delta-Sigma modulation principle based digital switching device and method for rotary transformer |
| CN102998525A (en) * | 2011-09-15 | 2013-03-27 | 无锡华润矽科微电子有限公司 | Multifunctional single-phase electric energy measuring circuit and automatic ammeter calibrating method thereof |
| CN103067019A (en) * | 2012-12-12 | 2013-04-24 | 天津大学 | Single-stage second-order front feeding Sigma-Delta modulation method and modulator |
-
2013
- 2013-09-05 CN CN201310400984.8A patent/CN104426548B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2650387Y (en) * | 2003-08-22 | 2004-10-20 | 金以城 | Self power-supply device for intelligent light-modulating switch |
| CN1964188A (en) * | 2006-12-06 | 2007-05-16 | 北京中星微电子有限公司 | A draw-off filter device of increment modulation type conversion |
| CN101803202A (en) * | 2007-03-28 | 2010-08-11 | 美国思睿逻辑有限公司 | Low-delay signal processing based on highly oversampled digital processing |
| US20110068961A1 (en) * | 2008-05-30 | 2011-03-24 | Olympus Corporation | A/d conversion device and servo control device |
| CN102714503A (en) * | 2011-01-20 | 2012-10-03 | 联发科技（新加坡）私人有限公司 | Continuous-time oversampled converter having enhanced immunity to noise |
| CN102998525A (en) * | 2011-09-15 | 2013-03-27 | 无锡华润矽科微电子有限公司 | Multifunctional single-phase electric energy measuring circuit and automatic ammeter calibrating method thereof |
| CN102751991A (en) * | 2012-07-30 | 2012-10-24 | 哈尔滨工业大学 | Delta-Sigma modulation principle based digital switching device and method for rotary transformer |
| CN103067019A (en) * | 2012-12-12 | 2013-04-24 | 天津大学 | Single-stage second-order front feeding Sigma-Delta modulation method and modulator |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566204A (en) * | 2018-04-19 | 2018-09-21 | 南通大学 | A kind of adaptive power frequency type double integration A/D converter of integration period for accurate fields of measurement |
| CN109406873A (en) * | 2018-12-11 | 2019-03-01 | 上海贝岭股份有限公司 | Electric energy computation chip and intelligent electric meter |
| CN112286846A (en) * | 2019-07-25 | 2021-01-29 | 珠海格力电器股份有限公司 | Method and equipment for processing interrupt event |
| CN114325085A (en) * | 2021-12-30 | 2022-04-12 | 江苏林洋能源股份有限公司 | Electric energy meter and method supporting dynamic energy consumption management |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104426548B (en) | 2017-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103257271B (en) | A kind of micro-capacitance sensor harmonic wave based on STM32F107VCT6 and m-Acetyl chlorophosphonazo pick-up unit and detection method | |
| CN104914304B (en) | Electric energy accurate measurement method and metering device under a kind of fluctuating load | |
| CN100550631C (en) | Pulse width modulation device | |
| CN203287435U (en) | A micro electrical network harmonic wave and inter-harmonic wave test apparatus based on an STM32F107VCT6 | |
| CN104426548A (en) | A/D (Analog/Digital) conversion sampling circuit and metering chip | |
| CN103852637B (en) | Intelligent electric meter with fundamental wave metering function and measurement method thereof | |
| CN103957005A (en) | Time-digital converter, full-digital phase-locked loop circuit and method | |
| CN101539596A (en) | Method for monitoring electric network frequency | |
| CN106610450A (en) | Single-phase electric energy metering chip | |
| CN103033675A (en) | Alternating current synchronous collecting system and achieving method thereof | |
| CN109194331A (en) | Electronic device and the method for correcting comparator in the electronic device | |
| CN103941622A (en) | Method for adopting high-accuracy pulse per second frequency multiplication to produce sampling pulse based on FPGA | |
| CN104111373A (en) | Metering method used for digital electric energy of intelligent substation | |
| CN202075344U (en) | Electric energy meter and electric energy correction system | |
| CN107102193A (en) | Signal noise processing unit in electric parameter metering process | |
| CN102928660A (en) | Reactive power measurement method based on finite impulse response (FIR) digital filter | |
| CN204679550U (en) | Electric energy accurate measuring device under a kind of fluctuating load | |
| CN107104674B (en) | Noise power estimation device in electric parameter measurement process | |
| CN205157646U (en) | Electric energy metering circuit based on voltage controlled oscillator | |
| CN201773147U (en) | Circuit for calculating virtual value of commercial electricity voltage | |
| CN108776259B (en) | Power analyzer based on digital bandwidth limiting technology | |
| CN103308759B (en) | Active power measurement method and system based on digital filtering | |
| CN115639400A (en) | High-precision alternating current electric energy metering method | |
| CN101110580A (en) | Hilbert filter used for power computing | |
| CN105425194B (en) | A kind of setting method of the meter constant of electric instrument |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 200235 Shanghai city Xuhui District Longcao Road No. 299 Tianhua Information Technology Park Building 2 floor A block 5 Applicant after: SHANGHAI EASTSOFT MICROELECTRONICS Co.,Ltd. Address before: 200235 Shanghai city Xuhui District Longcao Road No. 299 Tianhua Information Technology Park Building 2 floor A block 5 Applicant before: SHANGHAI HAIER INTEGRATED CIRCUIT Co.,Ltd. |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230913 Address after: 200235 5th floor, block a, building 2, Tianhua Information Technology Park, 299 Longcao Road, Xuhui District, Shanghai Patentee after: SHANGHAI EASTSOFT MICROELECTRONICS Co.,Ltd. Patentee after: QINGDAO EASTSOFT COMMUNICATION TECHNOLOGY Co.,Ltd. Address before: 200235 5th floor, block a, building 2, Tianhua Information Technology Park, 299 Longcao Road, Xuhui District, Shanghai Patentee before: SHANGHAI EASTSOFT MICROELECTRONICS Co.,Ltd. |