CN104425634A - Passivated emitter back electrode silicon crystal solar cell and manufacturing method thereof - Google Patents
Passivated emitter back electrode silicon crystal solar cell and manufacturing method thereof Download PDFInfo
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- CN104425634A CN104425634A CN201310728746.XA CN201310728746A CN104425634A CN 104425634 A CN104425634 A CN 104425634A CN 201310728746 A CN201310728746 A CN 201310728746A CN 104425634 A CN104425634 A CN 104425634A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 144
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 139
- 239000010703 silicon Substances 0.000 title claims abstract description 139
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000013078 crystal Substances 0.000 title abstract 2
- 238000002161 passivation Methods 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 44
- 238000003466 welding Methods 0.000 claims description 32
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 124
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 24
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- 239000004332 silver Substances 0.000 description 22
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
- H01L31/02245—Electrode arrangements specially adapted for back-contact solar cells for metallisation wrap-through [MWT] type solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention provides a passivated emitter back electrode silicon crystal solar cell and a manufacturing method thereof. The P-type silicon wafer is provided with a main grid line region and other regions except the main grid line region on the back surface. The back dielectric layer is provided with a first opening pattern positioned in the main grid line region and a second opening pattern positioned in other regions, wherein the first opening pattern and the second opening pattern expose the P-type silicon wafer, and the first opening pattern of the back dielectric layer is different from the second opening pattern.
Description
Technical field
The invention relates to a kind of solar cell, and relate to a kind of passivation emitter back electrode silicon wafer solar cell and manufacture method thereof especially.
Background technology
Solar cell is a kind of photovoltaic element (photovoltaic device) of power conversion.The basic structure of typical solar cell can be divided into substrate, P-N diode, anti-reflecting layer and metal electrode four major parts.In simple terms, the operation principle of solar cell is that P-N diode converts solar energy to electron hole pair, then conducts electric energy through positive and negative electrode.
In the prior art, propose one and there is high efficiency passivation emitter back electrode silicon wafer solar cell (passivated emitter rear contact solar cell, hereinafter referred to as PERC), it mainly forms dielectric layer on the back of the substrate, formation opening is removed in dielectric layer local, and wire mark aluminium paste and silver slurry on dielectric layer overleaf, form aluminium electrode finally by high temperature co-firing processing procedure and silver electrode is used as backplate.But in the processing procedure of passivation emitter back electrode silicon wafer solar cell, substrate back must make the backside surface of substrate level and smooth through a single-sided polishing processing procedure, dielectric layer is made to be attached to the back side of substrate to play the effect extending the carrier time-to-live.But thus, when multiple silicon wafer solar cell is interconnected to form silicon wafer photovoltaic module with welding rod and back silver electrode, exist between back silver electrode and substrate and between back silver electrode and dielectric layer because of aforementioned polished backside processing procedure and adhere to hypodynamic problem, and photovoltaic module is faced, and reliability declines, the low problem of yield.
Summary of the invention
The invention provides a kind of passivation emitter back electrode silicon wafer solar cell and manufacture method thereof, the adhesive force of passivation emitter back electrode silicon wafer solar cell in subsequent components processing procedure between back silver electrode and welding rod and between back silver electrode and substrate can be strengthened thus, come off from back silver electrode place when avoiding passivation emitter back electrode silicon wafer solar cell to be concatenated into passivation emitter back electrode silicon wafer photovoltaic module, increase reliability and the yield of photovoltaic module.
The present invention proposes a kind of passivation emitter back electrode silicon wafer solar cell, and it comprises P-type silicon sheet, N-type doped layer, front dielectric layer, front electrode, backside dielectric layer, the first backplate and the second backplate.P-type silicon sheet has sensitive surface and the back side, and the back side has main gate line region and other regions except main gate line region.N-type doped layer, front dielectric layer and front electrode are positioned on the sensitive surface of P-type silicon sheet.Backside dielectric layer is positioned on the back side of P-type silicon sheet, and backside dielectric layer has the first patterns of openings being positioned at main gate line region and the second patterns of openings being positioned at other regions, and wherein the first patterns of openings and the second patterns of openings expose P-type silicon sheet.First backplate is positioned in backside dielectric layer, and inserts in the first patterns of openings.Second backplate is positioned in backside dielectric layer, and inserts in the second patterns of openings.It should be noted that the first patterns of openings of backside dielectric layer is different from the second patterns of openings.
The present invention separately proposes a kind of manufacture method of passivation emitter back electrode silicon wafer solar cell, and it comprises the following steps.First, provide P-type silicon sheet, it has sensitive surface and the back side, and wherein P-type silicon sheet has main gate line region and other regions except main gate line region on the back side.Then, the sensitive surface of P-type silicon sheet is formed N-type doped layer, and form front dielectric layer on N-type doped layer.Then, the back side of P-type silicon sheet forms backside dielectric layer, to make the main gate line region that is positioned at of backside dielectric layer form the first patterns of openings, and other regions that are positioned at of dielectric layer form the second patterns of openings overleaf.It should be noted that the first patterns of openings is different from the second patterns of openings, and the first patterns of openings and the second patterns of openings expose P-type silicon sheet.Afterwards, front dielectric layer forms front electrode, dielectric layer is formed the first backplate overleaf, insert in the first patterns of openings to make the first backplate, and overleaf dielectric layer forms the second backplate, insert in the second patterns of openings to make the second backplate.Finally, the manufacture of passivation emitter back electrode silicon wafer solar cell is completed via high temperature co-firing processing procedure.
In an embodiment of the present invention, the first patterns of openings comprises multiple first sub pattern independent of each other, and the second patterns of openings comprises multiple second sub pattern independent of each other.
In an embodiment of the present invention, the first width of the first above-mentioned sub pattern is different from the second width of the second sub pattern.
In an embodiment of the present invention, the first above-mentioned sub pattern and the second sub pattern are respectively strip pattern.
In an embodiment of the present invention, the first spacing wherein between wantonly two adjacent first sub pattern is different from the second spacing between wantonly two adjacent second sub pattern.For example, the first spacing is such as less than the second spacing.
In an embodiment of the present invention, the first above-mentioned sub pattern is such as the distributional pattern presenting dotted line in main gate line region, the second above-mentioned sub pattern is such as the distributional pattern presenting solid line in other above-mentioned regions, and the ratio of the first sub pattern shared by main gate line region is such as be less than the second sub pattern ratio shared in other regions.
In an embodiment of the present invention, be such as that the shape of the first sub pattern is different from the second sub pattern.
In an embodiment of the present invention, the first above-mentioned sub pattern and the second sub pattern can be line respectively, point, line segment or its combine.
In an embodiment of the present invention, above-mentioned passivation emitter back electrode silicon wafer solar cell can comprise the welding rod be connected with the first backplate further.
In an embodiment of the present invention, above-mentioned p-type silicon chip comprises the silicon chip of boron doping or gallium doping.
In an embodiment of the present invention, the first patterns of openings in above-mentioned backside dielectric layer and the gross area of the second patterns of openings are between 0.5% to 15% relative to the ratio of the area at the back side.
In an embodiment of the present invention, above-mentioned backside dielectric layer pattern is such as Al
xo
y, SiO
2, Si
xn
y, Si
xn
yh
z, Si
xo
yn
zor the single or multiple lift structure of SiC combination.
In an embodiment of the present invention, above-mentioned front dielectric layer is such as SiO
2, Si
xn
y, Si
xn
yh
z, Si
xo
yn
zor the single or multiple lift structure of SiC combination.
In an embodiment of the present invention, the region that above-mentioned N-type doped layer corresponds to front electrode can be high-concentration dopant V group element (such as: phosphorus (P), arsenic (As)), and its sheet resistance is such as being less than or equal to 70ohm/sq..
In an embodiment of the present invention, the region that above-mentioned N-type doped layer corresponds to except front electrode can be low concentration doping V group element (such as: phosphorus (P), arsenic (As)), and its sheet resistance is such as being greater than 70ohm/sq..
In an embodiment of the present invention, above-mentioned N-type doped layer can be the part in the region corresponded to beyond front electrode is high-concentration dopant V group element (such as: phosphorus (P), arsenic (As)).
The present invention reintroduces a kind of passivation emitter back electrode silicon wafer solar cell, and it comprises P-type silicon sheet, N-type doped layer, front dielectric layer, front electrode, backside dielectric layer, the first backplate and the second backplate.P-type silicon sheet has sensitive surface and the back side, and the back side has main gate line region and other regions except main gate line region.N-type doped layer, front dielectric layer and front electrode are positioned on the sensitive surface of P-type silicon sheet.Backside dielectric layer is positioned on the back side of P-type silicon sheet, and backside dielectric layer is different from backside dielectric layer at the pattern being positioned at main gate line region and is being positioned at the pattern in other regions.First backplate is positioned in backside dielectric layer.Second backplate is positioned in backside dielectric layer, and insert backside dielectric layer be positioned at other zone maps described.
In an embodiment of the present invention, above-mentioned backside dielectric layer is being positioned at main gate line region for comprehensively covering P-type silicon sheet, and backside dielectric layer has patterns of openings being positioned at other regions.
The present invention proposes a kind of photovoltaic module, and it comprises multiple passivation emitter back electrode silicon wafer solar cell described above and welding rod, and wherein welding rod is electrically connected between two adjacent passivation emitter back electrode silicon wafer solar cells.
In an embodiment of the present invention, above-mentioned front electrode, the first backplate and the second backplate are formed via high temperature co-firing processing procedure.
In an embodiment of the present invention, the maximum temperature of above-mentioned high temperature co-firing processing procedure is greater than 600 DEG C.
Based on above-mentioned, by by the pattern being positioned at main gate line region of backside dielectric layer and be positioned at other regions design for not identical, effectively can strengthen the adhesive force of passivation emitter back electrode silicon wafer solar cell in subsequent components processing procedure between back silver electrode and welding rod and between back silver electrode and substrate, come off from back silver electrode place when avoiding passivation emitter back electrode silicon wafer solar cell to be concatenated into passivation emitter back electrode silicon wafer photovoltaic module, increase reliability and the yield of photovoltaic module.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic perspective view of a kind of passivation emitter back electrode silicon wafer solar cell of the first embodiment of the present invention;
Fig. 2 is the schematic diagram along the A-A' section in Fig. 1;
Fig. 3 is the back side top view of a kind of passivation emitter back electrode silicon wafer solar cell of the first embodiment of the present invention;
Fig. 4 A be in Fig. 3 rear surface of solar cell top view at the partial enlarged drawing of the first embodiment of part B;
Fig. 4 B is the partial enlarged drawing of the rear surface of solar cell top view in Fig. 3 in the second embodiment of part B;
Fig. 4 C is the partial enlarged drawing of the rear surface of solar cell top view in Fig. 3 in the 3rd embodiment of part B;
Fig. 4 D is the partial enlarged drawing of the rear surface of solar cell top view in Fig. 3 in the 4th embodiment of part B;
Fig. 5 A to Fig. 5 C is the schematic diagram of the manufacture method of a kind of passivation emitter back electrode silicon wafer solar cell of the first embodiment of the present invention;
Fig. 6 is the photovoltaic module schematic diagram of first embodiment of the invention.
Description of reference numerals:
10: photovoltaic module;
100: solar cell;
110:P type silicon chip;
120:N type doped layer;
130: front dielectric layer;
140: front electrode constituent;
140a: front electrode;
150,250,350,450: backside dielectric layer;
152,252,352: the first patterns of openings;
154,254,354,454: the second patterns of openings;
152a, 252a, 352a: the first sub pattern;
154a, 254a, 354a, 454a: the second sub pattern;
160: the first backplate constituents;
160a: the first backplate;
170: the second backplate constituents;
170a: the second backplate;
180: welding rod;
P1: the first spacing;
P2: the second spacing;
R1: main gate line region;
R2: other regions;
S1: sensitive surface;
S2: the back side;
W1: the first width;
W2: the second width.
Embodiment
Fig. 1 is the schematic perspective view of a kind of passivation emitter back electrode silicon wafer solar cell of the first embodiment of the present invention.Passivation emitter back electrode silicon wafer solar cell is hereinafter referred to as " solar cell ".Fig. 2 is the schematic diagram along the A-A' section in Fig. 1.
Please refer to Fig. 1 and Fig. 2, the solar cell 100 of the present embodiment comprises P-type silicon sheet 110, N-type doped layer 120, front dielectric layer 130, front electrode 140a, backside dielectric layer 150, first backplate 160a and the second backplate 170a.In detail, P-type silicon sheet 110 has sensitive surface S1 respect to one another and back side S2, sequentially comprises N-type doped layer 120, front dielectric layer 130 and front electrode 140a on the sensitive surface S1 of P-type silicon sheet 110.The back side S2 of P-type silicon sheet 110 has backside dielectric layer 150, the first backplate 160a and the second backplate 170a, and backside dielectric layer 150 have the first patterns of openings 152 and the second patterns of openings 154.
As shown in Figure 1, in the present embodiment, the sensitive surface S1 of P-type silicon sheet 110 has the structure of such as rough surface, pyramid (pyramid texturing) or inverted pyramid type (inverted-pyramid texturing), to reduce reflectivity when sunlight or light enter solar cell 100, increase the utilance of sunlight thus.
In the present embodiment, N-type doped layer 120 is positioned on the sensitive surface S1 of P-type silicon sheet 110, and front dielectric layer 130 is positioned on N-type doped layer 120.Front electrode 140a is positioned on front dielectric layer 130.
As shown in Figures 1 and 2, backside dielectric layer 150 is positioned on the back side S2 of P-type silicon sheet 110, and the backside dielectric layer 150 of the present embodiment is for single layer structure, in other embodiments, backside dielectric layer 150 also can be sandwich construction, in solar cell 100, when solar light irradiation P-type silicon sheet 110, the inside of P-type silicon sheet 110 can produce electron hole pair (carrier) simultaneously, and electronics and the hole generation current through both positive and negative polarity respectively.In passivation emitter back electrode silicon wafer solar cell of the present invention, the carrier produced can be avoided because of the protection of backside dielectric layer combining (recombined) again, and then extends the survival rate of carrier.Specifically, backside dielectric layer 150 has different patterns in different regions.
Fig. 3 is the back side top view of a kind of passivation emitter back electrode silicon wafer solar cell of the first embodiment of the present invention.Please refer to Fig. 3, the back side S2 of P-type silicon sheet 110 can be divided into main gate line region R1 and other regions R2 except the R1 of main gate line region, wherein main gate line region R1 is be the region forming main gate line (bus-bar) predetermined in solar cell 100.In the present embodiment, the back side S2 of P-type silicon sheet 110 is divided into three main gate line region R1 parallel to each other, in other embodiments, also can optionally be adjusted to two or more.In addition, main gate line region R1 other positions on the back side S2 of P-type silicon sheet 110 also visible product demand adjust.The present invention is different from the pattern of backside dielectric layer 150 at other regions R2 except the R1 of main gate line region by making backside dielectric layer 150 at the pattern of main gate line region R1, solar cell 100 can be made when being concatenated into and forming photovoltaic module thus effectively to increase adhesive force between adhesive force between the back silver electrode of solar cell and welding rod, the back silver electrode of solar cell and P-type silicon sheet 110, and then promote reliability and the yield of photovoltaic module.Hereafter will illustrate in detail backside dielectric layer 150.
In addition, please refer to Fig. 1 and Fig. 2, the first backplate 160a and the second backplate 170a is positioned in backside dielectric layer 150, and the second backplate 170a and the first backplate 160a is electrically connected.Specifically, in the present embodiment, the carrier from the second backplate 170a is collected to the first backplate 160a, and the electric current that collected carrier produces outwards conducts by the first backplate 160a again.In other words, the first backplate 160a of the present embodiment is as bus electrode (bus-bar electrode), and the second backplate 170a is then as finger electrode (finger electrode).
Furthermore, in the present embodiment, when multiple solar cell 100 is connected in series, solar cell 100 also can comprise welding rod 180, welding rod 180 is connected, outwards to be conducted by the electric current of the first backplate 160a being collected into the bus electrode of solar cell 100 further with the first backplate 160a as bus electrode.
It should be noted that, the back side is on purpose divided into main gate line region and other regions except main gate line region by solar cell of the present invention, make the pattern of backside dielectric layer in main gate line region and the difference of the pattern in other regions, be there is in zones of different by backside dielectric layer the technological means of different pattern distribution, the different form (morphology) being able to from the welding rod of back silver Electrode connection in successive process be formed because of different pattern between zones of different by the back side is made to distribute to increase back silver electrode pair P-type silicon sheet and the adhesive force to welding rod.In detail, making backside dielectric layer have the execution mode of different pattern in zones of different, the width of pattern, quantity, distribution density, figure etc. can be changed, illustrating illustrating respectively in detail below:
[the first embodiment]
Fig. 4 A is the partial enlarged drawing of the rear surface of solar cell top view in Fig. 3 in the first embodiment of part B.Please refer in the lump with reference to Fig. 1, Fig. 2 and Fig. 4 A, in the present embodiment, making backside dielectric layer 150 be different from the aspect of backside dielectric layer 150 at the pattern of other regions R2 except the R1 of main gate line region at the pattern of main gate line region R1, such as, is the width changing pattern.
Please with reference to Fig. 1, Fig. 2 and Fig. 4 A, specifically, backside dielectric layer 150 is positioned on the back side S2 of P-type silicon sheet 110, and backside dielectric layer 150 has the first patterns of openings 152 being positioned at main gate line region R1 and the second patterns of openings 154, first patterns of openings 152 being positioned at other regions R2 and the second patterns of openings 154 exposes P-type silicon sheet 110.In addition, the first backplate 160a is positioned in backside dielectric layer 150, and inserts in the first patterns of openings 152.Second backplate 170a is positioned in backside dielectric layer 150, and inserts in the second patterns of openings 154.
Please refer to Fig. 4 A, in the present embodiment, the width being positioned at first patterns of openings 152 of main gate line region R1 is different from the second patterns of openings 154 being positioned at other regions R2.In detail, in the region of partial enlargement overleaf, as shown in this case 4A, first patterns of openings 152 comprises two the first sub pattern 152a independent of each other, and the second patterns of openings 154 comprises four the second sub pattern 154a independent of each other, wherein these first sub pattern 152a and these the second sub pattern 154a are parallel to each other substantially.It should be noted that, in the present embodiment, the first sub pattern 152a and the second sub pattern 154a is all strip pattern, in other embodiments, the figure of the first sub pattern 152a and the second sub pattern 154a also can be line, point, line segment or its combine, the present invention is not as limit.
In addition, as shown in Figure 4 A, first width W 1 of the first sub pattern 152a is different from second width W 2 of the second sub pattern 154a, it is such as specifically the second width W 2 that first width W 1 of the first sub pattern 152a is greater than the second sub pattern 154a, certainly first width W 1 of the first sub pattern 152a also can be made in other embodiments to be less than second width W 2 of the second sub pattern 154a, the effect increasing adhesive force can be reached equally, refer to embodiment hereinafter.
Furthermore, in a first embodiment, by adjusting first width W 1 of the first sub pattern 152a, make its concrete aspect different from second width W 2 of the second sub pattern 154a, realize the technological means that the first patterns of openings 152 that backside dielectric layer 150 is positioned at main gate line region R1 is different from the second patterns of openings 154 being positioned at other regions R2 thus.Thus, by first patterns of openings 152 being positioned at main gate line region R1 of backside dielectric layer 150 is had different fractions distribution from the second patterns of openings 154 being positioned at other regions R2, effectively can strengthen the adhesive force of passivation emitter back electrode silicon wafer solar cell in subsequent components processing procedure between the first backplate 160a and welding rod 180 and between the first backplate 160a and P-type silicon sheet 110, come off from the first backplate 160a place when avoiding solar cell 100 to be concatenated into photovoltaic module 10, under the prerequisite making the efficiency of solar cell remain certain, and increase reliability and the yield of photovoltaic module further.
It is worth mentioning that, the first patterns of openings 152 of backside dielectric layer 150 and the gross area of the second patterns of openings 154 are preferably between 0.5% to 15% relative to the ratio of the area of back side S2, and solar cell can be made thus to play best efficiency.
Certainly, except above-mentioned first embodiment, also otherwise can realize the pattern that backside dielectric layer is positioned at main gate line region and be different from the technological means that it is positioned at the pattern in other regions.Certainly, designer also can according to product actual demand with the change width of the first embodiment and by the part or all of technology of following embodiment, further to strengthen the adhesive force between back silver electrode and welding rod and between back silver electrode and silicon chip.Also or, designer also only can select any one technology in following embodiment, can play enhancing adhesive force, improves the effect of photovoltaic module reliability and yield.
[the second embodiment]
Fig. 4 B is the partial enlarged drawing of the rear surface of solar cell top view in Fig. 3 in the second embodiment of part B.
The backside dielectric layer 250 of the present embodiment and the backside dielectric layer 150 of the first embodiment similar, only difference is that the backside dielectric layer 250 of the present embodiment is that distribution density (i.e. quantity) by changing the first patterns of openings 252 realizes the pattern that backside dielectric layer is positioned at main gate line region and is different from the technological means that it is positioned at the pattern in other regions.
Specifically, in the present embodiment, in the scope that the main gate line region R1 with the first embodiment is identical, to increase the quantity of the first patterns of openings 252 but not change width to replace in the first embodiment the practice increasing by the first patterns of openings 252 width.In detail, first patterns of openings 252 of the present embodiment comprises four the first sub pattern 252a independent of each other, and the second patterns of openings 254 comprises four the second sub pattern 254a independent of each other, wherein these first sub pattern 252a and the second sub pattern 254a are respectively strip pattern and parallel to each other substantially each other.
In addition, in the present invention, also the quantity of the first sub pattern 252a and the second sub pattern 254a can be adjusted depending on demand, the present invention is not as limit, as long as the first sub pattern 252a can be made different from the distribution density of the second sub pattern 254a, namely reach the effect strengthening passivation emitter back electrode silicon wafer solar cell the first backplate and welding rod and the adhesive force between the first backplate and P-type silicon sheet in subsequent components processing procedure.
More specifically, as shown in Figure 4 B, the first spacing P1 in the present embodiment between wantonly two adjacent first sub pattern 252a is less than the second spacing P2 between wantonly two adjacent second sub pattern 254a, certainly the first spacing P1 also can be made in other embodiments to be greater than the second spacing P2, the effect increasing adhesive force can be reached equally.
In other words, in second embodiment of the present invention, be by wantonly two adjacent first sub pattern 252a between the first spacing P1 be different from the second spacing P2 between wantonly two adjacent second sub pattern 254a, the first patterns of openings 252 being positioned at main gate line region R1 realizing backside dielectric layer 250 is thus different from the technological means of the second patterns of openings 254 being positioned at other regions R2.Thus, effectively can strengthen passivation emitter back electrode silicon wafer solar cell the first backplate and welding rod and the adhesive force between the first backplate and P-type silicon sheet in subsequent components processing procedure, come off from the first backplate place when avoiding solar cell to be concatenated into photovoltaic module, under the prerequisite making the efficiency of solar cell remain certain, and increase reliability and the yield of photovoltaic module further.
It is worth mentioning that, although in the backside dielectric layer 250 of the present embodiment, adopt separately the mode of the quantity of change first patterns of openings to be described, but designer also visible product demand and and with the mode of the width of change first patterns of openings of previous embodiment play enhancing adhesive force effect, improve the effect of photovoltaic module reliability and yield, the present invention is not as limit.
[the 3rd embodiment]
Fig. 4 C is the partial enlarged drawing of the rear surface of solar cell top view in Fig. 3 in the 3rd embodiment of part B.
The backside dielectric layer 350 of the present embodiment and the backside dielectric layer 150 of the first embodiment similar, only difference is that the backside dielectric layer 350 of the present embodiment is that figure by changing the first patterns of openings 352 realizes the pattern that backside dielectric layer is positioned at main gate line region and is different from the technological means that it is positioned at the pattern in other regions.
Specifically, in the scope that the main gate line region R1 with the first embodiment is identical, to change the shape of the first patterns of openings 352 but the mode not changing width and quantity replaces increasing in the first embodiment the practice of the first patterns of openings 152 width.In detail, first patterns of openings 352 of the present embodiment comprises multiple the first sub pattern 352a in line segment shape, and the second patterns of openings 354 comprises four the second sub pattern 354a in strip independent of one another.Macroscopic, the first sub pattern 352a in line segment shape of the present embodiment presents the distributional pattern of the strip pattern as two dotted lines in the R1 of main gate line region, and the second sub pattern 354a presents four distributional patterns as the strip pattern of solid line in the R2 of other regions.
It is worth mentioning that, the ratio that the first sub pattern 352a of the present embodiment is shared in the R1 of main gate line region is less than the second sub pattern 354a ratio shared in the R2 of other regions, the gross area of the backside dielectric layer 150 of back side S2 can be made thus to increase, namely the effect extending the carrier time-to-live increases, and then increases the efficiency of solar cell.
In other words, in the third embodiment of the present invention, that shape by adjusting the first sub pattern 352a is different from the shape of the second sub pattern 354a, the first patterns of openings 352 being positioned at main gate line region R1 to realize backside dielectric layer 350 is different from the second patterns of openings 354 being positioned at other regions R2, the first backplate and welding rod and the adhesive force between the first backplate and P-type silicon sheet can be maintained thus, also, namely under the maintenance reliability of photovoltaic module and the prerequisite of yield, the efficiency of solar cell is increased further.
It is worth mentioning that, although in the backside dielectric layer 350 of the present embodiment, adopt separately the mode of the figure of change first patterns of openings to be described, but designer also visible product demand and and play enhancing adhesive force by the mode such as width, distributed quantity, spacing of change first patterns of openings of previous embodiment, improve the effect of photovoltaic module reliability and yield, the present invention is not as limit.
[the 4th embodiment]
Fig. 4 D is the partial enlarged drawing of the rear surface of solar cell top view in Fig. 3 in the 4th embodiment of part B.
The backside dielectric layer 450 of the present embodiment is being positioned at main gate line region R1 for covering P-type silicon sheet comprehensively.Specifically, backside dielectric layer 450 does not have opening being positioned at main gate line region R1.In contrast, backside dielectric layer 450 is being positioned at second patterns of openings 454 of other regions R2, such as, it is the second patterns of openings 454 of previous embodiment.Specifically, the second patterns of openings 454 comprises multiple the second rounded sub pattern 454a.These second sub pattern 454a are macroscopically presenting many straight lines be made up of multiple point respectively distributional pattern side by side each other in the R2 of other regions.
In other words, in the third embodiment of the present invention, not there is opening by making the backside dielectric layer 450 in the R1 of main gate line region, and make the second patterns of openings 454 second sub pattern 454a being positioned at other regions R2 rounded, therefore, as above-described embodiment, the gross area of the backside dielectric layer at the back side can be made thus to increase, namely the effect extending the carrier time-to-live increases, and then increases the efficiency of solar cell.
It is worth mentioning that, although in the backside dielectric layer 450 of the present embodiment, make the backside dielectric layer 450 in the R1 of main gate line region not have opening and be described by the mode of the figure of change second patterns of openings, but designer also visible product demand and and to improve the efficiency of solar cell by the mode such as width, distributed quantity, spacing, figure of change second patterns of openings of previous embodiment, the present invention is not as limit.
The manufacture method of silicon wafer solar cell of the present invention is further illustrated below for aforementioned first embodiment.
Fig. 5 A to Fig. 5 C is the schematic diagram of the manufacture method of a kind of passivation emitter back electrode silicon wafer solar cell of the first embodiment of the present invention.
Please refer to Fig. 5 A.First, provide P-type silicon sheet 110, it has sensitive surface S1 and back side S2.P-type silicon sheet 110 overleaf S2 has main gate line region R1 and other regions R2 (as shown in Figure 3) except the R1 of main gate line region.In addition, P-type silicon sheet 110 is such as the silicon chip of boron doping or gallium doping.Then, N-type doping (such as the V group element such as phosphorus doping or arsenic doping) is carried out, to form N-type doped layer 120 on sensitive surface S1 at the sensitive surface S1 of P-type silicon sheet 110 with such as thermal diffusion (thermal diffusion) or ionic-implantation (ion implantation).
Then, with such as chemical vapour deposition technique (Chemical Vapor Deposition, or plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition CVD), PECVD) on the N-type doped layer 120 of sensitive surface S1, form front dielectric layer 130, wherein front dielectric layer 130 is such as SiO
2, Si
xn
y, Si
xn
yh
z, Si
xo
yn
zor the single or multiple lift structure of SiC combination.
Then, form backside dielectric layer 150 with chemical vapour deposition technique or plasma enhanced chemical vapor deposition method at the back side S2 of P-type silicon sheet 110, wherein backside dielectric layer 150 is such as Al
xo
y, SiO
2, Si
xn
y, Si
xn
yh
z, Si
xo
yn
zor the single or multiple lift structure of SiC combination.
Next, please refer to Fig. 5 B, then patterning is carried out to backside dielectric layer 150, the first patterns of openings 152 is formed with the main gate line region R1 that is positioned at of dielectric layer 150 overleaf, and other regions R2 that is positioned at of dielectric layer 150 forms the second patterns of openings 154 overleaf, wherein the first patterns of openings 152 and the second patterns of openings 154 expose P-type silicon sheet 110.It should be noted that the method for carrying out patterning to backside dielectric layer 150 comprises the methods such as etching glue method (etching paste method), laser-etching process (laser-etchingmethod), photolithography (photolithography method).
Then, please refer to Fig. 5 C, front dielectric layer 130 is formed front electrode constituent 140, for example, such as, is wire mark one front electrode constituent 140, and wherein front electrode constituent 140 is such as silver slurry.
Then, the first backplate constituent 160 and the second backplate constituent 170 are distinguished wire mark in the first patterns of openings 152 and in the second patterns of openings 154.First backplate constituent 160 is such as silver slurry, and the second backplate constituent 170 is such as aluminium paste.
Then, high temperature co-firing processing procedure is carried out to the said structure being formed with front electrode constituent 140, first backplate constituent 160 and the second backplate constituent 170, to form front electrode 140a, the first backplate 160a and the second backplate 170a respectively.It should be noted that the maximum temperature of high temperature co-firing processing procedure is greater than 600 DEG C.
Then, be welded on by welding rod 180 on first backplate 160a, welding rod 180 and the first backplate 160a and the second backplate 170a contact with each other thus.Form the structure of earlier figures 1, the solar cell 100 shown in Fig. 2.
It should be noted that N-type doped layer 120 correspondence can be high concentration phosphorus doping in the region of front electrode 140a, and its sheet resistance is for being less than or equal to 70ohm/sq..Again, N-type doped layer 120 region corresponded to except front electrode 140a can be low phosphorus doping, and its sheet resistance is for being greater than 70ohm/sq..In addition, N-type doped layer 120 also can be high concentration phosphorus doping corresponding to the part in the region beyond front electrode 140a.
Fig. 6 is the photovoltaic module schematic diagram of first embodiment of the invention.Photovoltaic module 10 can comprise multiple solar cell 100 and welding rod 180, and wherein welding rod 180 is electrically connected between two adjacent solar cells 100.Specifically, the two ends of welding rod 180 link the electrode of solar cell 100 and the electrode of another solar cell 100 respectively.Thus, welding rod 180 just can collect the electric current of self-electrode, and conducts the current to another solar cell 100.
< solar cell evaluation >
In the following example, evaluate passivation emitter back electrode silicon wafer solar cell, its result is as shown in table 1 and table 2.
-example 1-
Conductive paste A is made up of silver powder (50 ~ 60wt.%), ester alcohol (40 ~ 50wt.%), resin (1 ~ 10wt.%) and glass dust A (1 ~ 10wt.%), and its result is as shown in table 1.
-example 2-
Conductive paste B is made up of silver powder (50 ~ 60wt.%), ester alcohol (40 ~ 50wt.%), resin (1 ~ 10wt.%) and glass dust B (1 ~ 10wt.%), and its result is as shown in table 2.
[evaluation method]
-efficiency-
Use efficiency of solar cell measurement platform, the passivation emitter back electrode silicon wafer solar cell for different embodiment carries out battery efficiency assessment.The QuickSun-120CA type efficiency of solar cell measuring machine of efficiency of solar cell measurement platform manufactured by endeas.
-tensile test-
By welding rod (Ribbon) (tin-coated copper strip, its zinc-plated component ratio is Sn/Pb/Ag=62%/36%/2%) preheating at 60 DEG C, then welding rod is welded in backplate (as shown in Figure 1) by the welding gun being about 360 DEG C with temperature.Then, carry out tensile test with the opposite direction (180 degree) relative to substrate, measure and welding rod is separated required pulling force with surface electrode, wherein the translational speed of puller system is 20mm/sec, and pulling force is higher, and to represent adhesive force higher.
[evaluation result]
Table 1 and table 2 illustrate using conductive paste A and conductive paste B as the first backplate respectively, and based on above-mentioned first embodiment, measure and change etching area (i.e. first patterns of openings area and second patterns of openings area) ratio (%) efficiency on solar cell of backside dielectric layer in main gate line region and the impact of pulling force.
Please refer to table 1 and table 2, backside dielectric layer is when the etching area ratio (%) in main gate line region is greater than 1%, though the area of first patterns of openings of backside dielectric layer in main gate line region be greater than, the area of the second patterns of openings be less than or equal in other regions, regular pulling force is all greater than 1 (denominator of regular pulling force is the minimum requirements of general solar cell pulling force).Which illustrate by first patterns of openings being positioned at main gate line region of backside dielectric layer and the second patterns of openings of being positioned at other regions are designed to not identical, the effect of photovoltaic module reliability and yield can be met.Again when backside dielectric layer increases at the etching area (i.e. the area of the first patterns of openings) ratio (%) in main gate line region, though the efficiency of solar cell reduces a little but still can maintain certain level, and pulling force promotes significantly, the bond area represented between the first backplate and backside dielectric layer and between the first backplate and P-type silicon sheet increases, to promote the effect of photovoltaic module reliability and yield.Therefore can, according to different to the demand of pulling force, affect under battery efficiency not serious, the first patterns of openings ratio in adjustment main gate line region.
In addition, use the pulling force result of conductive paste B higher than conductive paste A, represent conductive paste B and and backside dielectric layer between and have good adhesive force between conductive paste B and P-type silicon sheet.
Table 1 conductive paste A
Table 2 conductive paste B
Comprehensively above-mentioned, by first patterns of openings being positioned at main gate line region of backside dielectric layer and the second patterns of openings of being positioned at other regions are designed to not identical in embodiments of the invention, effectively can strengthen passivation emitter back electrode silicon wafer solar cell back silver electrode and welding rod and the adhesive force between back silver electrode and substrate in subsequent components processing procedure, come off from back silver electrode place when avoiding passivation emitter back electrode silicon wafer solar cell to be concatenated into passivation emitter back electrode silicon wafer photovoltaic module, under the efficiency of solar cell can be made to maintain the prerequisite of certain level, effectively increase reliability and the yield of photovoltaic module.Further, in another embodiment of the invention, by making the backside dielectric layer in main gate line region not have opening, and making other regions have the second patterns of openings, also can make the improved efficiency of solar cell thus.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (31)
1. a passivation emitter back electrode silicon wafer solar cell, is characterized in that, comprising:
One P-type silicon sheet, it has a sensitive surface and a back side, and described P-type silicon sheet has a main gate line region and other regions except described main gate line region on the described back side;
One N-type doped layer, is positioned on the described sensitive surface of described P-type silicon sheet;
One front dielectric layer, is positioned on described N-type doped layer;
One front electrode, is positioned on the dielectric layer of described front;
One backside dielectric layer, be positioned on the described back side of described P-type silicon sheet, described backside dielectric layer has one first patterns of openings being positioned at described main gate line region and one second patterns of openings being positioned at other regions described, wherein said first patterns of openings and described second patterns of openings expose described P-type silicon sheet, and described first patterns of openings of described backside dielectric layer is different from described second patterns of openings;
One first backplate, is positioned in described backside dielectric layer, and inserts in described first patterns of openings; And
One second backplate, is positioned in described backside dielectric layer, and inserts in described second patterns of openings.
2. passivation emitter back electrode silicon wafer solar cell according to claim 1, is characterized in that, described first patterns of openings comprises multiple first sub pattern independent of each other, and described second patterns of openings comprises multiple second sub pattern independent of each other.
3. passivation emitter back electrode silicon wafer solar cell according to claim 2, is characterized in that, the first width of described first sub pattern is different from the second width of described second sub pattern.
4. passivation emitter back electrode silicon wafer solar cell according to claim 3, is characterized in that, described first sub pattern and described second sub pattern are respectively strip pattern.
5. passivation emitter back electrode silicon wafer solar cell according to claim 2, is characterized in that, the first spacing between wantonly two adjacent described first sub pattern is different from the second spacing between wantonly two adjacent described second sub pattern.
6. passivation emitter back electrode silicon wafer solar cell according to claim 5, it is characterized in that, the first spacing is less than the second spacing.
7. passivation emitter back electrode silicon wafer solar cell according to claim 2, it is characterized in that, described first sub pattern presents the distributional pattern of dotted line in described main gate line region, described second sub pattern presents the distributional pattern of solid line in other regions, and the ratio of described first sub pattern shared by described main gate line region is less than described second sub pattern ratio shared in other regions.
8. passivation emitter back electrode silicon wafer solar cell according to claim 2, is characterized in that, the shape of described first sub pattern is different from described second sub pattern.
9. passivation emitter back electrode silicon wafer solar cell according to claim 2, is characterized in that, described first sub pattern and described second sub pattern are line respectively, point, line segment or its combine.
10. passivation emitter back electrode silicon wafer solar cell according to claim 1, also comprise a welding rod, it is characterized in that, described welding rod is connected with described first backplate.
11. passivation emitter back electrode silicon wafer solar cells according to claim 1, is characterized in that, described p-type silicon chip comprises the silicon chip of boron doping or gallium doping.
12. passivation emitter back electrode silicon wafer solar cells according to claim 1, it is characterized in that, the gross area of the first patterns of openings described in described backside dielectric layer and described second patterns of openings is between 0.5% to 15% relative to the ratio of the area at the described back side.
13. passivation emitter back electrode silicon wafer solar cells according to claim 1, it is characterized in that, described backside dielectric layer is Al
xo
y, SiO
2, Si
xn
y, Si
xn
yh
z, Si
so
yn
zor the single or multiple lift structure of SiC combination.
14. passivation emitter back electrode silicon wafer solar cells according to claim 1, it is characterized in that, described front dielectric layer is SiO
2, Si
xn
yor Si
xn
yh
z, Si
xo
yn
zor the single or multiple lift structure of SiC combination.
15. passivation emitter back electrode silicon wafer solar cells according to claim 1, is characterized in that, the region that described N-type doped layer corresponds to described front electrode is high concentration phosphorus doping, and its sheet resistance is for being less than or equal to 70ohm/sq..
16. passivation emitter back electrode silicon wafer solar cells according to claim 1, is characterized in that, the described N-type doped layer region corresponded to except described front electrode is low phosphorus doping, and its sheet resistance is for being greater than 70ohm/sq..
17. passivation emitter back electrode silicon wafer solar cells according to claim 1, is characterized in that, the part in the region that described N-type doped layer corresponds to beyond described front electrode is high concentration phosphorus doping.
18. 1 kinds of passivation emitter back electrode silicon wafer solar cells, is characterized in that, comprising:
One P-type silicon sheet, it has a sensitive surface and a back side, and described P-type silicon sheet has a main gate line region and other regions except described main gate line region on the described back side;
One N-type doped layer, is positioned on the described sensitive surface of described P-type silicon sheet;
One front dielectric layer, is positioned on described N-type doped layer;
One front electrode, is positioned on the dielectric layer of described front;
One backside dielectric layer, is positioned on the described back side of described P-type silicon sheet, and described backside dielectric layer is different from described backside dielectric layer at the pattern being positioned at other regions described at the pattern being positioned at described main gate line region;
One first backplate, is positioned in described backside dielectric layer; And
One second backplate, is positioned in described backside dielectric layer, and inserts the pattern being positioned at other regions described of described backside dielectric layer.
19. passivation emitter back electrode silicon wafer solar cells according to claim 18, it is characterized in that, described backside dielectric layer is being positioned at described main gate line region for covering described P-type silicon sheet comprehensively, and described backside dielectric layer has patterns of openings in other regions described in being positioned at.
20. 1 kinds of photovoltaic modulies, is characterized in that, comprising:
Passivation emitter back electrode silicon wafer solar cell as described in any one of claim 1 to 19; And
Welding rod, is electrically connected between two adjacent described passivation emitter back electrode silicon wafer solar cells.
The manufacture method of 21. 1 kinds of passivation emitter back electrode silicon wafer solar cells, is characterized in that, comprising:
There is provided a P-type silicon sheet, it has a sensitive surface and a back side, and described P-type silicon sheet has a main gate line region and other regions except described main gate line region on the described back side;
The described sensitive surface of described P-type silicon sheet is formed a N-type doped layer;
Described N-type doped layer is formed a front dielectric layer;
Described front dielectric layer forms a front electrode;
The described back side of described P-type silicon sheet forms a backside dielectric layer, one first patterns of openings is formed with the described main gate line region that is positioned in described backside dielectric layer, and form one second patterns of openings in other regions described that are positioned at of described backside dielectric layer, wherein said first patterns of openings and described second patterns of openings expose described P-type silicon sheet, and described first patterns of openings of described backside dielectric layer is different from described second patterns of openings;
Described backside dielectric layer forms one first backplate, inserts in described first patterns of openings to make described first backplate; And
Described backside dielectric layer forms one second backplate, inserts in described second patterns of openings to make described second backplate.
The manufacture method of 22. passivation emitter back electrode silicon wafer solar cells according to claim 21, it is characterized in that, described first patterns of openings comprises multiple first sub pattern independent of each other, and described second patterns of openings comprises multiple second sub pattern independent of each other.
The manufacture method of 23. passivation emitter back electrode silicon wafer solar cells according to claim 22, it is characterized in that, the first width of described first sub pattern is different from the second width of described second sub pattern.
The manufacture method of 24. passivation emitter back electrode silicon wafer solar cells according to claim 23, it is characterized in that, described first sub pattern and described second sub pattern are respectively strip pattern.
The manufacture method of 25. passivation emitter back electrode silicon wafer solar cells according to claim 22, is characterized in that, the first spacing between wantonly two adjacent described first sub pattern is different from the second spacing between wantonly two adjacent described second sub pattern.
The manufacture method of 26. passivation emitter back electrode silicon wafer solar cells according to claim 25, it is characterized in that, the first spacing is less than the second spacing.
27. according to the manufacture method of the passivation emitter back electrode silicon wafer solar cell described in claim 22, it is characterized in that, described first sub pattern presents the distributional pattern of dotted line in described main gate line region, described second sub pattern presents the distributional pattern of solid line in other regions, and the ratio of described first sub pattern shared by described main gate line region is less than described second sub pattern ratio shared in other regions.
The manufacture method of 28. passivation emitter back electrode silicon wafer solar cells according to claim 22, it is characterized in that, the shape of described first sub pattern is different from described second sub pattern.
The manufacture method of 29. passivation emitter back electrode silicon wafer solar cells according to claim 22, it is characterized in that, described first sub pattern and described second sub pattern are line respectively, point, line segment or its combine.
The manufacture method of 30. passivation emitter back electrode silicon wafer solar cells according to claim 21, it is characterized in that, the gross area of the first patterns of openings described in described backside dielectric layer and described second patterns of openings is between 0.5% to 15% relative to the ratio of the area at the described back side.
The manufacture method of 31. passivation emitter back electrode silicon wafer solar cells according to claim 21, is characterized in that, be also included in described first backplate and form a welding rod.
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| TW102132443 | 2013-09-09 |
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| US20160284898A1 (en) * | 2015-03-27 | 2016-09-29 | Neo Solar Power Corp. | Solar cell |
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| WO2011002130A1 (en) * | 2009-06-29 | 2011-01-06 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
| CN202601627U (en) * | 2012-05-04 | 2012-12-12 | 浙江尖山光电股份有限公司 | Cirrus-type back electrode solar cell |
| US20130220411A1 (en) * | 2012-02-23 | 2013-08-29 | Lg Electronics Inc. | Solar cell and method for manufacturing the same |
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2013
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011002130A1 (en) * | 2009-06-29 | 2011-01-06 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
| US20130220411A1 (en) * | 2012-02-23 | 2013-08-29 | Lg Electronics Inc. | Solar cell and method for manufacturing the same |
| CN202601627U (en) * | 2012-05-04 | 2012-12-12 | 浙江尖山光电股份有限公司 | Cirrus-type back electrode solar cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20160284898A1 (en) * | 2015-03-27 | 2016-09-29 | Neo Solar Power Corp. | Solar cell |
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