CN104425353A - Through-silicon via polishing method - Google Patents
Through-silicon via polishing method Download PDFInfo
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- CN104425353A CN104425353A CN201310365548.1A CN201310365548A CN104425353A CN 104425353 A CN104425353 A CN 104425353A CN 201310365548 A CN201310365548 A CN 201310365548A CN 104425353 A CN104425353 A CN 104425353A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a through-silicon via polishing method which comprises the following steps: a semiconductor substrate is provided, wherein the semiconductor substrate is provided with a through-silicon via and covered with a copper layer which fills the through-silicon via; the copper layer is polished for the first time; and the copper layer is polished for the second time to form a copper wire layer, wherein the down force of the second polishing is smaller than the down force of the first polishing. According to the through-silicon via polishing method of the invention, the copper layer is polished step by step and the down force of the second polishing is decreased, so that the rate of copper grinding can be reduced, the dent defect in the through-silicon via can be reduced or eliminated, and the electrical performance of the device can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of finishing method of silicon through hole.
Background technology
Along with people are to the development of the requirement of electronic product to directions such as miniaturized, multi-functional, environment-friendly types, people make great efforts to seek electronic system to do less and less, and integrated level is more and more higher, and function is done more and more.Thereby produce many new technologies, new material and newly design, such as, the technology such as Stacked Die Packaging technology and system in package are exactly the Typical Representative of these technology.The former is called for short 3D encapsulation technology, refers under the prerequisite not changing package body sizes, stacks the encapsulation technology of two or more chip in same packaging body in vertical direction.
In numerous 3D encapsulation technologies, silicon through hole (Through-Silicon Via, being called for short TSV) technology is the focus of now research, TSV technology has following advantage: interconnection length can shorten to equal with chip thickness, adopts the logic module of the logic module substitution level distribution of vertical stacking; Remarkable reduction RC postpones and inductive effect, improves the transmission of digital data transmission speed and microwave; Realize the connection of high density, high-aspect-ratio.
In the manufacturing process of TSV, general needs experiences multiple complex process steps such as etching, plasma enhanced chemical vapor deposition, physical vapour deposition (PVD), electro-coppering, cmp (CMP).But, because the depth-to-width ratio of TSV is larger, so after carrying out copper plating process, the filling annulus that copper surface above through hole there will be, as shown in Figure 1, described semiconductor base 100 has silicon through hole 110, described semiconductor base 100 is coated with a layers of copper 200, described layers of copper 200 fills described silicon through hole 110, the filling annulus 210 that copper surface above described layers of copper 200 can have, Fig. 2 is the Scanning Electron picture of described filling annulus 210, again after CMP, the position of described filling annulus there will be pitting defects as shown in Figure 3, thus affect the electric property of device.
Summary of the invention
The object of the invention is to, a kind of finishing method of silicon through hole is provided, the pitting defects in silicon through hole can be reduced or eliminated, thus improve the electric property of device.
For solving the problems of the technologies described above, a kind of finishing method of silicon through hole, comprising:
There is provided semiconductor base, described semiconductor base has silicon through hole, described semiconductor base is coated with a layers of copper, described layers of copper fills described silicon through hole;
First polishing is carried out to described layers of copper;
Carry out the second polishing to described layers of copper, to form copper conductor layer, wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing.
Further, described second polishing step is carried out to described layers of copper after, also comprise: annealing process is carried out to described semiconductor base.
Further, described annealing process comprises:
Carry out the first intensification, after being warmed up to the first temperature, keep the very first time;
Carry out the second intensification, after being warmed up to the second temperature, kept for the second time;
Carry out nature cooling.
Further, the described first heating rate heated up is 0.5 DEG C/min ~ 1.5 DEG C/min, described first temperature is 140 DEG C ~ 160 DEG C, and the described very first time is 2min ~ 10min.
Further, the described second heating rate heated up is 2.5 DEG C/min ~ 3.5 DEG C/min, described second temperature is 290 DEG C ~ 310 DEG C, and described second time is 20min ~ 2h.
Further, described first polishing and described second polishing carry out polishing on same polishing pad.
Further, described first polishing controls polishing end point by endpoint monitoring.
Further, the ground slurry flow velocity of described first polishing is 100ml/min ~ 200ml/min.
Further, the beneath pressure of described first polishing is 2psi ~ 5psi.
Further, the rotating speed of described first polishing is 50rpm ~ 100rpm.
Further, described second polishing comprises the second main polishing and second and crosses polishing, and described second main polishing controls polishing end point by endpoint monitoring, and described second crosses polishing controls polishing end point by polishing time.
Further, described second main polishing and the second ground slurry flow velocity crossing polishing are 100ml/min ~ 200ml/min.
Further, described second main polishing and the second beneath pressure crossing polishing are 0.5psi ~ 2psi.
Further, described second main polishing and the second rotating speed crossing polishing are 50rpm ~ 100rpm.
Compared with prior art, the finishing method of silicon through hole provided by the invention has the following advantages:
1, in the finishing method of described silicon through hole, first the first polishing is carried out to described layers of copper, then the second polishing is carried out to described layers of copper, to form copper conductor layer, wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing, and compared with prior art, substep carries out polishing to described layers of copper, and reduce the beneath pressure of described second polishing, the grinding rate to copper can be reduced, thus the pitting defects in silicon through hole can be reduced or eliminated, thus improve the electric property of device.
2, in the finishing method of described silicon through hole, described second polishing step is carried out to described layers of copper after, also comprise and annealing process is carried out to described semiconductor base, preferably, described annealing process is naturally anneal after substep heats up, the pitting defects in silicon through hole can be reduced or eliminated further, to improve the electric property of device further.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that after silicon through hole carries out copper plating process in prior art, annulus is filled on copper surface;
Fig. 2 is for filling the Scanning Electron picture of annulus described in prior art;
Fig. 3 is the schematic diagram of the pitting defects of silicon through hole in prior art;
Fig. 4 is the flow chart of the finishing method of silicon through hole in one embodiment of the invention.
Embodiment
Be described in more detail below in conjunction with the finishing method of schematic diagram to silicon through hole of the present invention, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of finishing method of silicon through hole is provided, the finishing method of described silicon through hole first carries out the first polishing to described layers of copper, again the second polishing is carried out to described layers of copper, to form copper conductor layer, wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing, compared with prior art, substep carries out polishing to described layers of copper, and reduces the beneath pressure of described second polishing, can reduce the grinding rate to copper, thus the pitting defects that can reduce or eliminate in silicon through hole, thus improve the electric property of device.
In conjunction with above-mentioned core concept, the finishing method of silicon through hole provided by the invention, comprising:
Step S11, provides semiconductor base, described semiconductor base has silicon through hole, described semiconductor base is coated with a layers of copper, and described layers of copper fills described silicon through hole;
Step S12, carries out the first polishing to described layers of copper;
Step S13, carries out the second polishing to described layers of copper, and to form copper conductor layer, wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing.
Below incorporated by reference to Fig. 4, illustrate the finishing method of silicon through hole of the present invention.Wherein, Fig. 4 is the flow chart of the finishing method of silicon through hole in one embodiment of the invention.
First, as shown in Figure 4, carry out step S11, semiconductor base is provided, described semiconductor base has silicon through hole, described semiconductor base is coated with a layers of copper, described layers of copper fills described silicon through hole, because the depth-to-width ratio of described silicon through hole is comparatively large, so, the filling annulus that the copper surface above described layers of copper can have.
Then, carry out step S12, the first polishing is carried out to described layers of copper, to remove most described layers of copper, such as, remove the described layers of copper of 70% ~ 90%.Preferably, described first polishing controls polishing end point by endpoint monitoring, and described polishing end point is determined by concrete manufacturing process, and such as, in the present embodiment, described polishing end point is the described layers of copper of removal 80%.
Preferably, the ground slurry flow velocity of described first polishing is 100ml/min ~ 200ml/min, is preferably 150ml/min.The beneath pressure (downforce) of described first polishing is 2psi ~ 5psi (Pounds per squareinch, pound/square inch), such as, in the present embodiment, the polishing pad carrying out described first polishing has three chambeies, then the beneath pressure in these three chambeies is 4.2psi, 4.6psi and 2.5psi.But the polishing pad carrying out described first polishing is not limited to have three chambeies, also can only have a chamber, also within thought range of the present invention.Preferably, the rotating speed of described first polishing is 50rpm ~ 100rpm, and such as, in the present embodiment, described polishing pad and grinding head can rotate, then the rotating speed of described polishing pad is 87rpm, and the rotating speed of described grinding head is 93rpm.But carry out described first polishing and be not limited to described polishing pad and grinding head can rotate, described polishing pad also can be only had to rotate, also within thought range of the present invention.
Then, carry out step S13, carry out the second polishing to described layers of copper, to form copper conductor layer, wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing.In the present embodiment, described first polishing and described second polishing carry out polishing on same polishing pad, and described first polishing and described second polishing all carry out polishing, to save technological process on the first polishing pad.
Preferably, described second polishing comprises the second main polishing and second and crosses polishing, described second main polishing controls polishing end point by endpoint monitoring, to control the described layers of copper of main region to remove completely, described second crosses polishing controls polishing end point by polishing time, to control the described layers of copper of subregion to remove completely, wherein, described second main polishing and the described second described polishing end point crossing polishing are determined by concrete manufacturing process, such as, in the present embodiment, the polishing end point of described second main polishing is that the change of described polishing fluid is less than 80%, the polishing time 2min of described second mistake polishing, specifically do not limit.Preferably, described second main polishing and the second ground slurry flow velocity crossing polishing are 100ml/min ~ 200ml/min, are preferably 150ml/min.Described second main polishing and the second beneath pressure crossing polishing are 0.5psi ~ 2psi, such as, in the present embodiment, the polishing pad carrying out described second main polishing and the second mistake polishing has three chambeies, then the beneath pressure in these three chambeies is 1.7psi, 1.7psi and 1.0psi.But the polishing pad carrying out described second main polishing and the second mistake polishing is not limited to have three chambeies, also can only have a chamber, also within thought range of the present invention.Preferably, described second main polishing and the second rotating speed crossing polishing are 50rpm ~ 100rpm, and such as, in the present embodiment, described polishing pad and grinding head can rotate, then the rotating speed of described polishing pad is 87rpm, and the rotating speed of described grinding head is 93rpm.But carry out described second main polishing and second to cross polishing and be not limited to described polishing pad and grinding head can rotate, described polishing pad also can be only had to rotate, also within thought range of the present invention.
In the present embodiment, after step s 13, also comprise: annealing process is carried out to described semiconductor base.Concrete, described annealing process comprises:
Carry out the first sub-portion: carry out the first intensification, after being warmed up to the first temperature, keep the very first time.Preferably, the described first heating rate heated up is 0.5 DEG C/min ~ 1.5 DEG C/min, be preferably 1 DEG C/min, described first temperature is 140 DEG C ~ 160 DEG C, and be preferably 150 DEG C, the described very first time is 2min ~ 10min, is preferably 5min.
Carry out the second sub-portion: carry out the second intensification, after being warmed up to the second temperature, kept for the second time.Preferably, the described second heating rate heated up is 2.5 DEG C/min ~ 3.5 DEG C/min, be preferably 3 DEG C/min, described second temperature is 290 DEG C ~ 310 DEG C, and be preferably 300 DEG C, described second time is 20min ~ 2h, is preferably 1h.
Carry out the 3rd sub-portion: carry out nature cooling.
After above-mentioned annealing process, the pitting defects in silicon through hole can be reduced or eliminated further, to improve the electric property of device further.
In sum, the invention provides a kind of finishing method of silicon through hole, comprising: provide semiconductor base, described semiconductor base has silicon through hole, described semiconductor base is coated with a layers of copper, described layers of copper fills described silicon through hole; First polishing is carried out to described layers of copper; Carry out the second polishing to described layers of copper, to form copper conductor layer, wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing.
Compared with prior art, the finishing method of silicon through hole provided by the invention has the following advantages:
1, in the finishing method of described silicon through hole, first the first polishing is carried out to described layers of copper, then the second polishing is carried out to described layers of copper, to form copper conductor layer, wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing, and compared with prior art, substep carries out polishing to described layers of copper, and reduce the beneath pressure of described second polishing, the grinding rate to copper can be reduced, thus the pitting defects in silicon through hole can be reduced or eliminated, thus improve the electric property of device.
2, in the finishing method of described silicon through hole, described second polishing step is carried out to described layers of copper after, also comprise and annealing process is carried out to described semiconductor base, preferably, described annealing process is naturally anneal after substep heats up, the pitting defects in silicon through hole can be reduced or eliminated further, to improve the electric property of device further.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (14)
1. a finishing method for silicon through hole, comprising:
There is provided semiconductor base, described semiconductor base has silicon through hole, described semiconductor base is coated with a layers of copper, described layers of copper fills described silicon through hole;
First polishing is carried out to described layers of copper;
Second polishing is carried out to described layers of copper, to form copper conductor layer; Wherein, the beneath pressure of described second polishing is less than the beneath pressure of described first polishing.
2. the finishing method of silicon through hole as claimed in claim 1, is characterized in that, described second polishing step is carried out to described layers of copper after, also comprise: annealing process is carried out to described semiconductor base.
3. the finishing method of silicon through hole as claimed in claim 2, it is characterized in that, described annealing process comprises:
Carry out the first intensification, after being warmed up to the first temperature, keep the very first time;
Carry out the second intensification, after being warmed up to the second temperature, kept for the second time;
Carry out nature cooling.
4. the finishing method of silicon through hole as claimed in claim 3, is characterized in that, the described first heating rate heated up is 0.5 DEG C/and min ~ 1.5 DEG C/min, described first temperature is 140 DEG C ~ 160 DEG C, and the described very first time is 2min ~ 10min.
5. the finishing method of silicon through hole as claimed in claim 3, is characterized in that, the described second heating rate heated up is 2.5 DEG C/and min ~ 3.5 DEG C/min, described second temperature is 290 DEG C ~ 310 DEG C, and described second time is 20min ~ 2h.
6. as the finishing method of the silicon through hole in claim 1-5 as described in any one, it is characterized in that, described first polishing and described second polishing carry out polishing on same polishing pad.
7. as the finishing method of the silicon through hole in claim 1-5 as described in any one, it is characterized in that, described first polishing controls polishing end point by endpoint monitoring.
8. as the finishing method of the silicon through hole in claim 1-5 as described in any one, it is characterized in that, the ground slurry flow velocity of described first polishing is 100ml/min ~ 200ml/min.
9. as the finishing method of the silicon through hole in claim 1-5 as described in any one, it is characterized in that, the beneath pressure of described first polishing is 2psi ~ 5psi.
10. as the finishing method of the silicon through hole in claim 1-5 as described in any one, it is characterized in that, the rotating speed of described first polishing is 50rpm ~ 100rpm.
11. as the finishing method of the silicon through hole in claim 1-5 as described in any one, it is characterized in that, described second polishing comprises the second main polishing and second and crosses polishing, and described second main polishing controls polishing end point by endpoint monitoring, and described second crosses polishing controls polishing end point by polishing time.
The finishing method of 12. silicon through holes as claimed in claim 11, is characterized in that, described second main polishing and the second ground slurry flow velocity crossing polishing are 100ml/min ~ 200ml/min.
The finishing method of 13. silicon through holes as claimed in claim 11, is characterized in that, described second main polishing and the second beneath pressure crossing polishing are 0.5psi ~ 2psi.
The finishing method of 14. silicon through holes as claimed in claim 11, is characterized in that, described second main polishing and the second rotating speed crossing polishing are 50rpm ~ 100rpm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310365548.1A CN104425353B (en) | 2013-08-20 | 2013-08-20 | Polishing method of through silicon via |
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| CN201310365548.1A CN104425353B (en) | 2013-08-20 | 2013-08-20 | Polishing method of through silicon via |
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| CN104425353A true CN104425353A (en) | 2015-03-18 |
| CN104425353B CN104425353B (en) | 2019-12-27 |
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