CN104425280A - Semiconductor device structure and forming method thereof - Google Patents
Semiconductor device structure and forming method thereof Download PDFInfo
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- CN104425280A CN104425280A CN201310407723.9A CN201310407723A CN104425280A CN 104425280 A CN104425280 A CN 104425280A CN 201310407723 A CN201310407723 A CN 201310407723A CN 104425280 A CN104425280 A CN 104425280A
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- layer
- semiconductor device
- tension stress
- channel layer
- resilient coating
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011248 coating agent Substances 0.000 claims description 40
- 238000000576 coating method Methods 0.000 claims description 40
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 230000003139 buffering effect Effects 0.000 abstract 3
- 238000013508 migration Methods 0.000 abstract 1
- 230000005012 migration Effects 0.000 abstract 1
- 239000002800 charge carrier Substances 0.000 description 5
- 235000019994 cava Nutrition 0.000 description 2
- 101100207343 Antirrhinum majus 1e20 gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device structure and a forming method thereof. A buffering layer, a pull stress layer and a channel layer are formed on the semiconductor substrate in sequence; a gate dielectric layer and a gate electrode are formed on the channel layer, and then the pull stress layer is etched, so that the pull stress layer is sunken to a preset depth and is positioned between the channel layer and the buffering layer; an epitaxial layer and a source/drain electrode is formed. The pull stress layer is sunken to the preset depth and is positioned between the channel layer and the buffering layer, so that an effect of jacking the middle position of the channel layer can be achieved, and pull stress in the channel layer is increased; therefore, the migration rate of a current carrier can be increased, and the performance of a semiconductor device is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of semiconductor device structure and forming method thereof.
Background technology
Along with the development of semicon industry, the requirement of people to performance of semiconductor device is also more and more higher.The performance improving semiconductor device is one of trend of present technological development.
Please refer to Fig. 1, the semiconductor device in existing technique comprises: Semiconductor substrate 10; Be formed in gate oxide 30 and the grid 40 on Semiconductor substrate 10 surface successively; To be formed in Semiconductor substrate 10 and to be positioned at the source/drain 20 of described gate oxide 30 and grid 40 both sides; Be formed at the side wall 50 of described gate oxide 30 and grid 40 both sides.
Now along with the progress of technique, applied stress technique can be exerted pressure corresponding stress by the raceway groove between described semiconductor device source/drain 20, such as certain compression is applied to the raceway groove of PMOS, certain tension stress is applied to the raceway groove of NMOS tube, thus improve the mobility of PMOS and NMOS tube charge carrier, and then improve the reaction speed of semiconductor device, reduce the reaction time, to the performance boost of semiconductor device, there is very large progradation.
But, the more difficult realization of tension stress of the semiconductor device NMOS tube in existing technique, cannot to exert pressure tension stress to the raceway groove between described semiconductor device source/drain 20 largely, also the performance of NMOS tube cannot just be promoted, so how to improve the tension stress to raceway groove between NMOS tube source/drain 20, also just become those skilled in the art to be badly in need of the technical problem solved.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device structure and forming method thereof can increase tension stress to raceway groove, increase the mobility of charge carrier.
To achieve these goals, the present invention proposes a kind of formation method of semiconductor device, comprises step:
Semiconductor substrate is provided;
Form resilient coating, tension stress layer and channel layer on the semiconductor substrate successively;
Described channel layer is formed gate dielectric layer, grid and side wall, and wherein said grid is formed at described gate dielectric layer surface, and described side wall is formed at the both sides of described grid and gate dielectric layer;
Etch described channel layer, tension stress layer and resilient coating successively, make described channel layer, tension stress layer and resilient coating remain in the below of described side wall and gate dielectric layer;
The described tension stress layer of etching residue, makes the sidewall of described tension stress layer relative to side walls collapse one desired depth of described channel layer and resilient coating;
Form an epitaxial loayer on a semiconductor substrate, described epitaxial loayer surrounds the Partial Height of described resilient coating, tension stress layer, channel layer and side wall;
In described epitaxial loayer, form source/drain, described source/drain is positioned at the both sides of described side wall.
Further, in the formation method of described semiconductor device, the material of described resilient coating is carborundum or silicon.
Further, in the formation method of described semiconductor device, the thickness range of described resilient coating is 10nm ~ 50nm.
Further, in the formation method of described semiconductor device, the material of described tension stress layer is germanium silicon.
Further, in the formation method of described semiconductor device, the thickness range of described tension stress layer is 20nm ~ 80nm.
Further, in the formation method of described semiconductor device, the monolateral depression desired depth scope of described tension stress layer is 1/5 ~ 1/3 of gate CDs.
Further, in the formation method of described semiconductor device, the material of described channel layer is monocrystalline silicon or polysilicon.
Further, in the formation method of described semiconductor device, the thickness range of described channel layer is 5nm ~ 20nm.
Further, in the formation method of described semiconductor device, the material of described epitaxial loayer is carborundum.
Further, in the formation method of described semiconductor device, described source/drain adopts ion implantation or in-situ doped mode to be formed.
Further, in the formation method of described semiconductor device, the material of described gate dielectric layer is silicon dioxide.
Further, the present invention also proposes a kind of semiconductor device structure, adopts as above any one method is formed, comprising:
Semiconductor substrate; Form resilient coating on the semiconductor substrate, tension stress layer, channel layer, gate dielectric layer, grid, side wall and epitaxial loayer successively; Wherein, the sidewall of described tension stress layer is relative to side walls collapse one desired depth of described channel layer and resilient coating; Described side wall is positioned at the both sides of described gate dielectric layer and grid; Described epitaxial loayer is formed at the both sides of described side wall, and surrounds described resilient coating, tension stress layer and channel layer; Be formed in described epitaxial loayer the source/drain being positioned at described side wall both sides.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: form resilient coating, tension stress layer and channel layer on a semiconductor substrate successively; Then on channel layer, gate dielectric layer and grid is formed; Then etch described tension stress layer, described tension stress layer is caved in desired depth be positioned at the centre position of channel layer and resilient coating; Then epitaxial loayer and source/drain is formed; The centre position of channel layer and resilient coating is positioned at due to described tension stress layer depression desired depth, thus the effect of jack-up can be equipped with to described channel layer interposition, the tension stress in described channel layer can be increased, and then the mobility of charge carrier can be increased, improve the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the structural representation of semiconductor device in prior art;
Fig. 2 is the flow chart of method for forming semiconductor devices in one embodiment of the invention;
Fig. 3-Fig. 7 is the profile of semiconductor device in semiconductor device forming process in one embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, semiconductor device structure that the present invention proposes and forming method thereof is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, in the present embodiment, propose a kind of formation method of semiconductor device, comprise step:
S100: provide Semiconductor substrate 100, as shown in Figure 3;
Wherein, described Semiconductor substrate can be monocrystalline silicon, polysilicon or silicon-on-insulator etc.
S200: form resilient coating 210, tension stress layer 220 and channel layer 230 successively in described Semiconductor substrate 100, as shown in Figure 3;
Wherein, the material of described resilient coating 210 is carborundum or silicon, and its thickness range is 10nm ~ 50nm, such as, be 20nm; The material of described tension stress layer 220 is germanium silicon, and its thickness range is 20nm ~ 80nm, such as, be 40nm, and the material of described channel layer 230 is monocrystalline silicon or polysilicon, and its thickness range is 5nm ~ 20nm, such as, be 10nm.
S300: form gate dielectric layer 300, grid 400 and side wall 500 on described channel layer 230, wherein, described grid 400 is formed at the surface of described gate dielectric layer 300, and described side wall 500 is formed at the both sides of described grid 400 and gate dielectric layer 300, as shown in Figure 3;
Wherein, described gate dielectric layer 300 is silicon dioxide, and described grid 400 can be polysilicon gate or metal gates; Described side wall 500 can be silicon nitride.
S400: etch described channel layer 230, tension stress layer 220 and resilient coating 210 successively, makes described channel layer 230, tension stress layer 220 and resilient coating 210 remain in the below of described side wall 500 and gate dielectric layer 300, as shown in Figure 4;
Wherein, after etching, the two ends of described channel layer 230, tension stress layer 220 and resilient coating 210 and the two ends of described side wall 500 are in same plane respectively.
S500: the tension stress layer 220 of etching residue, makes the sidewall of described tension stress layer 200 relative to side walls collapse one desired depth of described channel layer 230 and resilient coating 210, and is close to described channel layer 230 and resilient coating 210 respectively, as shown in Figure 5;
Wherein, the scope of the monolateral depression desired depth L of described tension stress layer 220 is 1/5 ~ 1/3 of characteristic size L2 of described grid 400, such as, be 1/4; After etching, the two ends of described channel layer 230 and resilient coating 210 and the two ends of described side wall 500 are in same plane, the desired depth L1 and the end flat of described tension stress layer 220 all caves in; Because described tension stress layer 220 is positioned at the centre position of described channel layer 230, described tension stress layer 220 can cause certain extruding to described channel layer 230, thus make described channel layer 230 have larger tension stress, and then the mobility of charge carrier can be improved.
S600: form an epitaxial loayer 600 on a semiconductor substrate 100, described epitaxial loayer 600 surrounds the Partial Height of described resilient coating 210, tension stress layer 220, channel layer 230 and side wall 300, as shown in Figure 6;
Wherein, described epitaxial loayer 600 surrounds described resilient coating 210, tension stress layer 220 and channel layer 230, and in the present embodiment, the material of described epitaxial loayer 600 is consistent with the material of described resilient coating 210 is carborundum; Described epitaxial loayer 600 is formed at the both sides of described side wall 500, a little less than the surface of described grid 400, but a little more than the surface of described gate dielectric layer 300.
S700: form source/drain 700 in described epitaxial loayer 600, described source/drain 700 is positioned at the both sides of described side wall 500, as shown in Figure 7;
Wherein, described source/drain 700 adopts ion implantation or in-situ doped mode to be formed, and ion implantation energy can use 2KeV to 500KeV, such as, be 100KeV, and dosage range is 3e14 to 1e15, such as, be 5e14; In-situ doped dosage range is 1e19 to 1e21, such as, be 1e20.
In the present embodiment, also propose a kind of semiconductor device structure, adopt as above any one method is formed, please refer to Fig. 7, comprising:
Semiconductor substrate 100; Be formed in the resilient coating 210 in described Semiconductor substrate 100, tension stress layer 220, channel layer 230, gate dielectric layer 300, grid 400, side wall 500 and epitaxial loayer 600 successively; Wherein, described tension stress layer 220 desired depth that caves in is positioned at described resilient coating 210 and channel layer 230 centre position; Described side wall 500 is positioned at the both sides of described gate dielectric layer 300 and grid 400; Described epitaxial loayer 600 is formed at the both sides of described side wall 500, and surrounds described resilient coating 210, tension stress layer 220 and channel layer 230; Be formed in described epitaxial loayer 600 source/drain 700 being positioned at described side wall 500 both sides.
To sum up, in semiconductor device structure that the embodiment of the present invention provides and forming method thereof, form resilient coating, tension stress layer and channel layer on a semiconductor substrate successively; Then on channel layer, gate dielectric layer and grid is formed; Then etch described tension stress layer, described tension stress layer is caved in desired depth be positioned at the centre position of channel layer and resilient coating; Then epitaxial loayer and source/drain is formed; The centre position of channel layer and resilient coating is positioned at due to described tension stress layer depression desired depth, thus the effect of jack-up can be equipped with to described channel layer interposition, the tension stress in described channel layer can be increased, and then the mobility of charge carrier can be increased, improve the performance of semiconductor device.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (12)
1. a formation method for semiconductor device, comprises step:
Semiconductor substrate is provided;
Form resilient coating, tension stress layer and channel layer on the semiconductor substrate successively;
Described channel layer is formed gate dielectric layer, grid and side wall, and wherein said grid is formed at described gate dielectric layer surface, and described side wall is formed at the both sides of described grid and gate dielectric layer;
Etch described channel layer, tension stress layer and resilient coating successively, make described channel layer, tension stress layer and resilient coating remain in the below of described side wall and gate dielectric layer;
The described tension stress layer of etching residue, makes the sidewall of described tension stress layer relative to side walls collapse one desired depth of described channel layer and resilient coating;
Form an epitaxial loayer on a semiconductor substrate, described epitaxial loayer surrounds the Partial Height of described resilient coating, tension stress layer, channel layer and side wall;
In described epitaxial loayer, form source/drain, described source/drain is positioned at the both sides of described side wall.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described resilient coating is carborundum or silicon.
3. the formation method of semiconductor device as claimed in claim 2, it is characterized in that, the thickness range of described resilient coating is 10nm ~ 50nm.
4. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described tension stress layer is germanium silicon.
5. the formation method of semiconductor device as claimed in claim 4, it is characterized in that, the thickness range of described tension stress layer is 20nm ~ 80nm.
6. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the monolateral depression desired depth scope of described tension stress layer is 1/5 ~ 1/3 of gate CDs.
7. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described channel layer is monocrystalline silicon or polysilicon.
8. the formation method of semiconductor device as claimed in claim 6, it is characterized in that, the thickness range of described channel layer is 5nm ~ 20nm.
9. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described epitaxial loayer is carborundum.
10. the formation method of semiconductor device as claimed in claim 1, is characterized in that, described source/drain adopts ion implantation or in-situ doped mode to be formed.
The formation method of 11. semiconductor device as claimed in claim 1, is characterized in that, the material of described gate dielectric layer is silicon dioxide.
12. 1 kinds of semiconductor device structures, adopt as any one method in claim 1 to 11 is formed, comprising:
Semiconductor substrate; Form resilient coating on the semiconductor substrate, tension stress layer, channel layer, gate dielectric layer, grid, side wall and epitaxial loayer successively; Wherein, the sidewall of described tension stress layer is relative to side walls collapse one desired depth of described channel layer and resilient coating; Described side wall is positioned at the both sides of described gate dielectric layer and grid; Described epitaxial loayer is formed at the both sides of described side wall, and surrounds described resilient coating, tension stress layer and channel layer; Be formed in described epitaxial loayer the source/drain being positioned at described side wall both sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310407723.9A CN104425280B (en) | 2013-09-09 | 2013-09-09 | Semiconductor device structure and forming method thereof |
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| CN201310407723.9A CN104425280B (en) | 2013-09-09 | 2013-09-09 | Semiconductor device structure and forming method thereof |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787423B1 (en) * | 2002-12-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Strained-silicon semiconductor device |
| CN101023530A (en) * | 2004-09-20 | 2007-08-22 | 国际商业机器公司 | High-mobility bulk silicon pfet |
| CN101164157A (en) * | 2003-11-05 | 2008-04-16 | 国际商业机器公司 | Method and structure for forming strained si for cmos devices |
| US20090068824A1 (en) * | 2007-09-11 | 2009-03-12 | United Microelectronics Corp. | Fabricating method of semiconductor device |
| US20120205716A1 (en) * | 2011-02-16 | 2012-08-16 | International Business Machines Corporation | Epitaxially Grown Extension Regions for Scaled CMOS Devices |
| US20120326168A1 (en) * | 2011-06-16 | 2012-12-27 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
-
2013
- 2013-09-09 CN CN201310407723.9A patent/CN104425280B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787423B1 (en) * | 2002-12-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Strained-silicon semiconductor device |
| CN101164157A (en) * | 2003-11-05 | 2008-04-16 | 国际商业机器公司 | Method and structure for forming strained si for cmos devices |
| CN101023530A (en) * | 2004-09-20 | 2007-08-22 | 国际商业机器公司 | High-mobility bulk silicon pfet |
| US20090068824A1 (en) * | 2007-09-11 | 2009-03-12 | United Microelectronics Corp. | Fabricating method of semiconductor device |
| US20120205716A1 (en) * | 2011-02-16 | 2012-08-16 | International Business Machines Corporation | Epitaxially Grown Extension Regions for Scaled CMOS Devices |
| US20120326168A1 (en) * | 2011-06-16 | 2012-12-27 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
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| CN104425280B (en) | 2018-08-14 |
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