CN104425239A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN104425239A CN104425239A CN201310407704.6A CN201310407704A CN104425239A CN 104425239 A CN104425239 A CN 104425239A CN 201310407704 A CN201310407704 A CN 201310407704A CN 104425239 A CN104425239 A CN 104425239A
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- Prior art keywords
- preparation
- semiconductor device
- layer
- grid layer
- protective layer
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- 238000002360 preparation method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 75
- 239000011241 protective layer Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 238000005516 engineering process Methods 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 17
- 230000015654 memory Effects 0.000 abstract description 15
- 238000000137 annealing Methods 0.000 abstract 4
- 230000005611 electricity Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a preparation method of a semiconductor device. The preparation method comprises the following steps: providing a substrate with a gate layer; carrying out ion implantation on the gate layer to form a doped gate layer; preparing a protective layer on the doped gate layer; carrying out thermal annealing; removing the protective layer to expose the doped gate layer. The preparation method has the advantages that the protective layer is prepared on the doped gate layer before the step of thermal annealing and is removed after the step of thermal annealing; in the process of thermal annealing, the protective layer is used for protecting the surface of the doped gate layer to prevent pin type defects, thus avoiding electric leakage of flash memories and increasing the yield.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of preparation method of semiconductor device.
Background technology
Usually, the flash memory for storing data is divided into volatile memory and nonvolatile memory, loses its data when volatile memory is easy to break in the supply, even and if nonvolatile memory power supply close after, still can retention tab internal information.As compared to other nonvolatile storage technologies (such as, disc driver), nonvolatile memory has the advantages that cost is low, density is large.Therefore, nonvolatile memory is widely used in every field, comprise embedded system, as PC and peripheral hardware, telecommunications switch, cell phone, network interconnection device, instrument and meter and automobile device, also comprise emerging voice, image, data storage class product, as digital camera, digital recorder and personal digital assistant simultaneously.
Comprise the following steps in the preparation of existing flash memory, first, shown in figure Fig. 1, provide substrate 100, described substrate 100 has a grid layer 110;
Then, carry out ion implantation technology to described grid layer 110, to form doping grid layer 110 ', as shown in Figure 2, wherein, in ion implantation technology, the surface of doping grid layer 110 ' can sustain damage;
Then, carry out thermal anneal process, due to the high temperature in thermal anneal process, make to form some defect sources 111 on the doping grid layer 110 ' surface of damaged, as shown in Figure 3, defect source 111 cannot be detected by existing online (inline) detection means;
Afterwards, doping grid layer 110 described in selective removal, to form grid 110A, as shown in Figure 4.But, in the process, because defect source 111 cannot be removed, so the doping grid layer 110 ' below defect source 111 also can retain, thus formed.
Due in the flash memory of prior art, defect source 111 cannot be detected by existing online (inline) detection means, only have and just can be detected after formation aciculiform defect 110B, as shown in Figure 6, Fig. 5 is Scanning Electron microscope photograph, existence due to aciculiform defect 110B can make flash memory leak electricity, and affects yield.
Therefore, how to provide a kind of preparation method of semiconductor device, can reduce or avoid the formation of aciculiform defect, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the invention is to, a kind of preparation method of semiconductor device is provided, can reduce or avoid the formation of aciculiform defect, thus improve yield.
For solving the problems of the technologies described above, the invention provides a kind of preparation method of semiconductor device, comprising:
Substrate is provided, described substrate has a grid layer;
Ion implantation technology is carried out to described grid layer, to form doping grid layer;
Described doping grid layer prepares a protective layer;
Carry out thermal anneal process;
Remove described protective layer, to expose described doping grid layer.
Further, after the described protective layer step of removal, also comprise: doping grid layer described in selective removal.
Further, between doping grid layer, also comprise: on described doping grid layer, prepare an anti-reflecting layer described in the described protective layer step of removal and selective removal.
Further, on described doping grid layer, an anti-reflecting layer is prepared by high temperature oxide deposition technology.
Further, the material of described protective layer is the combination of one or more in silicon nitride, silica, silicon oxynitride or organic substance.
Further, the thickness of described protective layer is 5nm ~ 1 μm.
Further, wet-etching technology is adopted to remove described protective layer.
Further, described thermal anneal process is rapid thermal anneal process, and the temperature of described rapid thermal anneal process is 800 DEG C ~ 1400 DEG C.
Further, the injection element of described ion implantation technology is P elements.
Further, the material of described grid layer is polysilicon.
Compared with prior art, the preparation method of semiconductor device provided by the invention has the following advantages:
The preparation method of semiconductor device provided by the invention; before carrying out thermal anneal process step; described doping grid layer prepares a protective layer, after carrying out thermal anneal process step, removes described protective layer; compared with prior art; in the process of carrying out thermal anneal process, the surface of described doping grid layer protected by described protective layer, prevents the generation of aciculiform defect; thus avoid flash memory to leak electricity, improve yield.
Accompanying drawing explanation
Fig. 1-Fig. 4 is the schematic diagram of the preparation method of semiconductor device in prior art;
Fig. 5 is the Scanning Electron microscope photograph of aciculiform defect in prior art;
Fig. 6 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention;
Fig. 7-Figure 12 is the schematic diagram of the preparation method of semiconductor device in one embodiment of the invention.
Embodiment
Below in conjunction with schematic diagram, the preparation method to semiconductor device of the present invention is described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of preparation method of semiconductor device, and the preparation method of semiconductor device comprises provides substrate, described substrate has a grid layer; Ion implantation technology is carried out to described grid layer, to form doping grid layer; Described doping grid layer prepares a protective layer; Carry out thermal anneal process; Remove described protective layer, to expose described doping grid layer.The present invention is before carrying out thermal anneal process step; described doping grid layer prepares a protective layer; after carrying out thermal anneal process step; remove described protective layer, compared with prior art, in the process of carrying out thermal anneal process; the surface of described doping grid layer protected by described protective layer; prevent the generation of aciculiform defect, thus avoid flash memory to leak electricity, improve yield.
Below please refer to the preparation method that Fig. 6 and Fig. 7-Figure 12 illustrates described semiconductor device, wherein, Fig. 6 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention; Fig. 7-Figure 12 is the schematic diagram of the preparation method of semiconductor device in one embodiment of the invention.
First, carry out step S11, substrate 200 is provided, described substrate 200 has a grid layer 210, as shown in Figure 7.Preferably, the material of described grid layer 210 is polysilicon.But the material of described grid layer 210 is not limited to as polysilicon, as described in the material of grid layer 210 can be metal, also within thought range of the present invention.Wherein, described substrate 200 can be unadulterated monocrystalline substrate, monocrystalline substrate, silicon-on-insulator (SOI) substrate or SiGe (SiGe) substrate etc. doped with impurity, in the present embodiment, described substrate 200 is made up of single crystal silicon material.Described substrate 200 also comprises the necessary devices such as isolated area, and this is the common practise of this area, and therefore not to repeat here.
Then, carry out step S12, ion implantation technology is carried out to described grid layer 210, to form doping grid layer 210 ', as shown in Figure 8.In the present embodiment, the injection element of described ion implantation technology is P elements, and to form the doping grid layer 210 ' of N-type doping, but the injection element of described ion implantation technology is P elements, can also be boron element etc.
Then, step S13 is carried out, at upper preparation one protective layer 220 of described doping grid layer 210 ', as shown in Figure 9.Preferably; the material of described protective layer 220 is the combination of one or more in silicon nitride, silica, silicon oxynitride or organic substance; silicon nitride, silica, silicon oxynitride or organic substance are easily removed in step S15; but the material of described protective layer 220 is the combination of one or more in silicon nitride, silica, silicon oxynitride or organic substance; as long as can in step S15 removed material, also within thought range of the present invention.Wherein, the thickness of described protective layer 220 is preferably 5nm ~ 1 μm; can protect described doping grid layer 210 ' in step S14, thickness preferably 20nm, 100nm, 500nm etc. of described protective layer 220, but the thickness of described protective layer 220 is not limited to as 5nm ~ 1 μm.
Subsequently, carry out step S14, carry out thermal anneal process, in step S14, the surface of described doping grid layer 210 ' protected by described protective layer 220, prevents the generation in defect source, thus avoids flash memory to leak electricity, and improves yield.Preferably, described thermal anneal process is rapid thermal anneal process, can activate the ion of injection well, and the temperature of described rapid thermal anneal process is 800 DEG C ~ 1400 DEG C, is preferably 1000 DEG C.
Then, carry out step S15, remove described protective layer 220, to expose described doping grid layer 210 ', as shown in Figure 10.Preferably, adopt wet-etching technology to remove described protective layer 220, described protective layer 220 can be removed rapidly, but dry etch process can also be adopted to remove described protective layer 220, also within thought range of the present invention.
Further, in the present embodiment, after the step s 15, upper preparation one anti-reflecting layer 230 of described doping grid layer 210 ' is also included in.Preferably, by high temperature oxide deposition technology at upper preparation one anti-reflecting layer 230 of described doping grid layer 210 ', (illumination during photolithographic exposure) can be shone, the accurate in size photoresistance prepared by reverberation well.But and to be limited to by high temperature oxide deposition technology at upper preparation one anti-reflecting layer 230 of described doping grid layer 210 ', prepare anti-reflecting layer 230 as different deposition processs can also be adopted.
Finally; doping grid layer 210 ' described in selective removal; to form grid 210A; in step S14; the surface of described doping grid layer 210 ' protected by described protective layer 220; prevent the generation in defect source, thus in the step of doping grid layer 210 ' described in selective removal, the generation of aciculiform defect can be avoided.
In sum, the invention provides a kind of preparation method of semiconductor device, the preparation method of semiconductor device comprises provides substrate, described substrate has a grid layer; Ion implantation technology is carried out to described grid layer, to form doping grid layer; Described doping grid layer prepares a protective layer; Carry out thermal anneal process; Remove described protective layer, to expose described doping grid layer.Compared with prior art, the Bias Temperature instability test circuit that contains provided by the invention has the following advantages:
The preparation method of semiconductor device provided by the invention; before carrying out thermal anneal process step; described doping grid layer prepares a protective layer, after carrying out thermal anneal process step, removes described protective layer; compared with prior art; in the process of carrying out thermal anneal process, the surface of described doping grid layer protected by described protective layer, prevents the generation of aciculiform defect; thus avoid flash memory to leak electricity, improve yield.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a preparation method for semiconductor device, comprising:
Substrate is provided, described substrate has a grid layer;
Ion implantation technology is carried out to described grid layer, to form doping grid layer;
Described doping grid layer prepares a protective layer;
Carry out thermal anneal process;
Remove described protective layer, to expose described doping grid layer.
2. the preparation method of semiconductor device as claimed in claim 1, is characterized in that, after the described protective layer step of removal, also comprises: doping grid layer described in selective removal.
3. the preparation method of semiconductor device as claimed in claim 2, is characterized in that, described in the described protective layer step of removal and selective removal between doping grid layer, also comprises: on described doping grid layer, prepare an anti-reflecting layer.
4. the preparation method of semiconductor device as claimed in claim 3, is characterized in that, prepare an anti-reflecting layer by high temperature oxide deposition technology on described doping grid layer.
5. as the preparation method of the semiconductor device in claim 1-4 as described in any one, it is characterized in that, the material of described protective layer is the combination of one or more in silicon nitride, silica, silicon oxynitride or organic substance.
6. as the preparation method of the semiconductor device in claim 1-4 as described in any one, it is characterized in that, the thickness of described protective layer is 5nm ~ 1 μm.
7. as the preparation method of the semiconductor device in claim 1-4 as described in any one, it is characterized in that, adopt wet-etching technology to remove described protective layer.
8. as the preparation method of the semiconductor device in claim 1-4 as described in any one, it is characterized in that, described thermal anneal process is rapid thermal anneal process, and the temperature of described rapid thermal anneal process is 800 DEG C ~ 1400 DEG C.
9. as the preparation method of the semiconductor device in claim 1-4 as described in any one, it is characterized in that, the injection element of described ion implantation technology is P elements.
10. as the preparation method of the semiconductor device in claim 1-4 as described in any one, it is characterized in that, the material of described grid layer is polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310407704.6A CN104425239B (en) | 2013-09-09 | 2013-09-09 | The preparation method of semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310407704.6A CN104425239B (en) | 2013-09-09 | 2013-09-09 | The preparation method of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
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| CN104425239A true CN104425239A (en) | 2015-03-18 |
| CN104425239B CN104425239B (en) | 2017-10-17 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050233525A1 (en) * | 2004-04-16 | 2005-10-20 | Yee-Chia Yeo | Gate electrode for a semiconductor fin device |
| CN101192525A (en) * | 2006-11-28 | 2008-06-04 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device grid preparation method |
| CN101894749A (en) * | 2009-05-20 | 2010-11-24 | 中芯国际集成电路制造(北京)有限公司 | Gate doping method of semiconductor device |
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2013
- 2013-09-09 CN CN201310407704.6A patent/CN104425239B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050233525A1 (en) * | 2004-04-16 | 2005-10-20 | Yee-Chia Yeo | Gate electrode for a semiconductor fin device |
| CN101192525A (en) * | 2006-11-28 | 2008-06-04 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device grid preparation method |
| CN101894749A (en) * | 2009-05-20 | 2010-11-24 | 中芯国际集成电路制造(北京)有限公司 | Gate doping method of semiconductor device |
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| Publication number | Publication date |
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| CN104425239B (en) | 2017-10-17 |
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