CN104423516A - Reset circuit - Google Patents
Reset circuit Download PDFInfo
- Publication number
- CN104423516A CN104423516A CN201310380615.7A CN201310380615A CN104423516A CN 104423516 A CN104423516 A CN 104423516A CN 201310380615 A CN201310380615 A CN 201310380615A CN 104423516 A CN104423516 A CN 104423516A
- Authority
- CN
- China
- Prior art keywords
- signal
- reset
- logical block
- interface module
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a reset circuit. The reset circuit comprises a south bridge chip, a substrate management controller, a logical unit and an interface module. The south bridge chip and the substrate management controller output normal work signal or reset signal; the first input end of the logical unit is connected with the south bridge chip while the second input end thereof is connected with the substrate management controller, the logical unit outputs the reset signal or the normal work signal according to the signal received by the first and second input ends; the interface module is connected with the output end of the logical unit through a reset pin, the interface module executes the reset operation after receiving the reset signal and works normally work after receiving the normal work signal. The system is guaranteed for working normally while the interface module of the reset circuit is restarted.
Description
Technical field
The present invention relates to a kind of reset circuit.
Background technology
Peripheral Component Interconnect express slot (PCIE slot) is a kind of Peripheral Interface that current popularity rate is the highest.Because the reset of PCIE slot interface is that the signal exported by the output pin PLTRST_N of South Bridge chip directly controls, and this output pin controls the some Peripheral Interfaces of some other equipment on mainboard simultaneously, when wherein any one equipment occurs extremely needing to restart, just need to restart system, for this server for ask for something long-term stable operation or computing machine, can considerable influence be produced.
Summary of the invention
Given this, be necessary to provide a kind of when ensureing the reset circuit that system is normally run during a certain device reset in system.
A kind of reset circuit, comprising:
One South Bridge chip, comprises a reset signal output pin, and described South Bridge chip exports reset signal or normal working signal by described output pin;
One baseboard management controller, comprises a universal input output pin, and described baseboard management controller exports reset signal or normal working signal signal by described universal input output pin;
One logical block, comprise first and second input end and an output terminal, the first input end of described logical block connects the output pin of described South Bridge chip, second input end of described logical block connects the universal input output pin of described baseboard management controller, when first and second input end of described logical block all receives the normal working signal of South Bridge chip and baseboard management controller transmission, described logical block exports normal working signal by described output terminal; When any one reception reset signal of input end first season second of U1, output terminal sends reset signal;
One interface module, comprise a reset pin, described interface module is connected to the output terminal of described logical block by described reset pin, when only needing reseting interface module, described baseboard management controller exports reset signal, described South Bridge chip exports normal working signal, described logical block exports reset signal to described interface module, described interface module receives reset signal and resets, when wanting resetting system, the reset signal output pin of South Bridge chip exports reset signal, the equipment be connected with described South Bridge chip reset signal output pin in system receives reset signal and resets, the reset signal that described interface module receives the output of described logical block resets.
By baseboard management controller and logical block, when described reset circuit can ensure that South Bridge chip normally runs, described interface module is restarted.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of reset circuit better embodiment of the present invention.
Main element symbol description
| Reset circuit | 10 |
| South Bridge chip | 20 |
| Baseboard management controller | 30 |
| Logical block | U1 |
| Interface module | 40 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Please refer to Fig. 1, the better embodiment of reset circuit 10 of the present invention comprises South Bridge chip 20, baseboard management controller 30, interface module 40 and a logical block U1.
The output pin RST1 of described South Bridge chip 20 is connected to the first input end I1 of described logical block U1, the universal input output pin IO of described baseboard management controller 30 is connected to the second input end I2 of described logical block U1, and the output terminal O1 of described logical block U1 is connected to the reset pin RST2 of described interface module 40.The power end VCC of described logical block U1 is connected to a voltage input end P3V3, and described voltage input end P3V3 passes through electric capacity C ground connection, the earth terminal GND ground connection of described logical block U1.The output pin RST1 of described South Bridge chip 20 is the reset pin of other external equipments in connected system also, to control the reset operation of other external equipments.In the present embodiment, described interface module 40 is a PCIe slot, for connecting a PCIe equipment.
In present embodiment, described logical block U1 is one and door.
During normal use, described South Bridge chip 20 gives tacit consent to output high level signal through output pin RST1, described baseboard management controller 30 gives tacit consent to output high level signal through universal input output pin IO, first input end I1 and the second input end I2 of described logical block U1 all receive high level signal, described logical block U1 exports the reset pin RST2 of high level signal to described interface module 40 by described output terminal O1, and described interface module 40 normally works.
When described interface module 40 needs to restart, described baseboard management controller 30 exports a low level signal through universal input output pin IO, described South Bridge chip 20 still exports high level signal, the first input end I1 of described logical block U1 receives high level signal, the second input end I2 of described logical block U1 receives low level signal, described logical block U1 is through described output terminal O1 output low level signal to the reset pin RST2 of described interface module 40, and described interface module 40 restarts.The signal that the reset of other equipment that reason South Bridge chip 20 controls still is exported by the output pin RST1 of South Bridge chip 20 controls, and namely the reset pin of other equipment still receives high level signal, and when interface module 40 restarts, other equipment continues normal work.
When computer system needs to restart, the output pin RST1 of described South Bridge chip 20 and the equal output low level signal of universal input output pin IO of described baseboard management controller 30, the first input end I1 of described logical block U1 and the second input end I2 receives low level signal, the output terminal O1 output low level signal of described logical block U1 is to the reset pin RST2 of described interface module 40, described interface module 40 restarts, due to the output pin RST1 output low level signal of South Bridge chip 20, the reset pin of other equipment receives the laggard horizontal reset of low level signal.
By described baseboard management controller 30 and described logical block U1, described reset circuit 10 ensures that when docking port module 40 carries out reset operation system is normally run.
Finally it should be noted that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (3)
1. a reset circuit, comprising:
One South Bridge chip, comprises a reset signal output pin, and described South Bridge chip exports reset signal or normal working signal by described output pin;
One baseboard management controller, comprises a universal input output pin, and described baseboard management controller exports reset signal or normal working signal signal by described universal input output pin;
One logical block, comprise first and second input end and an output terminal, the first input end of described logical block connects the output pin of described South Bridge chip, second input end of described logical block connects the universal input output pin of described baseboard management controller, when first and second input end of described logical block all receives the normal working signal of South Bridge chip and baseboard management controller transmission, described logical block exports normal working signal by described output terminal; When any one reception reset signal of input end first season second of U1, output terminal sends reset signal;
One interface module, comprise a reset pin, described interface module is connected to the output terminal of described logical block by described reset pin, when only needing reseting interface module, described baseboard management controller exports reset signal, described South Bridge chip exports normal working signal, described logical block exports reset signal to described interface module, described interface module receives reset signal and resets, when wanting resetting system, the reset signal output pin of South Bridge chip exports reset signal, the equipment be connected with described South Bridge chip reset signal output pin in system receives reset signal and resets, the reset signal that described interface module receives the output of described logical block resets.
2. reset circuit as claimed in claim 1, is characterized in that: described logical block is one and door, and described normal working signal is high level signal, and described reset signal is low level signal.
3. reset circuit as claimed in claim 1, is characterized in that: described interface module is a PCIe slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310380615.7A CN104423516A (en) | 2013-08-28 | 2013-08-28 | Reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310380615.7A CN104423516A (en) | 2013-08-28 | 2013-08-28 | Reset circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104423516A true CN104423516A (en) | 2015-03-18 |
Family
ID=52972811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310380615.7A Pending CN104423516A (en) | 2013-08-28 | 2013-08-28 | Reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104423516A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808097A (en) * | 2016-02-26 | 2016-07-27 | 联想(北京)有限公司 | Information processing method and electronic device |
| CN108920317A (en) * | 2018-07-06 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of method and apparatus of diagnostic module external-connection displayer part and the multiplexing of PORT80 display device |
-
2013
- 2013-08-28 CN CN201310380615.7A patent/CN104423516A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808097A (en) * | 2016-02-26 | 2016-07-27 | 联想(北京)有限公司 | Information processing method and electronic device |
| CN105808097B (en) * | 2016-02-26 | 2019-05-31 | 联想(北京)有限公司 | A kind of information processing method and electronic equipment |
| CN108920317A (en) * | 2018-07-06 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of method and apparatus of diagnostic module external-connection displayer part and the multiplexing of PORT80 display device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150318 |
|
| WD01 | Invention patent application deemed withdrawn after publication |