CN104410573A - Package matching method based on TCAM (ternary content addressable memory) - Google Patents
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Abstract
The invention provides a package matching method based on a TCAM (ternary content addressable memory). The method comprises the following steps of calculating space compression grade (n) which is the number of the original table item capable of being compressed into one table item in the original TCAM chip according to package forwarding speed (r) and clock period (t) of a TCAM chip; selecting a TCAM chip in the suitable type according to the compression grade (n); compressing the original TCAM chip according to the compression grade (n); comparing a matching keyword and a rule base of the compressed TCAM chip when acquiring the matching keyword; and carrying out matching operations of n clock periods to obtain a matching result. By the scheme, the compression grade of TCAM items is dynamically selected according to requirements of the package forwarding speed of network equipment, the space utilization rate of the TCAM chip is improved on the premise that high-speed good user experience is ensured, and energy consumption is reduced. Moreover, the TCAM chip can be dynamically selected, so that the purchasing time of the TCAM chip is shortened, and the purchasing cost of the TCAM chip is reduced.
Description
Technical field
The present invention relates to internet data bag sorting technique field, be specifically related to a kind of bag matching process based on TCAM.
Background technology
Along with the Internet more and more gos deep into daily life, network traffics constantly increase, the quantity of various network application also rapidly increases, simultaneously, the malicious attack of thing followed new network also constantly occurs, thus result in increasing network core routing device and occur network congestion phenomenon, seriously reduce the forwarding performance of network core routing device.Given this, for the discharge pattern in recognition network is to provide more excellent service quality and network security level, packet classifier technique is arisen at the historic moment, and has become the core component of existing Internet architecture.Wherein, based on the high speed packet classification mechanism of three-state content addressing memory (TCAM) because having high bag rate matched, the true industrial standard of bag sorting technique has been become.
Every rule in TCAM chip rule base is expressed as strict tri-state (0,1 and *) form, and namely in TCAM, each bit can only get three kinds of values: 0,1 and * (representing outlier).If character string is all 0 identical with 1 with certain rule, then show that this character string meets this rule.Such as, character string " 110110 " and " 110010 " all meet rule " 11**10 ".TCAM by being contrasted by the strictly all rules in search keyword and rule base concurrently, and returns the matching result being positioned at TCAM position, location lower, to realize the matching operation of high speed within the fixed clock cycle.For reducing energy consumption, existing TCAM chip supports global mask register (GMR) and local mask register (BMR) mostly.As shown in Figure 1, GMR determines longitudinal bit position scope (as GMR 0 and GMR 2) of the participation matching operation in bag rule match, and BMR determines the TCAM memory block (such as Block0) that should be activated or forbid in matching operation.GMR and BMR co-operation can realize the function reducing TCAM chip energy consumption.
The inherent feature of TCAM chip rule base tri-state statement, determines and will unavoidably produce scope expansion problem in the matching process of range field.In typical IPv4 rule judges, protocol number and source IP address, object IP address all can be expressed as prefix form, namely all outlier * are all distributed in the end position (such as 11010***) of tri-state character string, and this makes above-mentioned three field informations in packet all can directly be stored in TCAM as a list item.But, source port number in packet and destination number information are characterized by real number scope in rule judges, such as, [1,65535] range field needs the tri-state character string of 30 prefix forms to characterize, and characterizing source port number and rule that destination slogan all belongs to [1,65535] judges then to need nearly 30 × 30=900 TCAM list item, this obviously result in serious scope expansion problem.Meanwhile, scope expands the power consumption that the list item sharp increase caused also increases TCAM chip, affects the practical application effect of TCAM chip.
Therefore, how to improve the space availability ratio of TCAM chip, expand to alleviate scope the negative effect brought, to the development of the packet classifier technique based on TCAM, there is vital impetus.
For solving the problem, prior art proposes a kind of C-TCAM (Compressed-TCAM: the TCAM of compression): adopt two-stage compression mechanism, every two range field (as the transport layer port number field) compression originally occupying two TCAM list items is stored in a TCAM list item, to improve the space availability ratio of TCAM chip.
But C-TCAM does not possess TCAM chip type selection function, can not according to the different demand of the network equipment forwarding rate dynamic adaptation TCAM chip type and space compression grade, cause chip space utilance not high, and energy consumption is higher.Such as, for IPv4 packet classification, if when TCAM chip bit wide is 144 bit, because non-range field comprises source address, destination address and protocol fields total length totally 72 bits, range field comprises source port and destination interface total length totally 32 bits, therefore, after adopting C-TCAM, the remaining bits width of every bar TCAM list item is 8 bits (144-72-32 × 2=8); But during TCAM chip according to 576 bit bit wides, C-TCAM method causes the remaining bits width of every bar TCAM list item to reach 440 bits, and wall scroll TCAM list item space utilance is only 23.6%.The reason producing this imagination is: C-TCAM algorithm does not possess dynamic TCAM chip type selection function, can only adopt range field two-stage compression mechanism regularly, and can not according to network equipment forwarding rate demand adjusting range field compression grade adaptively.
Summary of the invention
The object of the invention is to propose a kind of bag matching process based on TCAM, device forwards speed Network Based completes TCAM chip type Dynamic Selection and range field hierarchy compression intelligence is appraised and decided, on the basis ensureing the normal forwarding rate of the network equipment, improve the space availability ratio of TCAM chip.
For reaching above-mentioned purpose, the invention provides a kind of bag matching process based on TCAM, comprising:
According to the clock cycle t computer memory hierarchy compression n of Packet forwarding speed r and TCAM chip; This space compression grade n is the former list item quantity that can be compressed to 1 list item in former TCAM chip;
The TCAM chip of suitable type is selected according to described hierarchy compression n;
According to hierarchy compression n, former TCAM chip is compressed; Described compression comprises: by the n that occupies in former TCAM chip in n bar list item to source port number and destination slogan boil down to 1 list item, perform successively according to the top-down order in list item position;
When getting coupling keyword, the rule base of the TCAM chip after this coupling keyword and compression being contrasted, performs the matching operation of n clock cycle, obtain matching result.
Wherein, the described clock cycle t computer memory hierarchy compression n according to Packet forwarding speed r and TCAM chip comprises:
According to following formulae discovery Packet forwarding speed: the most parcel size of define grid is x bit, if certain network device interface bandwidth is y bit/s, then the Packet forwarding speed of TCAM-PC needs the numerical value reached to be calculated as follows:
r＝y/x；
Wherein, x is the most parcel size of network, and unit is bit; Y is network device interface bandwidth, and unit is bit/s;
Calculate the processing delay of the most parcel of described network:
d＝1/r
According to following formulae discovery TCAM chip hierarchy compression n:
that is:
Wherein, t is the clock cycle of TCAM chip, and unit is second.
Further, the maximum bit wide as TCAM chip is M, then for obtaining space compression rate large as far as possible, n should be:
The length of port numbers for the purpose of the length that the length that s is the length of source IP address, the length of IP address for the purpose of d, p are protocol number, s ' are source port number, d '.
Further, the described TCAM chip selecting suitable type according to described hierarchy compression n, comprising:
The bit wide z of the TCAM chip of described suitable type gets the smallest positive integral value of satisfied following condition:
(s+d+p)+(s'+d') n≤z≤M, and z ∈ C;
Wherein, C is the set of TCAM type, C={c|c ∈ N} (N=1,2,3 ...).
Wherein, described according to hierarchy compression n, compression is carried out to former TCAM chip and comprises:
In the list item of every bar compression, the rale store of high priority is in the position of side to the left, and the rale store of low priority is in side position to the right.
The described rule base by the TCAM chip after this coupling keyword and compression contrasts, and performs the matching operation of n clock cycle, obtains matching result, comprising:
I-th clock cycle, global mask register GMR activates GMR0+GMRi, i ∈ [1, n], forbids other all bit to reduce energy consumption;
If find, a matched rule is stored in TCAM memory block Block m, then, within the next clock cycle, activate all address blocks that numbering is less than or equal to m, forbid other all address blocks, to reduce energy consumption further;
When the matching operation of all n clock cycle all completes, from the rule matched, choose the minimum rule in address as final matching result.
Technique scheme has following beneficial effect:
Technique scheme is according to the Packet forwarding rate requirement Dynamic Selection TCAM entry hierarchy compression of the network equipment, namely, TCAM-PC (TCAM with Packet-forwarding-rate Constraints, meet the bag matching process based on TCAM of network equipment forwarding rate) rational space compression rate can be realized under the prerequisite ensureing network equipment high speed packet forwarding rate, ensure that under the prerequisite of the good Consumer's Experience of high speed, reduce the space hold degree of TCAM chip, improve the space availability ratio of TCAM chip, and reduce energy consumption; And achieve the Dynamic Selection of TCAM chip, rational chip type can be selected according to the different performance demand of network application, while realizing network application function, reduce time of choosing and the expense of TCAM chip.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is prior art TCAM structural representation;
Fig. 2 is the particular flow sheet of the bag matching process based on TCAM of the embodiment of the present invention one;
Fig. 3 is the architectural schematic of TCAM-PC of the present invention;
Fig. 4 is the workflow diagram of TCAM-PC of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The feature of the scope expansion problem that TCAM commensurate in scope process causes is: in the new TCAM list item of the every bar formed after expansion, the non-range field information such as source data packet address, destination address and protocol fields are identical, and only have range field such as source port number and destination slogan to be different.Based on above-mentioned feature, the present invention proposes a kind of TCAM chip selecting method---TCAM-PC improving TCAM space availability ratio.TCAM-PC passes through n (n=1,2 ...) bar comprises the TCAM list item boil down to one of different range field information (but simultaneously comprising identical non-range field information), and only retain the information of a non-range field in new list item upon compression, the object save TCAM chip-stored space to reach, improving space availability ratio.Said n is determined by the packet forwarding rate of the network equipment of configuration TCAM chip, and in the present invention, packet forwarding rate is defined as r packet/s (a forwarding r packet per second).
Embodiment one
As shown in Figure 2, be the flow chart of a kind of bag matching process based on TCAM of the present embodiment, comprise the following steps:
Step 201, according to the clock cycle t computer memory hierarchy compression n of Packet forwarding speed r and TCAM chip; This space compression grade n is the former list item quantity that can be compressed to 1 list item in former TCAM chip;
Step 202, selects the TCAM chip of suitable type according to described hierarchy compression n;
Step 203, according to hierarchy compression n, compresses former TCAM chip; Described compression comprises: by the n that occupies in former TCAM chip in n bar list item to source port number and destination slogan boil down to 1 list item, perform successively according to the top-down order in list item position;
Step 204, when getting coupling keyword, contrasting the rule base of the TCAM chip after this coupling keyword and compression, performing the matching operation of n clock cycle, obtain matching result.
Wherein, the described clock cycle t computer memory hierarchy compression n according to Packet forwarding speed r and TCAM chip comprises:
According to following formulae discovery Packet forwarding speed: the most parcel size of define grid is x bit, if certain network device interface bandwidth is y bit/s, then the Packet forwarding speed of TCAM-PC needs the numerical value reached to be calculated as follows:
r＝y/x；
Wherein, x is the most parcel size of network, and unit is bit; Y is network device interface bandwidth, and unit is bit/s;
Calculate the processing delay of the most parcel of described network:
d＝1/r
According to following formulae discovery TCAM chip hierarchy compression n:
that is:
Wherein, t is the clock cycle of TCAM chip, and unit is second.
Further, the maximum bit wide as TCAM chip is M, then for obtaining space compression rate large as far as possible, n should be:
The length of port numbers for the purpose of the length that the length that s is the length of source IP address, the length of IP address for the purpose of d, p are protocol number, s ' are source port number, d '.
Further, according to the TCAM chip that described hierarchy compression n selects suitable type, comprising:
The bit wide z of the TCAM chip of described suitable type gets the smallest positive integral value of satisfied following condition:
(s+d+p)+(s'+d') n≤z≤M, and z ∈ C;
Wherein, C is the set of TCAM type, C={c|c ∈ N} (N=1,2,3 ...).
Wherein, described according to hierarchy compression n, compression is carried out to former TCAM chip and comprises:
In the list item of every bar compression, the rale store of high priority is in the position of side to the left, and the rale store of low priority is in side position to the right.
Preferably, the described rule base by the TCAM chip after this coupling keyword and compression contrasts, and performs the matching operation of n clock cycle, obtains matching result, comprising:
I-th clock cycle, global mask register GMR activates GMR0+GMRi, i ∈ [1, n], forbids other all bit to reduce energy consumption;
If find, a matched rule is stored in TCAM memory block Block m, then, within the next clock cycle, activate all address blocks that numbering is less than or equal to m, forbid other all address blocks, to reduce energy consumption further;
When the matching operation of all n clock cycle all completes, from the rule matched, choose the minimum rule in address as final matching result.
The present embodiment has following beneficial effect:
The present embodiment is according to the Packet forwarding rate requirement Dynamic Selection TCAM entry hierarchy compression of the network equipment, namely, TCAM-PC can realize rational space compression rate under the prerequisite ensureing network equipment high speed packet forwarding rate, ensure that under the prerequisite of the good Consumer's Experience of high speed, reduce the space hold degree of TCAM chip, improve the space availability ratio of TCAM chip, and reduce energy consumption; And achieve the Dynamic Selection of TCAM chip, rational chip type can be selected according to the different performance demand of network application, while realizing network application function, reduce time of choosing and the expense of TCAM chip.
Embodiment two
TCAM-PC comprises at least three funtion parts, is described below:
1, TCAM chip space hierarchy compression computational methods:
The most parcel size of define grid is x bit, if certain network device interface bandwidth is y bit/s, then the Packet forwarding speed of TCAM-PC needs the numerical value reached to be calculated as follows:
r＝y/x (1)
In TCAM-PC, the bag processing delay of each packet is:
d＝1/r (2)
The clock cycle of definition of T CAM chip is t second, and former GREV quantity (the being defined as hierarchy compression n) deducibility that can be compressed to a rule in TCAM-PC is as follows:
Based on formula (1) to formula (3), can draw:
For typical IPv4 network, in each packet header, the length of source IP address and object IP address is 32bits, and the length of protocol number is 8bits, and the length of source port number and destination slogan is 16bits.If the maximum bit wide of TCAM chip is M, then for obtaining space compression rate large as far as possible, n should be:
2, TCAM chip selecting method:
Definition of T CAM type is for having the kind of different TCAM bit wide (if bit wide is 72 bits or 144 bits), and the set of existing TCAM type is C={c|c ∈ N} (N=1,2,3,), the then TCAM-PC mechanism TCAM chip type z (representing the bit wide of TCAM chip) that should select, can calculate according to such as lower inequality:
(32 × 2+8)+(16 × 2) n=72+32n≤z≤M and z ∈ C (6)
Note, for obtaining TCAM chip power-consumption as much as possible, z should get the smallest positive integral value of the inequality that satisfies condition (6).
3, TCAM-PC workflow:
Fig. 3 is the architectural schematic of TCAM-PC, and wherein, S_IP is address for the purpose of source address, D_IP, Prot is protocol number, S_Port is port for the purpose of source port, D_Port.
As shown in Figure 4, the course of work of TCAM-PC is as follows:
Step 401:TCAM-PC calculates the hierarchy compression n of TCAM memory space based on TCAM chip space hierarchy compression computational methods (formula (1) is to formula (5)); Then suitable TCAM chip type is selected based on TCAM chip selecting method (formula (6));
Step 402:TCAM-PC is according to originally occupying every n of n bar TCAM list item to source port number and destination slogan boil down to 1 list item, and perform successively (such as starting compression, until be compressed to Block m from the list item of Block 0) according to the top-down order in list item position; And in list item after every bar compression, the rale store of high priority is in side position to the left, and the rale store of low priority is in side position to the right;
Step 403: when a coupling keyword arrives, keyword and rule base contrast by TCAM-PC, perform the matching operation of n clock cycle: i-th clock cycle, GMR activates GMR0+GMRi, i ∈ [1, n], all the other all bits are all forbidden to reduce energy consumption; In addition, if find, a matched rule is stored in Block m, then, within the next clock cycle, only activate all address blocks (such as Block l, l≤m) that numbering is less than or equal to m, remaining address block is all forbidden, to reduce energy consumption further; When the matching operation of all n clock cycle all completes, TCAM-PC chooses the minimum rule in address as final matching result from the rule matched.
The present embodiment is according to the Packet forwarding rate requirement Dynamic Selection TCAM entry hierarchy compression of the network equipment, namely TCAM-PC can realize rational space compression rate under the prerequisite ensureing network equipment high speed packet forwarding rate, both ensure that the Consumer's Experience that high speed is good, again reduce the space hold degree of TCAM chip, improve the space availability ratio of TCAM chip, and reduce energy consumption.The Dynamic Selection of TCAM chip can be realized simultaneously, rational chip type can be selected according to the different performance demand of network application, while realizing network application function, reduce time of choosing and the expense of TCAM chip.
Those skilled in the art can also recognize the various illustrative components, blocks (illustrativelogical block) that the embodiment of the present invention is listed, unit, and step can pass through electronic hardware, computer software, or both combinations realize.For the replaceability (interchangeability) of clear displaying hardware and software, above-mentioned various illustrative components (illustrativecomponents), unit and step have universally described their function.Such function is the designing requirement realizing depending on specific application and whole system by hardware or software.Those skilled in the art for often kind of specifically application, can use the function described in the realization of various method, but this realization can should not be understood to the scope exceeding embodiment of the present invention protection.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1., based on a bag matching process of TCAM, it is characterized in that, comprising:
According to the clock cycle t computer memory hierarchy compression n of Packet forwarding speed r and TCAM chip; This space compression grade n is the former list item quantity that can be compressed to 1 list item in former TCAM chip;
The TCAM chip of suitable type is selected according to described hierarchy compression n;
According to hierarchy compression n, former TCAM chip is compressed; Described compression comprises: by the n that occupies in former TCAM chip in n bar list item to source port number and destination slogan boil down to 1 list item, perform successively according to the top-down order in list item position;
When getting coupling keyword, the rule base of the TCAM chip after this coupling keyword and compression being contrasted, performs the matching operation of n clock cycle, obtain matching result.
2. method according to claim 1, is characterized in that, the described clock cycle t computer memory hierarchy compression n according to Packet forwarding speed r and TCAM chip comprises:
The numerical value reached is needed according to following formulae discovery Packet forwarding speed:
r＝y/x；
Wherein, x is the size of the most parcel of network, and unit is bit; Y is network device interface bandwidth, and unit is bit/s;
Calculate the processing delay of the most parcel of described network:
d＝1/r
According to following formulae discovery TCAM chip hierarchy compression n:
that is:
Wherein, t is the clock cycle of TCAM chip, and unit is second.
3. method according to claim 2, is characterized in that, the maximum bit wide as TCAM chip is M, then, then for obtaining space compression rate large as far as possible, n should be:
The length of port numbers for the purpose of the length that the length that s is the length of source IP address, the length of IP address for the purpose of d, p are protocol number, s ' are source port number, d '.
4. method according to claim 3, is characterized in that, the described TCAM chip selecting suitable type according to described hierarchy compression n, comprising:
The bit wide z of the TCAM chip of described suitable type gets the smallest positive integral value of satisfied following condition:
(s+d+p)+(s'+d') n≤z≤M, and z ∈ C;
Wherein, C is the set of TCAM type, C={c|c ∈ N} (N=1,2,3 ...).
5. method according to claim 1, is characterized in that, described according to hierarchy compression n, carries out compression comprise former TCAM chip:
In the list item of every bar compression, the rale store of high priority is in the position of side to the left, and the rale store of low priority is in side position to the right.
6. method according to claim 1, is characterized in that, the described rule base by the TCAM chip after this coupling keyword and compression contrasts, and performs the matching operation of n clock cycle, obtains matching result, comprising:
I-th clock cycle, global mask register GMR activates GMR0+GMRi, i ∈ [1, n], forbids other all bit to reduce energy consumption;
If find, a matched rule is stored in TCAM memory block Block m, then, within the next clock cycle, activate all address blocks that numbering is less than or equal to m, forbid other address block, to reduce energy consumption further;
When the matching operation of all n clock cycle all completes, from the rule matched, choose the minimum rule in address as final matching result.
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