CN104410406A - Asynchronous counter circuit - Google Patents
Asynchronous counter circuit Download PDFInfo
- Publication number
- CN104410406A CN104410406A CN201410427073.9A CN201410427073A CN104410406A CN 104410406 A CN104410406 A CN 104410406A CN 201410427073 A CN201410427073 A CN 201410427073A CN 104410406 A CN104410406 A CN 104410406A
- Authority
- CN
- China
- Prior art keywords
- trigger
- circuit
- reset signal
- reset
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides an asynchronous counter circuit. The asynchronous counter circuit consists of a cascade trigger counting circuit, a reset signal generating circuit and a reset circuit. The asynchronous counter circuit is characterized in that the trigger load of a high-frequency counting clock is minimized only by additionally providing a trigger for constructing a reset signal on the basis of a conventional cascade trigger counting circuit, so that the power consumption of a counter can be effectively controlled. On the other hand, the timing sequence problem of clearing of an asynchronous counter can be solved effectively through the adopted reset signal and reset way.
Description
Technical field
The present invention relates to a kind of asynchronous counter circuit, can be applicable to have in the integrated circuit (IC) design of lower power consumption requirement counter.
Background technology
Counter is a kind of circuit common in integrated circuit, is mainly divided into coincidence counter and asynchronous counter two class.
Under the trigger of coincidence counter is all operated in counting clock, under unified clock-time scheduling, the sequential controllability of coincidence counter is good, is easy to design.Under trigger is all operated in counting clock, so the clock load of coincidence counter is comparatively large, on the other hand, the combinational logic more complicated needed for coincidence counter, so the power consumption of coincidence counter is larger.
What asynchronous counter adopted is the mode of trigger cascade, only first order flip-flop operation is under counting clock, rear class trigger clock is the data that prime exports, therefore trigger activity reduces by half step by step, and asynchronous counter does not need the complex logics such as adder, so asynchronous counter has the feature of small scale, low-power consumption.The major drawbacks of asynchronous counter is used to be, because the clock of each trigger is different, the mode of clearing generally by resetting of asynchronous counter, and there is the situations such as sequential is indefinite, median due to asynchronous count value, need the reset signal that could be generated safety by special trigger sample circuit, under these sample trigger are operated in counting clock, adds additional the load of counting clock.
Along with the generally application of RFID, portable and active or passive consumer electronic product, power consumption more and more becomes the bottleneck that properties of product and Consumer's Experience promote.Such as, in RFID application, the power consumption of whole chip is to the microwatt (10 of extremely low power dissipation
-6watt) level, wherein, the power consumption on trigger and clock network thereof is particularly crucial.In known asynchronous counter circuit, need to be processed count value by two triggers be operated under counting clock, to obtain the reset signal that the duration is half counted clock cycle, the asynchronous counter circuit of this two trigger expenses is still not ideal enough for the application of extremely low power dissipation.
The present invention is intended to propose a kind of only ancillary cost trigger and the asynchronous counter circuit of timing safety, to meet the application harsher to power consumption requirements.
Summary of the invention
The trigger cost of asynchronous flip-flops ancillary cost is reduced to minimum by the circuit that the present invention proposes, and can ensure the timing safety of this circuit on using simultaneously.
The asynchronous counter circuit that the present invention proposes, comprises cascaded triggers counting circuit, reset signal generative circuit and clear circuit three part.Wherein:
Cascaded triggers counting circuit is made up of the trigger of multiple cascade, and the clock of first order trigger is from counting clock, and the clock of rear class trigger exports from the anti-phase of prime trigger or homophase; The data of first order trigger export from the selector of clear circuit, and the data of rear class trigger are from the anti-phase output of trigger at the corresponding levels; The reset of first order trigger resets from input, and the reset of rear class trigger exports from the logical AND gate of clear circuit.
Reset signal generative circuit is made up of a count value decision circuitry and a sample trigger, and the count value of count value decision circuitry to cascaded triggers counting circuit judges, sample trigger sample this judged result generate reset signal;
Clear circuit is made up of a selector and a logical AND gate, selector selects the input of anti-phase output as first order cascaded triggers of signal 1 or first order cascaded triggers according to reset signal, input resets and carries out logical AND with reset signal by logical AND gate, and it exports as the reset of the cascaded triggers counting circuit second level to most final stage trigger.Cascaded triggers counting circuit realizes asynchronous counting, realizes plus coujnt when the clock of rear class trigger is the anti-phase output of prime trigger, realizes subtraction count when the clock of rear class trigger is the homophase output of prime trigger; The result of reset signal generative circuit to counting processes, and generates the reset signal that effective width is a counted clock cycle when reaching the count value of expectation; Clear circuit is for realizing the clearing to cascaded triggers.
In the present invention, in fact the trigger in cascaded triggers counting circuit is distinguished:
A) when reset signal is invalid, the data of first order trigger and rear class trigger all come from the anti-phase output of trigger at the corresponding levels.
B) when reset signal is effective, the clearing of first order trigger is realized by data terminal, namely signal 1 ' b1 input is selected on effective edge of counting clock by the selector of clear circuit, the clearing of rear class trigger is then direct to be realized by reset terminal, and namely the reset of rear class is all from the reset signal that clear circuit exports.
By distinguishing the clearing mode of the cascaded triggers first order and rear class, in reset signal generative circuit, a trigger only can be used to compare count results and sample, clock and the counting clock of this trigger are anti-phase, the reset signal effective width exported continues a counted clock cycle, can guarantee by aforementioned clearing mode the safety resetting sequential.
In addition, because reset signal generative circuit use only a clock and the anti-phase trigger of counting clock, when this trigger goes sample count result, new count value stabilizes half period, and the clearing count value therefore set in circuit adds 1 on the basis of the clearing count value required by reality.
Accompanying drawing explanation
Three asynchronous counter circuit figure (0 ~ 4 plus coujnt) that Fig. 1 the present invention realizes
Fig. 2 plus coujnt 0 ~ 3 resets sequential chart
Fig. 3 plus coujnt 0 ~ 4 resets sequential chart
Embodiment
Below in conjunction with accompanying drawing, embodiments of the present invention are described.
Fig. 1 is 3 the asynchronous adder counting circuits realized according to the present invention, and count range is 0 ~ 3, resets when namely counting down to 3.Wherein, cascaded triggers counting circuit (1) is made up of three triggers (11,12,13), reset signal generative circuit (2) is made up of count value decision circuitry (21) and a sample trigger (22), and clear circuit (3) is made up of a selector (31) and a logical AND gate (32).
In cascaded triggers counting circuit (1), 11 is first order trigger, 12,13 is rear class trigger, the clock of first order trigger (11) is from counting clock, the clock of rear class trigger (12,13) is respectively the anti-phase output of prime trigger, is therefore plus coujnt.The data of first order trigger (11) export from the selector (31) in clear circuit, and the data of rear class trigger (12,13) are from the anti-phase output of trigger at the corresponding levels.The reset of first order trigger (11) resets from input, and the generation that the reset of rear class trigger (12,13) exports from logical AND gate in clear circuit (32) resets.
In reset signal generative circuit (2), count value decision circuitry (21) compares count value, and according to as previously mentioned, for the scope of counting 0 ~ 3, the actual count value judged is 4.The clock of sample trigger (22) is the inversion clock of counting clock, is reset to input and resets, and when count value reaches 4, it is by the reset signal of a sampling output counted clock cycle.
In clear circuit (3), selector (31) is output signal 1 ' b1 when reset signal is effectively 0, reset signal is invalid be 1 time the output cascade trigger first order (11) anti-phase output.
Fig. 2 illustrates the sequential of above-mentioned asynchronous counter circuit.Q3Q2Q1 constitutes the asynchronous count value of 3, resets after release, adds 1 at the rising edge of each counting clock.When counting down to 4 (Q3Q2Q1=100), after half counted clock cycle, sample trigger exports the reset signal Qx of a clock cycle, the rear class trigger (Q1, Q2) of cascade resets by reset signal Qx at once, at next counting clock rising edge, the value of first order trigger Q1 is set to 1 by selector by reset signal, and after this counter continues the counting when the rising edge of counting clock arrives, thus achieves 0 ~ 3 cycle count.
As can see from Figure 2, owing to only used the sample trigger (22) that is operated in counting clock trailing edge, and in order to the safety realizing aforementioned manner resets, the count value 4 of half period has also been used outside 0 ~ 3 count value, but for external system, this asynchronous counter rising edge that to be no matter counting or sampling be all at counting clock, so count value 4 is externally invisible, only belong to the necessary part that asynchronous counter inside resets mechanism, from actual effect, the count value 4 of this half clock cycle can be regarded as a part for count value 0.
Notice, when the reset signal that sample trigger (22) exports is effective, rear class trigger (Q1, Q2) is reset immediately, and first order trigger Q1 will keep current value half period just can be set to 1, be 0 according to Q1 currency and be 1 have two kinds of situations, Fig. 2 illustrate reset signal effective time Q1 currency be the situation of 0, now count value 0 maintains half period, Fig. 3 illustrate reset signal effective time Q1 currency be the situation of 1, now count value 0 does not occur, count value 1 is by 1.5 clock cycle of maintenance.In this case, whether the judgement of counting 0 value is effectively judged by reset signal.
The sequential of asynchronous counter circuit when Fig. 3 illustrates count range 0 ~ 4.Be still the asynchronous count value that Q3Q2Q1 forms 3, count range is 0 ~ 4, and inner reset signal (Q3Q2Q1=101) when count value is 5 generates.When count value is 5, the value of first order trigger Q1 has been 1, after half period, rear class trigger resets by reset signal, now count value becomes 1 from 5, back to back counting clock rising edge, count value remains that 1 is constant until next counting clock rising edge becomes 2, so after 5 of half clock cycle and then 1.5 clock cycle 1.After this counter continues count when the rising edge of counting clock arrives and circulate.Do not occur although count 0 value in this case, when needs counting 0 is worth, reset signal is effective, so judge whether current count value and reset signal whether be effectively known current count value are 0 by combination.
As mentioned above, the present invention only additionally adopts a trigger for generating the asynchronous counter circuit of reset signal by achieving asynchronous counter circuit inside introducing external sightless counting judgment value (actual visible maximum count value adds 1), and ensure that count value is in inside and the external fail safe using sequential by the trigger that employing two kinds the is different mode that resets, judging that the mode of count value and reset signal solves counting 0 and is worth the non-existent problem of possibility by combining in addition.The cost of additional flip-flop to be reduced to minimum by the asynchronous counter circuit that the present invention proposes, and ensure that the timing safety in use simultaneously.
Should be understood that; the above-mentioned description for embodiment is comparatively concrete; just in order to better circuit disclosed in this invention be set forth, can not as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (4)
1. an asynchronous counter circuit, is characterized in that comprising cascaded triggers counting circuit, reset signal generative circuit and clear circuit, wherein:
Cascaded triggers counting circuit is made up of the trigger of multiple cascade, and the clock of first order trigger is from counting clock, and the clock of rear class trigger exports from the anti-phase of prime trigger or homophase; The data of first order trigger export from the selector of clear circuit, and the data of rear class trigger are from the anti-phase output of trigger at the corresponding levels; The reset of first order trigger resets from input, and the reset of rear class trigger exports from the logical AND gate of clear circuit.
Reset signal generative circuit is made up of a count value decision circuitry and a sample trigger, and the count value of count value decision circuitry to cascaded triggers counting circuit judges, sample trigger sample this judged result generate reset signal;
Clear circuit is made up of a selector and a logical AND gate, selector selects the input of anti-phase output as first order cascaded triggers of signal 1 or first order cascaded triggers according to reset signal, input resets and carries out logical AND with reset signal by logical AND gate, and it exports as the reset of the cascaded triggers counting circuit second level to most final stage trigger.
2. asynchronous counter circuit according to claim 1, it is characterized in that the input clock of the sample trigger in reset signal generative circuit and counting clock anti-phase, this trigger be reset to input reset.
3. asynchronous counter circuit according to claim 1, is characterized in that the effective width of the reset signal that the sample trigger in reset signal generative circuit exports is a counted clock cycle.
4. asynchronous counter circuit according to claim 1, it is characterized in that the selector in clear circuit is select signal with reset signal, export selection 1 when reset signal is 0, export the anti-phase output selecting first order cascaded triggers when reset signal is 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410427073.9A CN104410406B (en) | 2014-08-27 | 2014-08-27 | Asynchronous counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410427073.9A CN104410406B (en) | 2014-08-27 | 2014-08-27 | Asynchronous counter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104410406A true CN104410406A (en) | 2015-03-11 |
| CN104410406B CN104410406B (en) | 2017-05-17 |
Family
ID=52648007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410427073.9A Active CN104410406B (en) | 2014-08-27 | 2014-08-27 | Asynchronous counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104410406B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105955005A (en) * | 2016-07-01 | 2016-09-21 | 上海市同济医院 | Cardiopulmonary resuscitation timing beat meter and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56114442A (en) * | 1980-02-13 | 1981-09-09 | Nec Corp | Frequency dividing circuit |
| US20090304140A1 (en) * | 2008-06-05 | 2009-12-10 | Realtek Semiconductor Corp. | Asynchronous ping-pong counter and therof method |
| CN102111147A (en) * | 2009-12-23 | 2011-06-29 | 北京中电华大电子设计有限责任公司 | Asynchronous counter circuit and realizing method thereof |
| CN102224678A (en) * | 2008-11-27 | 2011-10-19 | 三美电机株式会社 | Counter circuit and protection circuit |
-
2014
- 2014-08-27 CN CN201410427073.9A patent/CN104410406B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56114442A (en) * | 1980-02-13 | 1981-09-09 | Nec Corp | Frequency dividing circuit |
| US20090304140A1 (en) * | 2008-06-05 | 2009-12-10 | Realtek Semiconductor Corp. | Asynchronous ping-pong counter and therof method |
| CN102224678A (en) * | 2008-11-27 | 2011-10-19 | 三美电机株式会社 | Counter circuit and protection circuit |
| CN102111147A (en) * | 2009-12-23 | 2011-06-29 | 北京中电华大电子设计有限责任公司 | Asynchronous counter circuit and realizing method thereof |
Non-Patent Citations (2)
| Title |
|---|
| 樊民革等: ""一种消除异步电路亚稳态的逻辑控制方法"", 《电子测量技术》 * |
| 王江舟: ""一种基于延时优化的异步计数器设计"", 《电脑知识与技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105955005A (en) * | 2016-07-01 | 2016-09-21 | 上海市同济医院 | Cardiopulmonary resuscitation timing beat meter and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104410406B (en) | 2017-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Kathuria et al. | A review of clock gating techniques | |
| CN104024979B (en) | It is used for energy efficiency and method, the equipment of energy saving, and system including what the frequency that non-frame is perceived was selected | |
| CN107463236B (en) | Reset detection circuit and reset detection method | |
| CN102111147B (en) | Asynchronous counter circuit and realizing method thereof | |
| Lalitha et al. | A review of manchester, miller, and fm0 encoding techniques | |
| KR20200069347A (en) | Inverted phase mode logic gates | |
| Strollo et al. | Low power flip-flop with clock gating on master and slave latches | |
| Wimer et al. | A look-ahead clock gating based on auto-gated flip-flops | |
| CN101593221B (en) | Method and circuit for preventing different zone clocks from burr during dynamic switching | |
| CN104410406A (en) | Asynchronous counter circuit | |
| JP2010282399A (en) | Clock switch circuit | |
| Moreira et al. | Return-to-One DIMS Logic on 4-phase m-of-n Asynchronous Circuits | |
| Gaur et al. | HDL implementation of prepaid electricity billing machine on FPGA | |
| Ismail et al. | Low power design of Johnson counter using clock gating | |
| CN110945372B (en) | Method for detecting at least one spur in an electrical signal and device for carrying out said method | |
| Xiang et al. | Design of a low-power pulse-triggered flip-flop with conditional clock technique | |
| Dillen et al. | Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules | |
| Vakil et al. | Comparitive analysis of null convention logic and synchronous CMOS ripple carry adders | |
| Wu et al. | Low power sequential circuit design by using priority encoding and clock gating | |
| Kim et al. | Low-power CMOS synchronous counter with clock gating embedded into carry propagation | |
| Basha et al. | Implementation of LFSR counter using CMOS VLSI technology | |
| Gupta | Clock power analysis of low power clock gated arithmetic logic unit on different FPGA | |
| Ni et al. | MRCO: A multi-ring convergence oscillator-based high-efficiency true random number generator | |
| CN105656472B (en) | A kind of priority decision circuitry | |
| CN105049003A (en) | Synchronised logic circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Applicant after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Applicant before: Beijing CEC Huada Electronic Design Co., Ltd. |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |