CN104409358A - Manufacture method of groove in groove semiconductor power device - Google Patents

Abstract

The invention discloses a manufacture method of a groove in a groove semiconductor power device, which can increase the width of polycrystalline silicon field plates. The method comprises the following steps: firstly, providing a semiconductor base plate of which the first main surface is the surface of a first conduction type epitaxial layer and the second main surface is the surface of a first conduction type substrate, secondly, forming a sacrificial oxide layer on the first main surface through deposition or thermal growth, thirdly, selectively masking and etching the sacrificial oxide layer and the epitaxial layer, so as to form the groove, fourthly, removing photoresist and the sacrificial oxide layer, fifthly, developing a gate oxide layer on the first main surface and the wall of the groove, sixthly, depositing polycrystalline silicon in the first main surface and the interior of the groove at the same time, seventhly, developing a sacrificial oxide layer on the polycrystalline silicon, eighthly, etching the sacrificial oxide layer on the polycrystalline silicon on the first main surface, ninthly, etching the polycrystalline silicon, tenthly, etching the sacrificial oxide layer on the polycrystalline silicon in the groove, and eleventhly, etching the polycrystalline silicon, so as to form polycrystalline silicon field plates which are distributed in a bilaterally symmetrical way in the groove. The method is particularly applied to the manufacture of partial pressure grooves in a terminal protected zone.

Description

The manufacture method of the groove in a kind of channel-type semiconductor device

Technical field

The present invention relates to a kind of manufacture method of channel-type semiconductor device, refer more particularly to the manufacture method of the groove in a kind of channel-type semiconductor device.

Background technology

The application number applied on February 2nd, 2013 to State Intellectual Property Office for applicant shown in Figure 12 is 201310041166.3, denomination of invention is trench semiconductor power device and trench semiconductor power device terminal protection structure in manufacture method and terminal protection structure; the width b of the polysilicon field plate in this terminal protection structure is usually less than 22% of groove width a; and; polycrystalline silicon etching process fluctuation is larger to the widths affect of polysilicon field plate; cause the withstand voltage lack of homogeneity of device; chip rate of good is low, adds manufacturing cost.

Summary of the invention

Technical problem to be solved by this invention is: the manufacture method providing the groove in a kind of channel-type semiconductor device that can increase polysilicon field plate width.

In order to solve the problems of the technologies described above, the technical solution used in the present invention is: the manufacture method of the groove in a kind of channel-type semiconductor device, the steps include:

1) in the first conductivity type substrate, grow the first conductive type epitaxial layer, form semiconductor substrate, the surface of the first conductive type epitaxial layer is the first interarea, and the surface of the first conductivity type substrate is the second interarea;

2) on the first interarea, one deck sacrificial oxide layer is formed by deposit or heat growth;

3) optionally shelter and etches sacrificial oxide layer and epitaxial loayer, form groove;

4) photoresist and sacrificial oxide layer is removed;

5) on the first interarea and trench wall, gate oxide is grown;

6) the depositing polysilicon while of on the gate oxide on the first interarea and in groove, the thickness of polysilicon should be less than 1/2nd of described groove width;

7) at described grown on polysilicon sacrificial oxide layer;

8) sacrificial oxide layer on the polysilicon on the gate oxide on the first interarea is etched;

9) under the blocking of sacrificial oxide layer, etch polysilicon;

10) sacrificial oxide layer in etching groove on polysilicon;

11) overall etch polysilicon, forms the polysilicon field plate be symmetrically arranged in groove.

As a kind of preferred version, described 9) in the process of step etch polysilicon, the severity control of etching is between 1/1 to two/3rd.

The invention has the beneficial effects as follows: the present invention is by generating layer of oxide layer operator guards on the polysilicon layer to reduce the etching to the polysilicon in groove; thus add polysilicon field plate width; realize polysilicon field plate width b and be increased to about 45% of groove width a; reduce the impact of technological fluctuation on field plate width; improve chip rate of good, reduce manufacturing cost.

Accompanying drawing explanation

Fig. 1 ~ Figure 11 is the manufacture method of groove in channel-type semiconductor device of the present invention.

Reference numeral in Fig. 1 to Figure 11 is: 6, N-type substrate, 7, N-type epitaxy layer, 8, sacrificial oxide layer, 9, gate oxide, 10, polysilicon, 11, sacrificial oxide layer, 12, polysilicon field plate, 13, photoresist, 14, groove.

Figure 12 is the structural representation of groove in the channel-type semiconductor device described in background technology.

Embodiment

Below in conjunction with accompanying drawing 1 ~ Figure 11, describe the manufacture method of groove in channel-type semiconductor device for N grooved semiconductor power MOS (Metal Oxide Semiconductor) device in detail, the steps include:

1) in heavily doped N-type substrate 6, grow lightly doped N-type epitaxy layer 7, formed using N-type epitaxy layer 7 surface as the first interarea with using N-type substrate 6 surface as the semiconductor substrate of the second interarea---shown in Figure 1;

2) on the first interarea, one deck sacrificial oxide layer 8 is formed by deposit or heat growth---shown in Figure 2;

3) on sacrificial oxide layer 8, photoresist 13 is coated, and the region that will etch of developing, optionally shelter and etches sacrificial oxide layer 8 and N-type epitaxy layer 7, groove 14---shown in Figure 3, the width of groove 14 is a in formation;

4) photoresist 13 and sacrificial oxide layer 8 is removed---shown in Figure 4;

5) on the first interarea and trench wall, gate oxide 9 is grown---shown in Figure 5;

6) on the gate oxide 9 on the first interarea and in groove 14, depositing polysilicon 10---shown in Figure 6, the thickness D of polysilicon 10 should be less than 1/2nd of the width a of groove 14, namely simultaneously

7) 6) polysilicon 10 that formed grows sacrificial oxide layer 11---shown in Figure 7;

8) sacrificial oxide layer 11 on the polysilicon 10 on the gate oxide 9 on sacrificial oxide layer 11 i.e. the first interarea above the first interarea is etched---shown in Figure 8;

9) polysilicon 10 (polysilicon 10 in groove 14 is not etched due to the blocking of sacrificial oxide layer 11 be subject on groove 14 sidewall) above the first interarea is etched---shown in Figure 9, the depth H of etch polysilicon 10 should between 1/to two/3rd of polysilicon 10 thickness D, that is: $\frac{1}{3}D<H<$ $\frac{1}{2}D;$

10) sacrificial oxide layer 11 in etching groove 14 on polysilicon 10---shown in Figure 10;

11) overall etch polysilicon 10, in groove 14, form the polysilicon field plate 12 be symmetrically arranged, its width b can reach 45% of groove width a---and shown in Figure 11.

Claims (2)

1. a manufacture method for the groove in channel-type semiconductor device, the steps include:

1) in the first conductivity type substrate, grow the first conductive type epitaxial layer, form semiconductor substrate, the surface of the first conductive type epitaxial layer is the first interarea, and the surface of the first conductivity type substrate is the second interarea;

2) on the first interarea, one deck sacrificial oxide layer is formed by deposit or heat growth;

3) optionally shelter and etches sacrificial oxide layer and epitaxial loayer, form groove;

4) photoresist and sacrificial oxide layer is removed;

5) on the first interarea and trench wall, gate oxide is grown;

6) the depositing polysilicon while of on the gate oxide on the first interarea and in groove, the thickness of polysilicon should be less than 1/2nd of described groove width;

7) at described grown on polysilicon sacrificial oxide layer;

8) sacrificial oxide layer on the polysilicon on the gate oxide on the first interarea is etched;

9) under the blocking of sacrificial oxide layer, etch polysilicon;

10) sacrificial oxide layer in etching groove on polysilicon;

11) overall etch polysilicon, forms the polysilicon field plate be symmetrically arranged in groove.

2. the manufacture method of the groove in channel-type semiconductor device according to claim 1, is characterized in that: described 9) in the process of step etch polysilicon, the severity control of etching is between 1/1 to two/3rd.