CN104409035B - Pixel circuit and driving method thereof - Google Patents
Pixel circuit and driving method thereof Download PDFInfo
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- CN104409035B CN104409035B CN201410734126.1A CN201410734126A CN104409035B CN 104409035 B CN104409035 B CN 104409035B CN 201410734126 A CN201410734126 A CN 201410734126A CN 104409035 B CN104409035 B CN 104409035B
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Abstract
The invention provides a pixel circuit and a driving method thereof. The display unit is coupled to the common electrode and the data line. The display unit writes a data voltage into the memory unit in a data writing period and forms a pixel voltage in the display unit according to the data voltage. The voltage adjusting unit is coupled between the display unit and the memory unit and used for controlling the display unit. The voltage adjusting unit adjusts the pixel voltage of the display unit according to the next-stage scanning signal of the pixel circuit during the voltage adjusting period, so that the pixel voltage is equal to the direct current sharing voltage provided by the sharing electrode.
Description
Technical field
The present invention relates to a kind of display device and method, the image element circuit of more particularly to a kind of display device and its driving
Method.
Background technology
With science and technology progress and people for the requirement of quality of life, Wearable product thus emerge.Probe into Wearable
The cause that product emerges should be Wearable product compared to portable product (such as mobile phone, tablet PC) have it is lighter and
The advantage being easy to carry about with one.Additionally, existing Wearable product is often equipped with condition monitoring mechanism, for quality of life requires
Higher consumer can tend to buy Wearable product to understand the state of a person, and correspondingly adjust its work and rest, to
Maintain its personal lifestyle quality.
Because Wearable product is more preferably frivolous compared to above-mentioned portable product, correspondingly, the battery of Wearable product holds
Amount is also reduced therewith, therefore, Wearable product becomes all the more harsh for the requirement of the power consumption of itself.Hereby it is possible to significantly
Pixel memories (Memory In Pixel, the MIP) technology for reducing power consumption is increasingly taken seriously.Due to traditional MIP circuits
Framework is to form two kinds of different crampings of high and low current potential from common voltage Vcom using the two reverse signals of Vb and Vw, and is taken
The characteristic of the periodic inversion with exchange common voltage AC-Vcom inverting the phase place of above-mentioned Vb and Vw signals, to avoid liquid crystal
It is impaired.Therefore, traditional MIP circuit frameworks are only applicable to exchange common voltage AC-Vcom.
However, Jing experiments are learnt, exchange common voltage AC-Vcom can produce coupled noise via parasitic capacitance
(coupling noise), this coupled noise can disturb the induction apparatuss of contact surface plate, cause contact surface plate capability error, thus,
The product for causing collocation contact surface plate the MIP circuits of conventionally employed exchange common voltage AC-Vcom are not suitable for into.
As can be seen here, above-mentioned existing mode, it is clear that still suffer from inconvenience and defect, and have much room for improvement.It is above-mentioned in order to solve
Problem, association area does not develop yet for a long time appropriate solution there's no one who doesn't or isn't painstakingly seeking solution.
The content of the invention
The content of the invention aims to provide simplifying for the present invention and makes a summary, so that reader possesses basic understanding to the present invention.This
The complete overview of the content of the invention and non-invention, and its be not intended in the key/critical element for pointing out the embodiment of the present invention or
Define the scope of the present invention.
One purpose of present invention is to provide a kind of image element circuit and its driving method, so as to improving prior art
Shortcoming.
For achieving the above object, a technical approach of present invention is with regard to a kind of image element circuit.It is aforementioned single comprising showing
Unit, memory cell and voltage-adjusting unit.Display unit is coupled to shared electrode and data wire.Display unit writes in data
Data voltage is write memory cell by period, and according to data voltage forming pixel voltage in display unit.Voltage is adjusted
Whole unit is coupled between display unit and memory cell and to control display unit.Voltage-adjusting unit is in Voltage Cortrol
Period according to the next stage scanning signal of image element circuit to adjust the pixel voltage of display unit so that pixel voltage is equal to
The direct current share voltage that shared electrode is provided.
For achieving the above object, another technical approach of present invention is with regard to a kind of pixel circuit drive method.It is aforementioned
Image element circuit includes display unit and memory cell, and display unit is coupled to shared electrode.Aforementioned pixel circuit drive method
Comprising subsequent step：Data voltage is write into memory cell in data address period by display unit, and according to data voltage
To form pixel voltage in display unit；And during Voltage Cortrol according to next stage scanning signal adjusting display unit
Pixel voltage so that pixel voltage be equal to shared electrode offer share voltage.
Therefore, technology according to the present invention content, the embodiment of the present invention is by a kind of image element circuit of offer and its driving side
Method, coupling is produced so as to solving pixel memories (Memory In Pixel, MIP) technology using exchange common voltage AC-VCOM
Close noise (coupling noise) problem so that using MIP technologies product in collocation contact surface plate (Touch Panel,
When TP), the situation for not having TP capability errors occurs.
After with reference to implementation below, the personnel in the technical field of the invention with usual knowledge should easily
Understand the essence spirit and other goals of the invention of the present invention, and the technology used in the present invention means and embodiment.
Description of the drawings
It is above and other objects of the present invention, feature, advantage and embodiment can be become apparent, appended accompanying drawing is said
It is bright as follows：
Figure 1A is to illustrate the circuit box schematic diagram according to a kind of image element circuit of one embodiment of the invention；
Figure 1B is to illustrate the drive waveforms schematic diagram according to a kind of image element circuit of another embodiment of the present invention；
Fig. 1 C are to illustrate the drive waveforms schematic diagram according to a kind of image element circuit of yet another embodiment of the invention；
Fig. 2A is to illustrate the circuit box schematic diagram according to a kind of image element circuit of further embodiment of this invention；
Fig. 2 B are to illustrate the drive waveforms schematic diagram according to a kind of image element circuit of another embodiment of the present invention；
Fig. 3 A are to illustrate the circuit box schematic diagram according to a kind of image element circuit of yet another embodiment of the invention；
Fig. 3 B are to illustrate the drive waveforms schematic diagram according to a kind of image element circuit of further embodiment of this invention；
Fig. 4 is illustrated according to a kind of image element circuit schematic diagram of another embodiment of the present invention；
Fig. 5 A are to illustrate the mode of operation schematic diagram according to a kind of image element circuit of yet another embodiment of the invention；
Fig. 5 B are to illustrate the mode of operation schematic diagram according to a kind of image element circuit of further embodiment of this invention；
Fig. 5 C are to illustrate the mode of operation schematic diagram according to a kind of image element circuit of another embodiment of the present invention；
Fig. 6 is the driving method flow chart for illustrating a kind of image element circuit according to another embodiment of the invention.
According to usual operating type, various features are not drawn to illustrate with element in figure, its illustrate mode be in order to
Specific features and element related to the present invention are presented in optimal manner.Additionally, between different accompanying drawings, with same or analogous
Component symbol is censuring similar elements/components.
Reference
100：Image element circuit 100A～100C：Image element circuit
110：Display unit 112：Pixel electrode
120：Voltage-adjusting unit 122：Writing module
124：Adjusting module 126：Latch module
130：Memory cell 600：Method
610～620：Step
Specific embodiment
In order that the narration of the present invention it is more detailed with it is complete, below for embodiments of the present invention and specific embodiment
Propose illustrative description；But this is not implemented or with the unique forms of the specific embodiment of the invention.Contain in embodiment
The feature of multiple specific embodiments is covered and to construction and the method and step and its order that operate these specific embodiments.So
And, identical or impartial function and sequence of steps also can be realized using other specific embodiments.
Unless this specification is defined otherwise, the implication of science and technology vocabulary used herein is led with technology belonging to the present invention
The personnel with usual knowledge understand and usual same meaning in domain.Additionally, in the case of context of getting along well conflicts, this
Singular noun used by description covers the complex number type of the noun；And also cover the odd number of the noun during plural noun used
Type.
In addition, with regard to coupling used herein, can refer to that two or more elements are mutually directly made entity or are electrically connected with
Touch, or mutually put into effect body or in electrical contact indirectly, be also referred to as two or more element mutual operations or action.
Figure 1A is to illustrate the circuit box schematic diagram according to a kind of image element circuit 100 of one embodiment of the invention.As schemed
Show, image element circuit 100 includes display unit 110, voltage-adjusting unit 120 and memory cell 130.In annexation, show
Show that unit 110 is coupled to shared electrode to receive direct current share voltage Vcom, and be coupled to data wire with receiving data voltage
Vdata.In addition, voltage-adjusting unit 120 is coupled between display unit 110 and memory cell 130.
To illustrate the mode of operation of the image element circuit 100 shown in Figure 1A, please with reference to Figure 1B, it is illustrated according to this
A kind of drive waveforms schematic diagram of the image element circuit 100 of bright another embodiment.During normal displaying mode (Normal Mode)
M1, input enables signal IE and output enables signal OE and is all low level, and voltage-adjusting unit 120 is defeated according to above-mentioned low level
Enter and export to enable signal IE, OE and close, now, image element circuit 100 is turned on and off according to scanning signal Vscan, with
Respective picture is shown accordingly based upon data voltage Vdata.
Then, in the period P1 of buffer mode (Pre-still Mode) period M2, it is high levle that input enables signal IE,
The write paths of voltage-adjusting unit 120 enable signal IE and open according to the input of above-mentioned high levle, now, image element circuit
100 write data voltage Vdata by voltage-adjusting unit 120 to memory cell 130.Subsequently, in static schema (Still
Mode) period M3, it is low level that input enables signal IE, and the write paths of voltage-adjusting unit 120 are according to above-mentioned low level
Input enables signal IE and closes, however, it is high levle that the output during this enables signal OE, therefore, voltage-adjusting unit 120
Outgoing route signal OE is enabled according to the output of above-mentioned high levle and is opened, now, the display unit 110 of image element circuit 100
During static schema in M3 according to the data voltage Vdata stored in memory cell 130 showing respective picture.
As described above, share voltage Vcom that the shared electrode for being couple to display unit 110 is provided is the shared electricity of direct current
Pressure, accordingly, the image element circuit 100 of the embodiment of the present invention is not required to using exchange common voltage AC-Vcom technologies, thus is able to effectively
Ground solves the problems, such as to produce coupled noise (coupling noise) using exchange common voltage AC-Vcom.Consequently, it is possible to adopt
With the product of the image element circuit 100 of the embodiment of the present invention in arrange in pairs or groups contact surface plate (Touch Panel, TP) when, contact surface plate
Function will not be affected.In summary, the image element circuit 100 of the embodiment of the present invention can be efficiently solved using exchange common voltage
The disappearance of AC-Vcom technologies, so that contact surface plate energy normal operation, therefore, using the image element circuit 100 of the embodiment of the present invention
Product can arrange in pairs or groups contact surface plate to be operated with allowing user instinct type in addition to power consumption being greatly reduced, more, and then improve
Using the practicality of the product of the image element circuit 100 of the embodiment of the present invention.
Fig. 1 C are refer to, the detailed drive waveforms of M2 during its buffer mode for further illustrating shown in Figure 1B.It is above-mentioned slow
M2 includes data address period t1 during punch die formula.As illustrated, in data address period t1, scanning signal SRn is high levle,
Data voltage Vdata is write memory cell 130 by display unit 110 according to scanning signal SRn of high levle, and according to data
Voltage Vdata is with the formation pixel voltage Vp in display unit 110.For example, in data address period t1, display unit
110 according to high levles scanning signal SRn will about -5V (volt) data voltage Vdata write memory cell 130, meanwhile,
Display unit 110 also can be according to the data voltage Vdata of above-mentioned about -5V, to be formed on the pixel capacitance in display unit 110
The pixel voltage Vp (refer to the waveform of the pixel voltage Vp of Fig. 1 C) of about -5V.Specifically, the pixel voltage of above-mentioned about -5V
Vp is the pressure reduction between pixel electrode (not shown) and shared electrode, and this pressure reduction (that is, pixel voltage Vp) will cause to show single
The M2 during whole buffer mode of unit 110 shows white picture, and this white picture may be discovered by user, and affects user
Perception.
Therefore, the present invention also proposes the image element circuit 100A shown in Fig. 2A.Compared to the image element circuit 100 shown in Figure 1A,
The voltage-adjusting unit 120 of the image element circuit 100A of Fig. 2A is further coupled to next stage scan line to receive next stage scanning signal
The corresponding operating mode of SRn+1, image element circuit 100A refer to Fig. 2 B, and it is illustrated according to one kind picture of another embodiment of the present invention
The drive waveforms schematic diagram of plain circuit 100A.Please with reference to Fig. 2A and Fig. 2 B, in data address period t1, scanning signal SRn
For high levle, the display unit 110 of image element circuit 100A writes according to scanning signal SRn of high levle to memory cell 130
Data voltage Vdata, meanwhile, display unit 110 also can be according to data voltage Vdata forming pixel in display unit 110
Voltage Vp, as described above, this pixel voltage Vp is between the pixel electrode (not shown) of display unit 110 and shared electrode
Pressure reduction, and this pressure reduction (that is, pixel voltage Vp) will cause display unit 110 to show white picture.
However, because voltage-adjusting unit 120 is further coupled to next stage scan line, therefore, the t2 during Voltage Cortrol, electricity
Pressure adjustment unit 120 be able to according to the next stage scan line of image element circuit 100A provide next stage scanning signal SRn+1 to adjust
The pixel voltage Vp of whole display unit 110 so that the pixel voltage Vp of display unit 110 is equal to the direct current of shared electrode offer
Share voltage Vcom, therefore, pressure reduction is there is no longer between the pixel electrode (not shown) of display unit 110 and shared electrode, and
It is avoided that display unit 110 shows white picture.
Pixel voltage waveform Vp (- 5V) of Fig. 2 B is refer to, in data address period t1, pixel voltage Vp is about -5V (volts
It is special), now, display unit 110 can briefly show white picture in data address period t1 according to the pixel voltage Vp of aforementioned -5V
Face.Pixel voltage waveform Vp (- 5V) of Fig. 2 B, the t2 during Voltage Cortrol are continued referring to, pixel voltage Vp is about 0V (volts
It is special), that is, the pixel voltage Vp of display unit 110 is adjusted to be equal to the direct current share voltage of shared electrode offer
Vcom, therefore, pressure reduction is there is no longer between the pixel electrode (not shown) of display unit 110 and shared electrode, so as to show list
Unit 110 only can briefly show white picture in data address period t1.The persistent period of above-mentioned data address period t1 is extremely short, and
Will not be discovered by user, consequently, it is possible to the image element circuit 100A shown in Fig. 2A is when the perception that can further improve user.
The technological means of the solve problem of the image element circuit 100,100A of the embodiment of the present invention it is stated that as above, are only lifted below
The several embodiments for realizing image element circuit 100,100A of example so that the present invention it is more readily appreciated that but the present invention not with follow-up
Embodiment is limited.
Fig. 3 A are to illustrate the circuit box schematic diagram according to a kind of image element circuit 100B of yet another embodiment of the invention.Compare
In the image element circuit 100A shown in Fig. 2A, the embodiment shown in Fig. 3 A further provides for the internal circuit of voltage-adjusting unit 120
One of implementation.As shown in Figure 3A, voltage-adjusting unit 120 includes writing module 122, adjusting module 124 and breech lock mould
Block 126.In annexation, writing module 122 is coupled to scan line to receive scanning signal SRn, and adjusting module 124 is coupled to
Next stage scan line is receiving next stage scanning signal SRn+1.On the other hand, latch module 126 be coupled to writing module 122 with
Between adjusting module 124, and it is turned on and off to receive and according to signal (IE, OE are referred to as) is enabled.
The corresponding operating mode of the image element circuit 100B shown in Fig. 3 A refer to Fig. 3 B, and it is illustrated according to another reality of the invention
Apply a kind of drive waveforms schematic diagram of image element circuit 100B of example.Please with reference to Fig. 3 A and Fig. 3 B, in operative relationship, write
Scanning signal SRn of the high levle that module 122 is provided in data address period t1 according to scan line and open so that display unit
110 pass through writing module 122 data voltage Vdata is write into memory cell 130.Subsequently, writing module 122 is adjusted in voltage
Scanning signal SRn of the low level that whole period t2 is provided according to scan line and close, therefore, display unit 110 is in Voltage Cortrol
Period t2 no longer writes data voltage Vdata to memory cell 130.Meanwhile, the t2 roots during Voltage Cortrol of adjusting module 124
Open according to next stage scanning signal SRn+1 of next stage scan line offer, low level signal (such as storage assembly Vb) is write
Enter display unit 110 so that pixel voltage Vp is low level voltage.As illustrated, due to the share voltage of shared electrode offer
Vcom t2 during Voltage Cortrol are also low level voltage, therefore, the pixel electrode (not shown) of display unit 110 with it is shared
Pressure reduction is there is no longer between electrode, and is avoided that display unit 110 shows white picture.
Fig. 3 B are refer to, in another embodiment, latch module 126 can be received and according to enabling signal (IE, OE are referred to as)
And be turned on and off.For example, latch module 126 can be in data maintenance period t3 according to enabling signal (IE, OE are referred to as)
Close, to disconnect display unit 110 and memory cell 130 so that memory cell 130 maintains data voltage Vdata.
Fig. 4 is illustrated according to a kind of image element circuit 100C schematic diagrams of another embodiment of the present invention.Compared to Figure 1A, Fig. 2A
And the image element circuit 100,100A, 100B shown in Fig. 3 A, the image element circuit 100C shown in Fig. 4 further provide for image element circuit 100,
One of implementation of internal circuit of 100A, 100B.As shown in figure 4, display unit 110 includes switch T1, switch T2, storage
Electric capacity Cst and liquid crystal capacitance Clc.Furthermore, above-mentioned switch T1 and switch T2 all include first end, control end and second
End, above-mentioned storage capacitors Cst and liquid crystal capacitance Clc are all comprising first end and the second end.In annexation, the first of T1 is switched
End is coupled to data wire with receiving data voltage Vdata, and the control end for switching T1 is coupled to scan line to receive scanning signal
SRn。
On the other hand, the first end for switching T2 is coupled to second end of switch T1, and the control end for switching T2 is defeated to receive
Go out to enable signal OE.Additionally, the first end of storage capacitors Cst is coupled to second end of switch T2, the second end of storage capacitors Cst
Direct current share voltage Vcom is received to be coupled to shared electrode.In addition, the first end of liquid crystal capacitance Clc and the of switch T1
Two ends are coupled to pixel electrode 112, and second end of liquid crystal capacitance Clc receives direct current share voltage to be coupled to shared electrode
Vcom。
In another embodiment, the writing module 122 of voltage-adjusting unit 120 includes write switch T3, this write switch
T3 includes first end, control end and the second end.In annexation, the first end of write switch T3 is coupled to display unit 110
Switch T1 the second end and the first end of switch T2, the control end of write switch T3 is coupled to scan line to receive scanning signal
SRn。
In another embodiment, adjusting module 124 includes adjustment switch T5, adjustment switch T8 and adjustment switch T9.Enter one
For step, adjustment switch T5, adjustment switch T8 and adjustment switch T9 all include first end, control end and the second end.Close in connection
Fasten, the first end of adjustment switch T5 is coupled to the second end, the first end of switch T2 and the write of the switch T1 of display unit 110
The first end of switch T3, the control end of adjustment switch T5 is coupled to next stage scan line to receive next stage scanning signal SRn+1.
Additionally, the first end of adjustment switch T8 is coupled to memory cell to receive storage assembly Vw, the control end of adjustment switch T8
130.In addition, the first end of adjustment switch T9 is coupled to second end of adjustment switch T8, the control end of adjustment switch T9 is coupled to
Memory cell 130, second end of adjustment switch T9 is to receive storage assembly Vb.
In another embodiment, latch module 126 includes latch switch T4, latch switch T6 and latch switch T7.Enter one
For step, above-mentioned latch switch T4, latch switch T6 and latch switch T7 all include first end, control end and the second end.Yu Lian
Connect in relation, the first end of latch switch T4 is coupled to second end of write switch T3, and the control end of latch switch T4 is to connect
Receive input and enable signal IE.In addition, the first end of latch switch T6 is coupled to second end of adjustment switch T5, latch switch T6
Control end enables signal IE to receives input.Additionally, the first end of latch switch T7 is coupled to the switch T1 of display unit 110
The second end, the switch first end of T2, the first end of the first end of write switch T3 and adjustment switch T5, the control of latch switch T7
End processed enables signal OE to receive output.
In another embodiment, memory cell 130 includes switch T10, not gate (NOT gate) IN1 and not gate (NOT
gate)IN2.Furthermore, switch T10 and include first end, control end and the second end, and not gate IN1 and not gate IN2 are all included
Input and outfan.In annexation, the control end for switching T10 enables signal IE to receive output.Additionally, not gate
The input of IN1 is coupled to the first end of switch T10, and the outfan of not gate IN1 is coupled to the control end of adjustment switch T9.Separately
Outward, the input of not gate IN2 is coupled to the outfan of not gate IN1, and the outfan of not gate IN2 is coupled to second end of switch T10.
It should be noted that, in the embodiment shown in fig. 4, switch T1, write switch T3, latch switch T4, latch switch
T6, latch switch T7, adjustment switch T5, adjustment switch T8 and adjustment switch T9 can include N-type MOS field
Effect transistor.Additionally, switch T2 and switch T10 can include P-type mos field-effect transistor.But this
Invention is not limited with the embodiment shown in Fig. 4, and it only illustratively to illustrate one of implementation of the invention, is not taking off
Under the situation of the spirit of the present invention, the modification or modification that carry out to above-described embodiment still fall into the scope of the claims of the present invention
It is interior.
Please with reference to Figure 1A to Fig. 4, because the embodiment of the present invention adopts direct current share voltage Vcom, therefore, above-mentioned reality
Apply each operation signal of example to be slightly different with using exchanging share voltage AC-Vcom, be illustrated below.In an embodiment
In, data voltage Vdata includes single positive level voltage (such as 5V) in t2 during data address period t1 and Voltage Cortrol
And single negative level voltage (such as -5V), storage assembly Vw comprising positive level voltage (such as 5V) and negative level voltage (for example -
5V), storage assembly Vb includes low level voltage (such as 0V).But the present invention is not limited with above-described embodiment, its only to
One of implementation of the present invention is illustratively illustrated, under the situation of the spirit without departing from the present invention, above-described embodiment is entered
Capable modification or modification is still fallen in the scope of the claims of the present invention.
The mode of operation of the image element circuit 100C shown in Fig. 4 will be illustrated below.Fig. 2 is refer to, in normal display
M1 during pattern, input enables signal IE and output enables signal OE and is all low level, latch switch T4, latch switch T6 and door bolt
Lock-switch T7 enables signal IE, OE and closes according to the input and output of low level, and now, image element circuit 100C is according to scanning letter
Number Vscan and be turned on and off, to show respective picture accordingly based upon data voltage Vdata.
Then, please with reference to Fig. 5 A to Fig. 5 C illustrating the mode of operation of the image element circuit 100C shown in Fig. 4.Need explanation
, Fig. 5 A to Fig. 5 C respectively illustrate buffer mode during M2 data address period t1, Voltage Cortrol during t2 and data
The circuit operation view of maintenance period t3.Please with reference to Fig. 3 B and Fig. 5 A, in data address period t1, scanning signal
It is high levle that SRn and input enable signal IE, and switch T1 and switch T3 are all opened according to scanning signal SRn of high levle, opened
Close T4 to enable signal IE according to the input of high levle and open, and switch T10 and closed according to the enabling signal IE of high levle.Together
When, next stage scanning signal SRn+1 and output enable signal OE and are all low level, and switch T5 and switch T7 is respectively according to low level
Next stage scanning signal SRn+1 and output enable signal OE and close.Now, display module 110 switchs T1 and Jing by it
By switch T3 and switch T4 writing data voltage Vdata to memory cell 130.It should be noted that, in display module 110 pairs
During the write data voltage Vdata of memory cell 130, display module 110 is easy to form pixel voltage on its liquid crystal capacitance Clc
Vp。
Then, please with reference to Fig. 3 B and Fig. 5 B, the t2 during Voltage Cortrol, next stage scanning signal SRn+1 and input
Signal IE is enabled for high levle, T5 and switch T6 is switched and is opened according to next stage scanning signal SRn+1 of high levle and input respectively
Opened with signal IE.Meanwhile, scanning signal SRn and output enable signal OE and are all low level, switch T1 and switch T3 all roots
Close according to scanning signal SRn of low level, and switch T7 and signal OE is enabled according to the output of low level and is closed.Now, store up
It is low level voltage (such as 0V) to deposit signal Vb, and this storage assembly Vb is via switch T6, switch T5 with to liquid crystal capacitance Clc writes
Low level voltage (such as 0V).As illustrated, because the direct current common voltage Vcom that common electrode is provided also is low level voltage
(such as 0V), therefore, pressure reduction is there is no longer between the pixel electrode 112 of display unit 110 and shared electrode, and it is avoided that display is single
Unit 110 shows white picture.
Subsequently, Fig. 5 C are refer to, in data maintenance period t3, scanning signal SRn, next stage scanning signal SRn+1 and defeated
Go out to enable signal OE and be all low level, switch T3, switch T5 and switch T7 scanning signal SRn respectively according to low level, next
Level scanning signal SRn+1 and output enable signal OE and close.Now, the connection quilt of display unit 110 and memory cell 130
Disconnect so that memory cell 130 maintains data voltage Vdata.
Fig. 6 is to illustrate the flow chart of driving method 600 according to a kind of image element circuit of another embodiment of the invention.As schemed
Shown, the driving method 600 of image element circuit is comprised the steps of：
Step 610：Data voltage is write into memory cell in data address period by display unit, and according to data electricity
Press to form pixel voltage in display unit；And
Step 620：According to next stage scanning signal to adjust the pixel voltage of display unit during Voltage Cortrol, so as to
Pixel voltage is set to be equal to the share voltage of shared electrode offer.
To make the driving method 600 of image element circuit of the invention it can be readily appreciated that please with reference to Fig. 2A and Fig. 2 B.In step
In 610, data voltage Vdata is write into memory cell 130 in data address period t1 by display unit 110, and according to number
According to voltage Vdata with the formation pixel voltage Vp in display unit 110.In step 620, t2 is according under during Voltage Cortrol
One-level scanning signal SRn+1 to adjust the pixel voltage Vp of display unit 110 so that pixel voltage Vp is equal to shared electrode
Direct current share voltage Vcom of offer.
As described above, direct current common voltage is used in the driving method 600 of the image element circuit of the embodiment of the present invention, according to
This, the driving method 600 of the image element circuit of the present invention does not adopt exchange common voltage AC-Vcom technologies, thus is able to effectively
Solve the problems, such as to produce coupled noise using exchange common voltage AC-Vcom, thus, contact surface plate (Touch Panel, TP)
Function will not be affected.Therefore, being removed using the product of the driving method 600 of the image element circuit of the present invention can be greatly reduced power consumption
Amount is outer, and the TP that can also arrange in pairs or groups improves the image element circuit driving side using the present invention to be operated with allowing user instinct type
The practicality of the product of method 600.
Additionally, refer to Fig. 2 B, although will cause display unit using the driving method 600 of the image element circuit of the present invention
110 briefly show white picture in data address period t1 according to pressure reduction (that is, pixel voltage Vp).However, in Voltage Cortrol
Period t2, the pixel voltage Vp of display unit 110 are adjusted to be equal to direct current share voltage Vcom of shared electrode offer,
Therefore, pressure reduction is there is no longer between the pixel electrode (not shown) and shared electrode of display unit 110, so as to display unit 110
Only can briefly show white picture in data address period t1.The persistent period of above-mentioned data address period t1 is extremely short, without
Discovered by user, consequently, it is possible to work as can further improve user using the driving method 600 of the image element circuit of the present invention
Perception.
In another embodiment, step 610 is refer to, is deposited data voltage write in data address period by display unit
The step of storage unit, includes：The scanning signal provided according to scan line in data address period by display unit is with by data electricity
Pressure write memory cell.Fig. 2A and Fig. 2 B are refer to, in data address period t1, scanning signal SRn that scan line is provided is
High levle, data voltage Vdata is write by display unit 110 according to scanning signal SRn of high levle to memory cell 130.
In another embodiment, step 620 is refer to, it is aobvious to adjust according to next stage scanning signal during Voltage Cortrol
The step of pixel voltage for showing unit, includes：During Voltage Cortrol according to next stage scanning signal with by low level signal write
Display unit, so that pixel voltage is low level voltage.The share voltage that above-mentioned shared electrode is provided is low level voltage.Please
With reference to Fig. 2A and Fig. 2 B, the t2 during Voltage Cortrol, scanning signal SRn+1 that next stage scanning signal is provided is high levle, because
This, voltage-adjusting unit 120 is able to next stage scanning signal SRn+1 according to high levle to write low level signal (such as 0V)
Display unit 110 so that pixel voltage Vp is low level voltage (such as 0V).Due to the t2 during Voltage Cortrol, above-mentioned shared electricity
Share voltage Vcom that pole provides also is low level voltage (such as 0V), therefore, the pixel electrode (not shown) of display unit 110
Pressure reduction is there is no longer between shared electrode, and is avoided that display unit 110 shows white picture.
In another embodiment, pixel circuit drive method 600 is also included：Image element circuit sequentially operates in normal display mould
Formula, buffer mode and static schema, above-mentioned image element circuit is in static schema according to the data voltage in memory cell with aobvious
Show respective picture, during above-mentioned buffer mode is comprising data address period and Voltage Cortrol, data voltage is in data address period
And during Voltage Cortrol it is interior comprising single positive level voltage and single negative level voltage.Refer to Figure 1A and Figure 1B, image element circuit
100 sequentially can operate in normal displaying mode during M3 during M2 and static schema during M1, buffer mode, and in static schema
During period M3, image element circuit 100 is according to the data voltage Vdata stored in memory cell 130 showing respective picture.Please join
T2 during M2 is comprising data address period t1 and Voltage Cortrol during according to Fig. 2 B, above-mentioned buffer mode, data voltage Vdata is in number
Comprising single positive level voltage (such as 5V) and single negative level voltage (example in t2 during according to address period t1 and Voltage Cortrol
Such as -5V).
In another embodiment, the characteristic of the signal that the pixel circuit drive method 600 of the embodiment of the present invention is adopted is such as
It is described afterwards.Fig. 3 B are refer to, scanning signal SRn is high levle signal in data address period t1, and scanning signal SRn is adjusted in voltage
Whole period t2 is low level signal.Additionally, next stage scanning signal SRn+1 is low level signal in data address period t1, under
One-level scanning signal SRn+1 t2 during Voltage Cortrol is high levle signal.
The driving method 600 of image element circuit as above all can be performed by software, hardware and/or firmware.Citing comes
Say, if to perform speed and accuracy as overriding concern, substantially can select based on hardware and/or firmware；If to design bullet
Property be overriding concern, then substantially can select software based on；Or, can simultaneously adopt software, hardware and firmware work compound.Should
Recognize, these examples provided above do not have it is so-called which is better and which is worse point, also and be not used to limit the present invention, be familiar with this
Technical staff was when depending on needing at that time elastic design.
Furthermore, there are usual knowledge personnel when it can be appreciated that in the driving method 600 of image element circuit in art
Each step is named according to its function of performing, merely to allowing the technology of this case to become apparent from understandable, is not limited to this
A little steps.Each step is integrated into into same step or multiple steps are split into, or either step is changed to another step
Perform in rapid, all still fall within embodiments of the present invention.
From the invention described above embodiment, there are following advantages using the present invention.The embodiment of the present invention is by offer
A kind of image element circuit and its driving method, so as to solving pixel memories (Memory In Pixel, MIP) technology using exchange
Common voltage AC-Vcom and produce the problem of coupled noise so that using MIP technologies product in arrange in pairs or groups contact surface plate when, touch
Meeting the function of plate will not be affected.
Although disclosing the specific embodiment of the present invention in embodiment of above, but it is not limited to the present invention,
In the technical field of the invention the personnel with usual knowledge, should in the case of the principle without departing substantially from the present invention is with spirit
Various changes can be carried out to it should be defined as with modification, therefore protection scope of the present invention with appending claims
It is accurate.
Claims (15)
1. a kind of image element circuit, it is characterised in that include：
One display unit, is coupled to a shared electrode and a data wire；
One memory cell a, wherein data voltage is write the memorizer list by the display unit in a data address period
Unit, and according to the data voltage forming a pixel voltage in the display unit；And
One voltage-adjusting unit, is coupled between the display unit and the memory cell and single to control the display
Unit, wherein the voltage-adjusting unit during a Voltage Cortrol according to the next stage scanning signal of the image element circuit adjusting
The pixel voltage of the display unit, so that the direct current that the pixel voltage is equal to the shared electrode offer is total to
Enjoy voltage.
2. image element circuit according to claim 1, it is characterised in that the voltage-adjusting unit is included：
One writing module, is coupled to scan line, wherein said write module in the data address period according to the scanning
Scan signal that line is provided and open so that the display unit by said write module so that the data voltage to be write
Enter the memory cell；And
One adjusting module, is coupled to a next stage scan line, wherein said write module during the Voltage Cortrol according to institute
The scanning signal of scan line offer is provided and is closed, and the adjusting module is according to the next stage scan line is provided
Next stage scanning signal and open, wherein a low level signal is write the display unit by the adjusting module, so that institute
It is a low level voltage to state pixel voltage, wherein the share voltage that the shared electrode is provided is a low level voltage.
3. image element circuit according to claim 2, it is characterised in that the voltage-adjusting unit is also included：
One latch module, to receive one signal is enabled, wherein the latch module is opened in a data maintenance period according to described
Closed with signal, so as to disconnect the display unit and the memory cell, so that the memory cell is maintained
The data voltage.
4. image element circuit according to claim 3, it is characterised in that said write module is included：
One write switch, comprising a first end, a control end and one second end, wherein the first end coupling of said write switch
The display unit is connected to, the control end of said write switch is coupled to the scan line.
5. image element circuit according to claim 4, it is characterised in that the adjusting module is included：
One first adjustment switch, comprising a first end, a control end and one second end, wherein the first adjustment switch is described
First end is coupled to the display unit, and the control end of the first adjustment switch is coupled to the next stage scan line；
One second adjustment switch, comprising a first end, a control end and one second end, wherein the second adjustment switch is described
First end is coupled to the memorizer list to receive one first storage assembly, the control end of the second adjustment switch
Unit；And
One the 3rd adjustment switch, comprising a first end, a control end and one second end, wherein the 3rd adjustment switch is described
First end is coupled to second end of the second adjustment switch, and the control end of the 3rd adjustment switch is coupled to institute
Memory cell is stated, second end of the 3rd adjustment switch is to receive one second storage assembly.
6. image element circuit according to claim 5, it is characterised in that the latch module is included：
One first latch switch, comprising a first end, a control end and one second end, wherein first latch switch is described
First end is coupled to second end of said write switch, and the control end of first latch switch is described to receive
The input for enabling signal enables signal；
One second latch switch, comprising a first end, a control end and one second end, wherein second latch switch is described
First end is coupled to second end of the first adjustment switch, and the control end of second latch switch is to receive
The input enables signal；And
One the 3rd latch switch, comprising a first end, a control end and one second end, wherein the 3rd latch switch is described
First end is coupled to the display unit, and the control end of the 3rd latch switch described enables the one of signal to receive
Output enables signal.
7. image element circuit according to claim 6, it is characterised in that the display unit is included：
One second switch, comprising a first end, a control end and one second end, wherein the first end coupling of the second switch
It is connected to the data wire, the control end of the second switch is coupled to the scan line, described the of the second switch
Two ends are coupled to the first end of said write switch；
One the 3rd switch, comprising a first end, a control end and one second end, wherein the first end coupling of the 3rd switch
Second end of the second switch is connected to, the control end of the 3rd switch is coupled to the 3rd latch switch
The control end, and enable signal to receive the output；
One storage capacitors, comprising a first end and one second end, wherein the first end of the storage capacitors be coupled to it is described
Second end of the 3rd switch, second end of the storage capacitors is to be coupled to the shared electrode；And
One liquid crystal capacitance, comprising a first end and one second end, wherein the first end of the liquid crystal capacitance be coupled to it is described
Second end of second switch and the first end of the 3rd switch, second end of the liquid crystal capacitance is to coupling
It is connected to the shared electrode.
8. the image element circuit according to any one of claim 1 to claim 7, it is characterised in that the image element circuit
A normal displaying mode, a buffer mode and a static schema are sequentially operated in, wherein the image element circuit is in the static mould
According to the data voltage in the memory cell to show respective picture in formula, wherein the buffer mode is comprising described
During data address period and the Voltage Cortrol, the data voltage is in the data address period and the Voltage Cortrol phase
It is interior comprising single positive level voltage and single negative level voltage.
9. the image element circuit according to any one of claim 2 to claim 7, it is characterised in that the scanning signal
It is a high levle signal in the data address period, the scanning signal is low level letter during the Voltage Cortrol
Number, wherein the next stage scanning signal in the data address period be a low level signal, the next stage scanning signal
It is a high levle signal during the Voltage Cortrol.
10. the image element circuit according to any one of claim 5 to claim 7, it is characterised in that first storage
Signal packet is containing positive level voltage and negative level voltage, wherein second storage assembly includes a low level voltage.
11. a kind of pixel circuit drive methods, it is characterised in that the image element circuit includes a display unit and a memorizer list
Unit, the display unit is coupled to a shared electrode, wherein the pixel circuit drive method is included：
One data voltage is write into the memory cell in a data address period by the display unit, and according to the number
According to voltage forming a pixel voltage in the display unit；And
According to a next stage scanning signal to adjust the pixel voltage of the display unit during a Voltage Cortrol, so as to
The pixel voltage is set to be equal to the direct current share voltage that the shared electrode is provided.
12. pixel circuit drive methods according to claim 11, it is characterised in that by the display unit in the number
The step of data voltage is write into the memory cell according to address period includes：
The scan signal provided according to scan line in the data address period by the display unit is with by the data
Voltage writes the memory cell.
13. pixel circuit drive methods according to claim 11, it is characterised in that the basis during the Voltage Cortrol
The step of next stage scanning signal is with the pixel voltage for adjusting the display unit is included：
According to the next stage scanning signal so that a low level signal is write into the display unit during the Voltage Cortrol,
So that the pixel voltage is a low level voltage, wherein the share voltage that the shared electrode is provided is a low level
Voltage.
14. pixel circuit drive methods according to any one of claim 11 to claim 13, it is characterised in that also
Comprising：
The image element circuit sequentially operates in a normal displaying mode, a buffer mode and a static schema, wherein the pixel
Circuit in the static schema according to the data voltage in the memory cell to show respective picture, wherein described
During buffer mode is comprising the data address period and the Voltage Cortrol, the data voltage is in the data address period
And during the Voltage Cortrol it is interior comprising single positive level voltage and single negative level voltage.
15. pixel circuit drive methods according to claim 12 or claim 13, it is characterised in that the scanning letter
Number in the data address period be a high levle signal, the scanning signal during the Voltage Cortrol for a low level believe
Number, wherein the next stage scanning signal in the data address period be a low level signal, the next stage scanning signal
It is a high levle signal during the Voltage Cortrol.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103134042A TWI562124B (en) | 2014-09-30 | 2014-09-30 | Pixel circuit and method for driving the same |
| TW103134042 | 2014-09-30 |
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| Publication Number | Publication Date |
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| CN104409035A CN104409035A (en) | 2015-03-11 |
| CN104409035B true CN104409035B (en) | 2017-04-12 |
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| TW (1) | TWI562124B (en) |
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| TWI613639B (en) | 2016-09-06 | 2018-02-01 | 友達光電股份有限公司 | Switchable pixel circuit and driving method thereof |
| CN110148387A (en) * | 2019-05-21 | 2019-08-20 | 合肥奕斯伟集成电路有限公司 | A kind of the output compensation method and system of driving circuit |
| CN111399677B (en) * | 2020-02-17 | 2023-06-06 | 友达光电（昆山）有限公司 | Touch display device and touch sensing method thereof |
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| JP2005300948A (en) * | 2004-04-13 | 2005-10-27 | Hitachi Displays Ltd | Display device and driving method therefor |
| TWI288389B (en) * | 2005-03-15 | 2007-10-11 | Au Optronics Corp | Method for eliminating residual image and liquid crystal display therefor |
| CN101592833B (en) * | 2008-05-29 | 2010-09-15 | 立景光电股份有限公司 | Pixel circuit and drive method thereof |
| TW201024831A (en) * | 2008-12-16 | 2010-07-01 | Chi Mei Optoelectronics Corp | Display panel, display apparatus and driving method of pixel unit |
| US8823624B2 (en) * | 2010-08-13 | 2014-09-02 | Au Optronics Corporation | Display device having memory in pixels |
| TWM419123U (en) * | 2011-01-18 | 2011-12-21 | Chunghwa Picture Tubes Ltd | Pixel structure with pre-charge function |
| JP5801734B2 (en) * | 2012-03-01 | 2015-10-28 | 株式会社ジャパンディスプレイ | Liquid crystal display device, driving method of liquid crystal display device, and electronic apparatus |
| TWI473066B (en) * | 2012-04-23 | 2015-02-11 | Sitronix Technology Corp | Display panel and its drive circuit |
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| TWI562124B (en) | 2016-12-11 |
| TW201612886A (en) | 2016-04-01 |
| CN104409035A (en) | 2015-03-11 |
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