CN104409035A - Pixel circuit and driving method thereof - Google Patents
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Abstract
The invention provides a pixel circuit and a driving method thereof. The display unit is coupled to the common electrode and the data line. The display unit writes a data voltage into the memory unit in a data writing period and forms a pixel voltage in the display unit according to the data voltage. The voltage adjusting unit is coupled between the display unit and the memory unit and used for controlling the display unit. The voltage adjusting unit adjusts the pixel voltage of the display unit according to the next-stage scanning signal of the pixel circuit during the voltage adjusting period, so that the pixel voltage is equal to the direct current sharing voltage provided by the sharing electrode.
Description
Technical field
The present invention relates to a kind of display device and method, particularly relate to a kind of image element circuit and driving method thereof of display device.
Background technology
Along with the progress of science and technology and people are for the requirement of quality of life, thus Wearable product emerges.Probing into the cause that Wearable product emerges, should be that Wearable product has advantage that is lighter and that be easy to carry about with one compared to portable product (as mobile phone, flat computer).In addition, existing Wearable product is often equipped with condition monitoring mechanism, requires that higher consumer can tend to buy Wearable product to understand the state of a person, and correspondingly adjust its work and rest, to maintaining its personal lifestyle quality for quality of life.
Because Wearable product is better frivolous compared to above-mentioned portable product, correspondingly, the battery capacity of Wearable product is also reduced thereupon, and therefore, Wearable product becomes all the more harsh for the requirement of the power consumption of itself.Accordingly, pixel memories (Memory In Pixel, the MIP) technology that significantly can reduce power consumption more and more comes into one's own.Because traditional MIP circuit framework utilizes these two reverse signals of Vb and Vw to form high and low current potential two kinds of different crampings from common voltage Vcom, the phase place of above-mentioned Vb and Vw signal and the characteristic of the periodic inversion of collocation interchange common voltage AC-Vcom is reversed, to avoid liquid crystal impaired.Therefore, traditional MIP circuit framework is only applicable to exchange common voltage AC-Vcom.
But, learn through experiment, exchange common voltage AC-Vcom and can produce coupled noise (coupling noise) via stray capacitance, this coupled noise can disturb the inductor of contact surface plate, cause contact surface plate capability error, so, adopt causing the product of collocation contact surface plate not to be suitable for tradition the MIP circuit exchanging common voltage AC-Vcom.
As can be seen here, obviously still there is inconvenience and defect, and have much room for improvement in above-mentioned existing mode.In order to solve the problem, association area there's no one who doesn't or isn't seeks solution painstakingly, but does not develop suitable solution yet for a long time.
Summary of the invention
Summary of the invention aims to provide simplification of the present invention summary, possesses basic understanding to make reader to the present invention.This summary of the invention is complete overview of the present invention not, and its purpose is not being pointed out the key/critical element of the embodiment of the present invention or defining scope of the present invention.
One object of content of the present invention is providing a kind of image element circuit and driving method thereof, so as to improving the shortcoming of prior art.
For achieving the above object, a technical approach of content of the present invention is about a kind of image element circuit.Aforementionedly comprise display unit, memory cell and voltage-adjusting unit.Display unit is coupled to shared electrode and data line.Data voltage is write memory cell in data address period by display unit, and according to data voltage to form pixel voltage in display unit.Voltage-adjusting unit to be coupled between display unit and memory cell and in order to control display unit.Voltage-adjusting unit during Voltage Cortrol according to the next stage sweep signal of image element circuit to adjust the pixel voltage of display unit, thus the direct current share voltage making pixel voltage be equal to shared electrode to provide.
For achieving the above object, another technical approach of content of the present invention is about a kind of pixel circuit drive method.Aforementioned image element circuit comprises display unit and memory cell, and display unit is coupled to shared electrode.Aforementioned pixel circuit drive method comprises subsequent step: in data address period, data voltage is write memory cell by display unit, and according to data voltage to form pixel voltage in display unit; And during Voltage Cortrol according to next stage sweep signal to adjust the pixel voltage of display unit, thus the share voltage making pixel voltage be equal to shared electrode to provide.
Therefore, according to technology contents of the present invention, the embodiment of the present invention is by providing a kind of image element circuit and driving method thereof, so as to solving pixel memories (Memory In Pixel, MIP) technology adopts interchange common voltage AC-VCOM and produces the problem of coupled noise (coupling noise), with make the product of employing MIP technology in arrange in pairs or groups contact surface plate (Touch Panel, TP) time, do not have TP capability error situation occur.
After with reference to following embodiment, the personnel in the technical field of the invention with usual knowledge should understand essence spirit of the present invention and other goal of the invention easily, and the technology used in the present invention means and embodiment.
Accompanying drawing explanation
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, appended the description of the drawings is as follows:
Figure 1A is the circuit box schematic diagram of a kind of image element circuit illustrated according to one embodiment of the invention;
Figure 1B is the drive waveforms schematic diagram of a kind of image element circuit illustrated according to another embodiment of the present invention;
Fig. 1 C is the drive waveforms schematic diagram of a kind of image element circuit illustrated according to yet another embodiment of the invention;
Fig. 2 A is the circuit box schematic diagram of a kind of image element circuit illustrated according to further embodiment of this invention;
Fig. 2 B is the drive waveforms schematic diagram of a kind of image element circuit illustrated according to another embodiment of the present invention;
Fig. 3 A is the circuit box schematic diagram of a kind of image element circuit illustrated according to yet another embodiment of the invention;
Fig. 3 B is the drive waveforms schematic diagram of a kind of image element circuit illustrated according to further embodiment of this invention;
Fig. 4 illustrates a kind of image element circuit schematic diagram according to another embodiment of the present invention;
Fig. 5 A is the mode of operation schematic diagram of a kind of image element circuit illustrated according to yet another embodiment of the invention;
Fig. 5 B is the mode of operation schematic diagram of a kind of image element circuit illustrated according to further embodiment of this invention;
Fig. 5 C is the mode of operation schematic diagram of a kind of image element circuit illustrated according to another embodiment of the present invention;
Fig. 6 is the driving method process flow diagram of a kind of image element circuit illustrated according to another embodiment of the present invention.
According to usual operating type, in figure, various feature and element do not illustrate to scale, and it illustrates that mode is to present specific features related to the present invention and element in optimal manner.In addition, between different accompanying drawing, similar elements/components is censured with same or analogous component symbol.
Reference numeral
100: image element circuit 100A ~ 100C: image element circuit
110: display unit 112: pixel electrode
120: voltage-adjusting unit 122: writing module
124: adjusting module 126: breech lock module
130: memory cell 600: method
610 ~ 620: step
Embodiment
In order to make of the present invention describe more detailed and complete, propose illustrative description for embodiments of the present invention and specific embodiment below; But this not implements or uses the unique forms of the specific embodiment of the invention.Cover in embodiment multiple specific embodiment feature and in order to construction and these specific embodiments of operation method step with its sequentially.But, other specific embodiment also can be utilized to realize identical or impartial function and sequence of steps.
Unless this instructions separately has definition, the implication of science and technology vocabulary used herein with have in the technical field of the invention usual knowledge personnel understand with usual meaning identical.In addition, when getting along well context conflict, this instructions singular noun used contains the complex number type of this noun; And during plural noun used, also contain the odd number type of this noun.
In addition, couple about used herein, can refer to that two or more element directly makes entity or in electrical contact mutually, or mutually indirectly put into effect body or in electrical contact, also can refer to two or more element mutual operation or action.
Figure 1A is the circuit box schematic diagram of a kind of image element circuit 100 illustrated according to one embodiment of the invention.As shown in the figure, image element circuit 100 comprises display unit 110, voltage-adjusting unit 120 and memory cell 130.In annexation, display unit 110 is coupled to shared electrode to receive direct current share voltage Vcom, and is coupled to data line to receive data voltage Vdata.In addition, voltage-adjusting unit 120 is coupled between display unit 110 and memory cell 130.
For the mode of operation of the image element circuit 100 shown in Figure 1A is described, please with reference to Figure 1B, it is the drive waveforms schematic diagram of a kind of image element circuit 100 illustrated according to another embodiment of the present invention.In normal displaying mode (Normal Mode) period M1, input is enabled signal IE and output and is enabled signal OE and be all low level, voltage-adjusting unit 120 is enabled signal IE, OE according to the input of above-mentioned low level and output and closes, now, image element circuit 100 is opened according to sweep signal Vscan or is closed, correspondingly to show respective picture according to data voltage Vdata.
Then, in the period P1 of buffer mode (Pre-still Mode) period M2, it is high levle that signal IE is enabled in input, the write paths of voltage-adjusting unit 120 is enabled signal IE according to the input of above-mentioned high levle and opens, now, image element circuit 100 writes data voltage Vdata by voltage-adjusting unit 120 pairs of memory cells 130.Subsequently, in static schema (Still Mode) period M3, it is low level that signal IE is enabled in input, the write paths of voltage-adjusting unit 120 is enabled signal IE according to the input of above-mentioned low level and closes, but, it is high levle that signal OE is enabled in output during this, therefore, the outgoing route of voltage-adjusting unit 120 is enabled signal OE according to the output of above-mentioned high levle and opens, now, the display unit 110 of image element circuit 100 in static schema period M3 according in memory cell 130 store data voltage Vdata to show respective picture.
As mentioned above, the share voltage Vcom that the shared electrode being couple to display unit 110 provides is direct current share voltage, accordingly, the image element circuit 100 of the embodiment of the present invention does not need to adopt and exchanges common voltage AC-Vcom technology, is thus effectively solved to adopt to exchange common voltage AC-Vcom and the problem that produces coupled noise (coupling noise).Thus, adopt the product of the image element circuit 100 of the embodiment of the present invention when collocation contact surface plate (Touch Panel, TP), the function of contact surface plate can not be affected.Sum up and discuss, the image element circuit 100 of the embodiment of the present invention can solve the disappearance adopting and exchange common voltage AC-Vcom technology effectively, to make the normal operation of contact surface plate energy, therefore, adopt the product of the image element circuit 100 of the embodiment of the present invention except can significantly reduce except power consumption, more can arrange in pairs or groups contact surface plate to operate with allowing user's instinct type, and then raising adopts the practicality of the product of the image element circuit 100 of the embodiment of the present invention.
Please refer to Fig. 1 C, it illustrates the detailed drive waveforms of the buffer mode period M2 shown in Figure 1B further.Above-mentioned buffer mode period M2 comprises data address period t1.As shown in the figure, in data address period t1, sweep signal SRn is high levle, and data voltage Vdata is write memory cell 130 according to the sweep signal SRn of high levle by display unit 110, and according to data voltage Vdata to form pixel voltage Vp in display unit 110.For example, in data address period t1, the data voltage Vdata of about-5V (volt) is write memory cell 130 according to the sweep signal SRn of high levle by display unit 110, simultaneously, display unit 110 also can according to the data voltage Vdata of above-mentioned about-5V, the pixel capacitance in display unit 110 to be formed the pixel voltage Vp (please refer to the waveform of the pixel voltage Vp of Fig. 1 C) of about-5V.Specifically, the pixel voltage Vp of above-mentioned about-5V is the pressure reduction between pixel electrode (not shown) and shared electrode, this pressure reduction (that is pixel voltage Vp) will make display unit 110 show white picture in whole buffer mode period M2, this white picture may be discovered by user, and affects the perception of user.
Therefore, the present invention also proposes the image element circuit 100A shown in Fig. 2 A.Compared to the image element circuit 100 shown in Figure 1A, the voltage-adjusting unit 120 of the image element circuit 100A of Fig. 2 A is also coupled to next stage sweep trace to receive next stage sweep signal SRn+1, the corresponding operating mode of image element circuit 100A please refer to Fig. 2 B, and it illustrates the drive waveforms schematic diagram of a kind of image element circuit 100A according to another embodiment of the present invention.Please with reference to Fig. 2 A and Fig. 2 B, in data address period t1, sweep signal SRn is high levle, the display unit 110 of image element circuit 100A writes data voltage Vdata according to the sweep signal SRn of high levle to memory cell 130, simultaneously, display unit 110 also can according to data voltage Vdata to form pixel voltage Vp in display unit 110, as mentioned above, this pixel voltage Vp is the pressure reduction between the pixel electrode (not shown) of display unit 110 and shared electrode, and this pressure reduction (that is pixel voltage Vp) will make display unit 110 show white picture.
But, because voltage-adjusting unit 120 is also coupled to next stage sweep trace, therefore, at Voltage Cortrol period t2, the next stage sweep signal SRn+1 that voltage-adjusting unit 120 is able to provide according to the next stage sweep trace of image element circuit 100A is to adjust the pixel voltage Vp of display unit 110, the direct current share voltage Vcom making the pixel voltage Vp of display unit 110 be equal to shared electrode to provide, therefore, no longer include pressure reduction between the pixel electrode (not shown) of display unit 110 and shared electrode, and display unit 110 can be avoided to show white picture.
Please refer to pixel voltage waveform Vp (-5V) of Fig. 2 B, in data address period t1, pixel voltage Vp is about-5V (volt), and now, display unit 110 can show white picture according to the pixel voltage Vp of aforementioned-5V momently in data address period t1.Continue referring to pixel voltage waveform Vp (-5V) of Fig. 2 B, in Voltage Cortrol period t2, pixel voltage Vp is about 0V (volt), that is the pixel voltage Vp of display unit 110 has been adjusted to the direct current share voltage Vcom being equal to shared electrode and providing, therefore, no longer include pressure reduction between the pixel electrode (not shown) of display unit 110 and shared electrode, thus display unit 110 only can show white picture at data address period t1 momently.The duration of above-mentioned data address period t1 is extremely short, and can not be discovered by user, and thus, the image element circuit 100A shown in Fig. 2 A is when the perception that can improve user further.
The image element circuit 100 of the embodiment of the present invention, the technological means of dealing with problems of 100A have illustrated as above, several embodiment realizing image element circuit 100,100A of only illustrating below, be easier to understand, but the present invention are not limited with subsequent embodiment to make the present invention.
Fig. 3 A is the circuit box schematic diagram of a kind of image element circuit 100B illustrated according to yet another embodiment of the invention.Compared to the image element circuit 100A shown in Fig. 2 A, the embodiment shown in Fig. 3 A provides one of implementation of the internal circuit of voltage-adjusting unit 120 further.As shown in Figure 3A, voltage-adjusting unit 120 comprises writing module 122, adjusting module 124 and breech lock module 126.In annexation, writing module 122 is coupled to sweep trace to accept sweep signal SRn, and adjusting module 124 is coupled to next stage sweep trace to receive next stage sweep signal SRn+1.On the other hand, breech lock module 126 is coupled between writing module 122 and adjusting module 124, and in order to receive and to open according to enabling signal (IE, OE are referred to as) or close.
The corresponding operating mode of the image element circuit 100B shown in Fig. 3 A please refer to Fig. 3 B, and it illustrates the drive waveforms schematic diagram of a kind of image element circuit 100B according to further embodiment of this invention.Please with reference to Fig. 3 A and Fig. 3 B, in operative relationship, the sweep signal SRn of the high levle that writing module 122 provides according to sweep trace in data address period t1 and opening, makes display unit 110 by writing module 122 so that data voltage Vdata is write memory cell 130.Subsequently, the sweep signal SRn of the low level that writing module 122 provides according to sweep trace in Voltage Cortrol period t2 and closing, therefore, display unit 110 no longer writes data voltage Vdata to memory cell 130 in Voltage Cortrol period t2.Simultaneously, the next stage sweep signal SRn+1 that adjusting module 124 provides in Voltage Cortrol period t2 according to next stage sweep trace and opening, so that low level signal (as storage assembly Vb) is write display unit 110, pixel voltage Vp is made to be low level voltage.As shown in the figure, the share voltage Vcom provided due to shared electrode in Voltage Cortrol period t2 be also low level voltage, therefore, no longer include pressure reduction between the pixel electrode (not shown) of display unit 110 and shared electrode, and display unit 110 can be avoided to show white picture.
Please refer to Fig. 3 B, in another embodiment, breech lock module 126 can receive and open according to enabling signal (IE, OE are referred to as) or close.For example, breech lock module 126 can be closed in data maintenance period t3 according to enabling signal (IE, OE are referred to as), to disconnect display unit 110 and memory cell 130, makes memory cell 130 maintain data voltage Vdata.
Fig. 4 illustrates a kind of image element circuit 100C schematic diagram according to another embodiment of the present invention.Compared to the image element circuit 100 shown in Figure 1A, Fig. 2 A and Fig. 3 A, 100A, 100B, the image element circuit 100C shown in Fig. 4 provides one of the implementation of internal circuit of image element circuit 100,100A, 100B further.As shown in Figure 4, display unit 110 comprises switch T1, switch T2, storage capacitors Cst and liquid crystal capacitance Clc.Furthermore, above-mentioned switch T1 and switch T2 all comprises first end, control end and the second end, and above-mentioned storage capacitors Cst and liquid crystal capacitance Clc all comprises first end and the second end.In annexation, the first end of switch T1 is coupled to data line to receive data voltage Vdata, and the control end of switch T1 is coupled to sweep trace to receive sweep signal SRn.
On the other hand, the first end of switch T2 is coupled to second end of switch T1, and the control end of switch T2 enables signal OE in order to receive output.In addition, the first end of storage capacitors Cst is coupled to second end of switch T2, and second end of storage capacitors Cst is in order to be coupled to shared electrode to receive direct current share voltage Vcom.In addition, the first end of liquid crystal capacitance Clc and second end of switch T1 are coupled to pixel electrode 112, and second end of liquid crystal capacitance Clc is in order to be coupled to shared electrode to receive direct current share voltage Vcom.
In another embodiment, the writing module 122 of voltage-adjusting unit 120 comprises write switch T3, and this write switch T3 comprises first end, control end and the second end.In annexation, the first end of write switch T3 is coupled to second end of the switch T1 of display unit 110 and the first end of switch T2, and the control end of write switch T3 is coupled to sweep trace to receive sweep signal SRn.
In an embodiment again, adjusting module 124 comprises adjustment switch T5, adjustment switch T8 and adjustment switch T9.Furthermore, adjust switch T5, adjustment switch T8 and adjust switch T9 and all comprise first end, control end and the second end.In annexation, the first end of adjustment switch T5 is coupled to the first end of second end of the switch T1 of display unit 110, the first end of switch T2 and write switch T3, and the control end of adjustment switch T5 is coupled to next stage sweep trace to receive next stage sweep signal SRn+1.In addition, the first end of adjustment switch T8 is in order to receive storage assembly Vw, and the control end of adjustment switch T8 is coupled to memory cell 130.In addition, the first end of adjustment switch T9 is coupled to second end of adjustment switch T8, and the control end of adjustment switch T9 is coupled to memory cell 130, and second end of adjustment switch T9 is in order to receive storage assembly Vb.
In another embodiment, breech lock module 126 comprises latch switch T4, latch switch T6 and latch switch T7.Furthermore, above-mentioned latch switch T4, latch switch T6 and latch switch T7 all comprise first end, control end and the second end.In annexation, the first end of latch switch T4 is coupled to second end of write switch T3, and the control end of latch switch T4 enables signal IE in order to receive input.In addition, the first end of latch switch T6 is coupled to second end of adjustment switch T5, and the control end of latch switch T6 enables signal IE in order to receive input.In addition, the first end of latch switch T7 is coupled to the first end of second end of the switch T1 of display unit 110, the first end of switch T2, the first end of write switch T3 and adjustment switch T5, and the control end of latch switch T7 enables signal OE in order to receive output.
In another embodiment, memory cell 130 comprises switch T10, not gate (NOT gate) IN1 and not gate (NOT gate) IN2.Furthermore, switch T10 comprises first end, control end and the second end, and not gate IN1 and not gate IN2 all comprises input end and output terminal.In annexation, the control end of switch T10 enables signal IE in order to receive output.In addition, the input end of not gate IN1 is coupled to the first end of switch T10, and the output terminal of not gate IN1 is coupled to the control end of adjustment switch T9.In addition, the input end of not gate IN2 is coupled to the output terminal of not gate IN1, and the output terminal of not gate IN2 is coupled to second end of switch T10.
It should be noted that, in the embodiment shown in fig. 4, switch T1, write switch T3, latch switch T4, latch switch T6, latch switch T7, adjustment switch T5, adjustment switch T8 and adjustment switch T9 can comprise N-type mos field effect transistor.In addition, switch T2 and switch T10 can comprise P-type mos field effect transistor.But the present invention is not limited with the embodiment shown in Fig. 4, it is only in order to illustrate one of implementation of the present invention illustratively, under the situation not departing from spirit of the present invention, the amendment carry out above-described embodiment or modification still fall in the scope of the claims of the present invention.
Please with reference to Figure 1A to Fig. 4, due to embodiment of the present invention employing direct current share voltage Vcom, therefore, it is slightly different that each operation signal of above-described embodiment and employing exchange share voltage AC-Vcom, illustrates as follows.In one embodiment, data voltage Vdata comprises the accurate voltage of single normotopia (such as 5V) and the accurate voltage in single negative position (such as-5V) in data address period t1 and Voltage Cortrol period t2, storage assembly Vw comprises the accurate voltage of normotopia (such as 5V) and negative position accurate voltage (such as-5V), and storage assembly Vb comprises low level voltage (such as 0V).But the present invention is not limited with above-described embodiment, it is only in order to illustrate one of implementation of the present invention illustratively, and under the situation not departing from spirit of the present invention, the amendment carry out above-described embodiment or modification still fall in the scope of the claims of the present invention.
Be described to the mode of operation of the image element circuit 100C shown in Fig. 4 below.Please refer to Fig. 2, in normal displaying mode period M1, input is enabled signal IE and output and is enabled signal OE and be all low level, latch switch T4, latch switch T6 and latch switch T7 enable signal IE, OE according to the input of low level and output and close, now, image element circuit 100C opens or closes according to sweep signal Vscan, correspondingly to show respective picture according to data voltage Vdata.
Then, please with reference to Fig. 5 A to Fig. 5 C with the mode of operation of the image element circuit 100C shown in key diagram 4.It should be noted that, Fig. 5 A to Fig. 5 C respectively illustrates data address period t1, the Voltage Cortrol period t2 of buffer mode period M2 and the circuit operation view of data maintenance period t3.Please with reference to Fig. 3 B and Fig. 5 A, in data address period t1, it is high levle that signal IE is enabled in sweep signal SRn and input, switch T1 and switch T3 all opens according to the sweep signal SRn of high levle, switch T4 enables signal IE according to the input of high levle and opens, and switch T10 closes according to the enabling signal IE of high levle.Meanwhile, next stage sweep signal SRn+1 and output are enabled signal OE and are all low level, and switch T5 and switch T7 enables signal OE according to the next stage sweep signal SRn+1 of low level and output and closes respectively.Now, display module 110 is by its switch T1 and via switch T3 and switch T4 to write data voltage Vdata to memory cell 130.It should be noted that, when display module 110 pairs of memory cells 130 write data voltage Vdata, display module 110 is easy to its liquid crystal capacitance Clc forms pixel voltage Vp.
Then, please with reference to Fig. 3 B and Fig. 5 B, in Voltage Cortrol period t2, it is high levle that signal IE is enabled in next stage sweep signal SRn+1 and input, and switch T5 and switch T6 enables signal IE according to the next stage sweep signal SRn+1 of high levle and input and opens respectively.Meanwhile, sweep signal SRn and output are enabled signal OE and are all low level, and switch T1 and switch T3 all closes according to the sweep signal SRn of low level, and switch T7 enables signal OE according to the output of low level and closes.Now, storage assembly Vb is low level voltage (such as 0V), this storage assembly Vb via switch T6, switch T5 to write low level voltage (such as 0V) to liquid crystal capacitance Clc.As shown in the figure, the direct current common voltage Vcom provided due to common electrode is also low level voltage (such as 0V), therefore, no longer include pressure reduction between the pixel electrode 112 of display unit 110 and shared electrode, and display unit 110 can be avoided to show white picture.
Subsequently, please refer to Fig. 5 C, in data maintenance period t3, sweep signal SRn, next stage sweep signal SRn+1 and output are enabled signal OE and are all low level, and switch T3, switch T5 and switch T7 enable signal OE according to sweep signal SRn, the next stage sweep signal SRn+1 of low level and output and close respectively.Now, display unit 110 is disconnected with the connection of memory cell 130, makes memory cell 130 maintain data voltage Vdata.
Fig. 6 is driving method 600 process flow diagram of a kind of image element circuit illustrated according to another embodiment of the present invention.As shown in the figure, the driving method 600 of image element circuit comprises following steps:
Step 610: in data address period, data voltage is write memory cell by display unit, and according to data voltage to form pixel voltage in display unit; And
Step 620: during Voltage Cortrol according to next stage sweep signal to adjust the pixel voltage of display unit, thus the share voltage making pixel voltage be equal to shared electrode to provide.
For making driving method 600 easy to understand of image element circuit of the present invention, please with reference to Fig. 2 A and Fig. 2 B.In step 610, in data address period t1, data voltage Vdata is write memory cell 130 by display unit 110, and according to data voltage Vdata to form pixel voltage Vp in display unit 110.In step 620, in Voltage Cortrol period t2 according to next stage sweep signal SRn+1 to adjust the pixel voltage Vp of display unit 110, thus the direct current share voltage Vcom making pixel voltage Vp be equal to shared electrode to provide.
As mentioned above, what adopt in the driving method 600 of the image element circuit of the embodiment of the present invention is direct current common voltage, accordingly, the driving method 600 of image element circuit of the present invention does not adopt and exchanges common voltage AC-Vcom technology, thus effectively solved to adopt and exchange common voltage AC-Vcom and produce the problem of coupled noise, so, the function of contact surface plate (Touch Panel, TP) can not be affected.Therefore, adopt the product of the driving method 600 of image element circuit of the present invention except can significantly reduce except power consumption, the TP that also can arrange in pairs or groups to operate with allowing user's instinct type, and then improves the practicality of the product adopting pixel circuit drive method 600 of the present invention.
In addition, please refer to Fig. 2 B, although adopt the driving method 600 of image element circuit of the present invention that display unit 110 will be made to show white picture in data address period t1 momently according to pressure reduction (that is pixel voltage Vp).But, in Voltage Cortrol period t2, the pixel voltage Vp of display unit 110 has been adjusted to the direct current share voltage Vcom being equal to shared electrode and providing, therefore, no longer include pressure reduction between the pixel electrode (not shown) of display unit 110 and shared electrode, thus display unit 110 only can show white picture at data address period t1 momently.The duration of above-mentioned data address period t1 is extremely short, and can not be discovered by user, thus, adopts the driving method 600 of image element circuit of the present invention when the perception that can improve user further.
In another embodiment, please refer to step 610, comprised in the step that data voltage to be write memory cell by data address period by display unit: the sweep signal provided according to sweep trace in data address period by display unit is to write memory cell by data voltage.Please refer to Fig. 2 A and Fig. 2 B, be high levle in data address period t1, the sweep signal SRn that sweep trace provides, according to the sweep signal SRn of high levle, data voltage Vdata write to memory cell 130 by display unit 110.
In an embodiment again, please refer to step 620, comprise with the step of the pixel voltage adjusting display unit according to next stage sweep signal during Voltage Cortrol: during Voltage Cortrol according to next stage sweep signal with by low level signal write display unit, thus make pixel voltage be low level voltage.The share voltage that above-mentioned shared electrode provides is low level voltage.Please refer to Fig. 2 A and Fig. 2 B, in Voltage Cortrol period t2, the sweep signal SRn+1 that next stage sweep signal provides is high levle, therefore, voltage-adjusting unit 120 to be able to according to the next stage sweep signal SRn+1 of high levle, so that low level signal (as 0V) is write display unit 110, make pixel voltage Vp be low level voltage (as 0V).Due at Voltage Cortrol period t2, the share voltage Vcom that above-mentioned shared electrode provides also is low level voltage (as 0V), therefore, no longer include pressure reduction between the pixel electrode (not shown) of display unit 110 and shared electrode, and display unit 110 can be avoided to show white picture.
In another embodiment, pixel circuit drive method 600 also comprises: image element circuit sequentially operates in normal displaying mode, buffer mode and static schema, above-mentioned image element circuit in static schema according to the data voltage in memory cell to show respective picture, during above-mentioned buffer mode comprises data address period and Voltage Cortrol, data voltage during data address period and Voltage Cortrol in comprise the accurate voltage of the accurate voltage of single normotopia and single negative position.Please refer to Figure 1A and Figure 1B, image element circuit 100 sequentially can operate in normal displaying mode period M1, buffer mode period M2 and static schema period M3, and when static schema period M3, image element circuit 100 according to the data voltage Vdata stored in memory cell 130 to show respective picture.Please refer to Fig. 2 B, above-mentioned buffer mode period M2 comprises data address period t1 and Voltage Cortrol period t2, data voltage Vdata comprise the accurate voltage of single normotopia (such as 5V) and the accurate voltage in single negative position (such as-5V) in data address period t1 and Voltage Cortrol period t2.
In another embodiment, the characteristic of signal that adopts of the pixel circuit drive method 600 of the embodiment of the present invention as described later.Please refer to Fig. 3 B, sweep signal SRn is high levle signal in data address period t1, sweep signal SRn in Voltage Cortrol period t2 be low level signal.In addition, next stage sweep signal SRn+1 is low level signal in data address period t1, next stage sweep signal SRn+1 in Voltage Cortrol period t2 be high levle signal.
The driving method 600 of image element circuit as above all can be performed by software, hardware and/or firmware.For example, if with execution speed and accuracy for overriding concern, then hardware and/or firmware substantially can be selected to be main; If take design flexibility as overriding concern, then software substantially can be selected to be main; Or, software, hardware and firmware work compound can be adopted simultaneously.Should be appreciated that, above these lifted examples are not so-called, and which is better and which is worse point, also and be not used to limit the present invention, is familiar with technique personnel and works as depending on needing Flexible Design at that time.
Moreover have usual knowledge personnel in art when understanding, the function that each step in the driving method 600 of image element circuit performs according to it is named, and is only to allow the technology of this case more become apparent, and is not used to limit those steps.Each step be integrated into same step or be split into multiple step, or arbitrary step is changed in another step performing, all still being belonged to embodiments of the present invention.
From the invention described above embodiment, application the present invention has following advantages.The embodiment of the present invention is by providing a kind of image element circuit and driving method thereof, so as to solving pixel memories (Memory In Pixel, MIP) technology adopts interchange common voltage AC-Vcom and produces the problem of coupled noise, with make the product of employing MIP technology in arrange in pairs or groups contact surface plate time, the function of contact surface plate can not be affected.
Although disclose specific embodiments of the invention in above embodiment; but itself and be not used to limit the present invention; there are the personnel of usual knowledge in the technical field of the invention when not deviating from principle of the present invention and spirit; should carry out various change and modification to it, therefore protection scope of the present invention should define with appending claims and be as the criterion.
Claims (15)
1. an image element circuit, is characterized in that, comprises:
One display unit, is coupled to a shared electrode and a data line;
One memory cell, a data voltage is write described memory cell in a data address period by wherein said display unit, and according to described data voltage to form a pixel voltage in described display unit; And
One voltage-adjusting unit, to be coupled between described display unit and described memory cell and in order to control described display unit, wherein said voltage-adjusting unit during a Voltage Cortrol according to the next stage sweep signal of described image element circuit to adjust the described pixel voltage of described display unit, thus the direct current share voltage making described pixel voltage be equal to described shared electrode to provide.
2. image element circuit according to claim 1, is characterized in that, described voltage-adjusting unit comprises:
One writing module, be coupled to scan line, the one scan signal that wherein said writing module provides in described data address period according to described sweep trace and opening, thus make described display unit by said write module described data voltage to be write described memory cell; And
One adjusting module, be coupled to a next stage sweep trace, the described sweep signal that wherein said writing module provides according to described sweep trace during described Voltage Cortrol and closing, and the described next stage sweep signal that provides according to described next stage sweep trace of described adjusting module and opening, one low level signal is write described display unit by wherein said adjusting module, thus making described pixel voltage be a low level voltage, the described share voltage that wherein said shared electrode provides is a low level voltage.
3. image element circuit according to claim 2, is characterized in that, described voltage-adjusting unit also comprises:
One breech lock module, signal is enabled in order to receive one, wherein said breech lock module in a data maintenance period according to described in enable signal and close, thus to disconnect described display unit and described memory cell, thus make described memory cell maintain described data voltage.
4. image element circuit according to claim 3, is characterized in that, said write module comprises:
One write switch, comprise a first end, a control end and one second end, the described first end of wherein said write switch is coupled to described display unit, and the described control end of said write switch is coupled to described sweep trace.
5. image element circuit according to claim 4, is characterized in that, described adjusting module comprises:
One first adjustment switch, comprises a first end, a control end and one second end, and the described first end of wherein said first adjustment switch is coupled to described display unit, and the described control end of described first adjustment switch is coupled to described next stage sweep trace;
One second adjustment switch, comprises a first end, a control end and one second end, and the described first end of wherein said second adjustment switch is in order to receive one first storage assembly, and the described control end of described second adjustment switch is coupled to described memory cell; And
One the 3rd adjustment switch, comprise a first end, a control end and one second end, the described first end of wherein said 3rd adjustment switch is coupled to described second end of described second adjustment switch, the described control end of described 3rd adjustment switch is coupled to described memory cell, and described second end of described 3rd adjustment switch is in order to receive one second storage assembly.
6. image element circuit according to claim 5, is characterized in that, described breech lock module comprises:
One first latch switch, comprise a first end, a control end and one second end, the described first end of wherein said first latch switch is coupled to described second end of said write switch, and the described control end of described first latch switch enables signal in order to an input of enabling signal described in receiving;
One second latch switch, comprise a first end, a control end and one second end, the described first end of wherein said second latch switch is coupled to described second end of described first adjustment switch, and the described control end of described second latch switch enables signal in order to receive described input; And
One the 3rd latch switch, comprise a first end, a control end and one second end, the described first end of wherein said 3rd latch switch is coupled to described display unit, and the described control end of described 3rd latch switch enables signal in order to an output of enabling signal described in receiving.
7. image element circuit according to claim 6, is characterized in that, described display unit comprises:
One second switch, comprise a first end, a control end and one second end, the described first end of wherein said second switch is coupled to described data line, the described control end of described second switch is coupled to described sweep trace, and described second end of described second switch is coupled to the described first end of said write switch;
One the 3rd switch, comprise a first end, a control end and one second end, the described first end of wherein said 3rd switch is coupled to described second end of described second switch, the described control end of described 3rd switch is coupled to the described control end of described 3rd latch switch, and enables signal in order to receive described output;
One storage capacitors, comprises a first end and one second end, and the described first end of wherein said storage capacitors is coupled to described second end of described 3rd switch, and described second end of described storage capacitors is in order to be coupled to described shared electrode; And
One liquid crystal capacitance, comprise a first end and one second end, the described first end of wherein said liquid crystal capacitance is coupled to described second end of described second switch and the described first end of described 3rd switch, and described second end of described liquid crystal capacitance is in order to be coupled to described shared electrode.
8. the image element circuit according to any one of claim 1 to claim 7, it is characterized in that, described image element circuit sequentially operates in a normal displaying mode, a buffer mode and a static schema, wherein said image element circuit in described static schema according to the described data voltage in described memory cell to show respective picture, during wherein said buffer mode comprises described data address period and described Voltage Cortrol, described data voltage during described data address period and described Voltage Cortrol in comprise the accurate voltage of the accurate voltage of single normotopia and single negative position.
9. the image element circuit according to any one of claim 2 to claim 7, it is characterized in that, described sweep signal is a high levle signal in described data address period, described sweep signal is a low level signal during described Voltage Cortrol, wherein said next stage sweep signal is a low level signal in described data address period, and described next stage sweep signal is a high levle signal during described Voltage Cortrol.
10. the image element circuit according to any one of claim 5 to claim 7, is characterized in that, described first storage assembly comprises the accurate voltage of the accurate voltage of normotopia and negative position, and wherein said second storage assembly comprises a low level voltage.
11. 1 kinds of pixel circuit drive methods, is characterized in that, described image element circuit comprises a display unit and a memory cell, and described display unit is coupled to a shared electrode, and wherein said pixel circuit drive method comprises:
In a data address period, one data voltage is write described memory cell by described display unit, and according to described data voltage to form a pixel voltage in described display unit; And
During a Voltage Cortrol according to a next stage sweep signal to adjust the described pixel voltage of described display unit, thus the direct current share voltage making described pixel voltage be equal to described shared electrode to provide.
12. pixel circuit drive methods according to claim 11, is characterized in that, the step that described data voltage writes described memory cell are comprised in described data address period by described display unit:
The one scan signal provided in described data address period according to scan line by described display unit is to write described memory cell by described data voltage.
13. pixel circuit drive methods according to claim 11, is characterized in that, comprise during described Voltage Cortrol according to described next stage sweep signal with the step of the described pixel voltage adjusting described display unit:
During described Voltage Cortrol according to described next stage sweep signal so that a low level signal is write described display unit, thus make described pixel voltage be a low level voltage, the described share voltage that wherein said shared electrode provides is a low level voltage.
14., according to claim 11 to the pixel circuit drive method according to any one of claim 13, is characterized in that, also comprise:
Described image element circuit sequentially operates in a normal displaying mode, a buffer mode and a static schema, wherein said image element circuit in described static schema according to the described data voltage in described memory cell to show respective picture, during wherein said buffer mode comprises described data address period and described Voltage Cortrol, described data voltage during described data address period and described Voltage Cortrol in comprise the accurate voltage of the accurate voltage of single normotopia and single negative position.
15. according to claim 12 or pixel circuit drive method according to claim 13, it is characterized in that, described sweep signal is a high levle signal in described data address period, described sweep signal is a low level signal during described Voltage Cortrol, wherein said next stage sweep signal is a low level signal in described data address period, and described next stage sweep signal is a high levle signal during described Voltage Cortrol.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| TW103134042A TWI562124B (en) | 2014-09-30 | 2014-09-30 | Pixel circuit and method for driving the same |
| TW103134042 | 2014-09-30 |
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| CN104409035A true CN104409035A (en) | 2015-03-11 |
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Also Published As
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| TW201612886A (en) | 2016-04-01 |
| CN104409035B (en) | 2017-04-12 |
| TWI562124B (en) | 2016-12-11 |
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