CN104392058A - Epitaxial double-channel isolation diode drive array modeling method and simulation model - Google Patents

Abstract

The invention provides an epitaxial double-channel isolation diode drive array modeling method and a simulation model. The method includes: extracting single device size, scale and process model parameters and device model parameters of a diode array device under benchmark process conditions, and establishing a process model and a device model; verifying the obtained process model parameters and device model parameters according to parameter test results of experiment flow sheets; creating dependency relationship between electrical properties of diodes and the device size, process model parameters and device model parameters according to the verified process model parameters and device model parameters; simulating the relation among internal forward drive current of a diode array, cross current and substrate leakage current by utilizing a parasitic triode network model, and then verifying process optimization conditions of the diode array device. According to performance requirements of the next-generation diode drive array device, the device process conditions and device parameters can be determined conveniently and quickly, and device performances are predicated.

Description

Extension double channel isolating diode drives array modeling methods and realistic model

Technical field

The present invention relates to diode array device modeling method and emulation technology, particularly relate to a kind of different size, scale diode array device for driving modeling method and the realistic model of phase transition storage.

Background technology

Phase transition storage (PCRAM) is based on late 1960s (S.R.Ovshinsky, Phys.Rev.Lett., 21,1968, p1450) to the beginning of the seventies (people such as J.Feinleib, Appl.Phys.Lett., 18,1971, p254) the novel Ultrahigh of reversible transition can be there is in a kind of chalcogenide compound semiconductive thin film of being proposed by Ovshinsky under the effect of electricity, heat and light.Phase transition storage is international study hotspot as high-density memory technology, and 1D1R (1 diode and 1 reversible transition resistance) is the optimal path realizing high-density city array.Forward drive ability is strong, leakage current and little, the highdensity diode array of crossfire are the prerequisites realizing mass memory.Samsung company (people such as M.J.Kang delivers in IEDM meeting) develops 4F under 20nm technology node ²pCRAM array device, phase-change material is defined in narrow and small region, and be 30nm at the height of the word-line direction phase-change material along array, width is only 7.5nm; Length along bit line direction phase-change material is 22nm.But, it drives diode array to adopt selective epitaxial technology, manufacturing cost is very high, and this preparation technology completes after CMOS technology, its inevitable heat treatment process can cause the electric property of 40nm cmos device to drift about, reduce the product yield of 40nm CMOS logical circuit, this technology is not suitable for the application design of built-in PC RAM chip under 40nm standard CMOS process.2010, Chinese Academy of Sciences's micro-system and infotech research institute have developed device architecture and preparation technology's (Chinese patent of the epitaxial diode array of isolating based on double channel, the preparation method of the epitaxial diode array of dual shallow groove isolation, application number: 201010289920.1), this technology adopts the CMOS manufacturing process of main flow, substrate is formed heavily doped first conductivity type regions, adopt silicon epitaxy technology growth epitaxial loayer, then by etch process formed deep trench isolation between diode array wordline and perpendicular to the shallow channel in deep trench direction formed bit line spacer from, the insulation course of high-aspect-ratio is filled in deep trench and shallow channel respectively.Finally, through ion implantation technology, the active region surrounded in dark, shallow trench isolation forms the second conductivity type regions, forms diode array.

Along with the development of semiconductor photolithography, the difficult point of the technology node research and development high-density diode array device of below 40nm is the crossfire between twin zener dioder array substrate leakage current, adjacent bit lines and between adjacent word line; Effective reduction resistance in series, promotes diode forward driving force; Optimize the reverse breakdown characteristics of diode, increase the switch current ratio of driving element.Wherein, diode array device substrate leakage current depends on wordline buried regions ion implantation technology parameter; Crossfire between adjacent bit lines is by the etching of shallow trench isolation, fill process; The noise current of adjacent word line when array gating switches comes from the etching fill process of deep trench; Forward drive ability when single diode is opened depends on the scale of diode array, wordline length and wordline buried regions ion implantation technology; The reverse breakdown characteristics of unchecked diode will have influence on the static leakage current of whole diode array device, thus causes maloperation, and it is closely related that this and diode form the first conductive type ion injection technology.In sum, need efficient a, low cost and accurately method carry out the relation between combing complicated technological parameter like this and diode array electric parameters.TCAD (Technology Computer Aided Design) is semiconductor process simulation and device simulation instrument, is design and research means effectively and quickly during modern semiconductors manufactures, and is also the beneficial way reducing device manufacturing cost simultaneously.By means of TCAD emulation platform, set up two-dimentional extension double channel diode and drive the process modeling of array and calibrate; Combined process model parameter builds diode array device model, with wafer-level test data for foundation debugging and calibration device model, determines Optimizing Technical; Adopt the diode of parasitic triode network model research multiport to drive internal crosstalk electric current and the substrate leakage current effect of array device, reach the object of optimized device performance.

Current existing diode model, all for single tube device, namely cannot describe the current-voltage relation between each port of multiport diode array.Given this, the present invention proposes a kind of modeling method of extension double channel diode array device, by process modeling and the device model of computer software platform building extension double channel isolating diode array, the ghost effect of main diode array device inside and crosstalk effect, in conjunction with the performance requirement of device application, Optimizing Process Parameters, accomplishes the ghost effect of twin zener dioder array inside effectively, promotes forward and reverse electric property of diode array.This device model is through calibration, there is the dirigibility in array scale, geometric parameter, technological parameter, model dimension etc., can be used for the electric property of Predicting and analysis diode (led) driver part under different performance index request, phase transition storage (PCRAM) is driven as being applied to, resistive memories (RRAM), magnetic storage (MRAM) and ferroelectric memory (FeRAM) etc.

Set up extension double channel isolating diode array device from process modeling, physical model to the simulating scheme of sub circuit model, need the model parameter of many description diode arrays, therefore, device designer can utilize the performance of diode array model dummy diode array quickly and easily, and is optimized device performance and predicts judgement.

Current diode model mostly is single tube model, it is desirable dopant profiles in process modeling, device model only can describe the I-E characteristic of Two-port netwerk, cannot to describe in same wordline crossfire effect between adjacent bit, also cannot describe leakage current and substrate leakage current between wordline.And diode drives array device to be multiport device, need to provide sub circuit model parameter according to the demand of deviser, meet integrated circuit (IC) design, in the unit size driving array and array scale, there is natural activity.

Therefore, be necessary that proposing a kind of new extension double channel isolating diode drives array modeling methods and circuit model to solve the problems referred to above.

Summary of the invention

The shortcoming of prior art in view of the above, a kind of extension double channel isolating diode is the object of the present invention is to provide to drive array modeling methods and circuit model, single tube model mostly is for solving diode model of the prior art, it is desirable dopant profiles in process modeling, device model only can describe the I-E characteristic of Two-port netwerk, crossfire effect between adjacent bit cannot to be described in same wordline, also cannot describe the problem of leakage current and substrate leakage current between wordline.

For achieving the above object and other relevant objects, the invention provides a kind of extension double channel isolating diode and drive array modeling methods, described modeling method at least comprises: (1) extracts process modeling parameter and the device parameter of the diode array device under single device size, scale and basic process condition; (2) according to the process modeling parameter extracted in step (1) and device parameter, the process modeling under different components size and scale and different technology conditions and device model is set up; (3) according to the process modeling parameter under the parameter testing result verification different components size of experiment flow, scale and different technology conditions and device parameter; (4) the interdependence relation of diode electrology characteristic and device size, process modeling parameter and device parameter is set up according to the process modeling parameter after verification in step (3) and device parameter; (5) the inner forward drive current of parasitic triode network model dummy diode array, relation between crossfire and substrate leakage current is utilized; (6) the diode array inside forward drive current obtained in foundation step (5), the relation between crossfire and substrate leakage current, the process optimization condition of verification diode array device.

Preferably, the process modeling parameter extracting the diode array device under single device size, scale and basic process condition in described step (1) comprises step: (a) sets up the diffusion model of different impurity in silicon; B () calibrates the diffusion model of each impurity in silicon according to the Seamlessly Multiple Data Sources Integration that each impurity distributes; C () extracts the process modeling parameter under one group of single size, scale and basic process condition, build the device architecture of N*N extension double channel isolating diode array with this.

Preferably, the described impurity in described step (a) comprises arsenic, phosphorus, boron, boron fluoride and germanium.

Preferably, the described process modeling parameter in described step (c) comprises arsenic doping concn, wordline fill process maximum temperature, wordline fill process time in PN junction area, silicon epitaxy layer thickness, the shallow-trench isolation degree of depth, bit line isolation width, wordline isolation width, wordline buried regions.

Preferably, single device size is extracted in described step (1), the device parameter of the diode array device under scale and basic process condition comprises step: (d) sets up single size on Sdevice platform, device electrical model under scale and basic process condition: (e) adopts the method characterizing device electric property of four ports emulation, and carry out the Two-port netwerk IF of single diode, IR and four port IF, IW, ID, the electrical testing of IB: (f) is according to measured data calibration device model parameter, extract the index characterizing diode array performance simultaneously.

Preferably, the index of described sign diode array performance comprises: diode series resistance R _s, with the contact resistance R of electrode _cT, metal interconnected line resistance R _m, leakage current IWL between wordline and wordline.

Preferably, the step setting up the process modeling under different components size and scale and different technology conditions in described step (2) comprises: (g) carries out grouping experiment to the test result of technological parameter in diode array device under described basic process condition; H () sets up the diode array process modeling of different components size and different array scale on Sprocess platform.

Preferably, the step setting up the device model under different components size and scale and different technology conditions in described step (2) comprises: (i), according to the diode array process modeling set up in described step (h), extracts the device electrology characteristic parameter of different components size, scale and different technology conditions; J () determines preferred technological parameter according to the simulation results.

Preferably, the interdependence of diode electrology characteristic and device size, process modeling parameter and device parameter described in described step (4) is closed and is: $\mathrm{ID}\∝(\mathrm{EPI}\_\mathrm{THK}),(\mathrm{BNL}\_\mathrm{Dose}),\frac{1}{(\mathrm{STI}\_\mathrm{Depth})};\mathrm{IB}\∝\frac{1}{(\mathrm{EPI}\_\mathrm{THK})},\frac{1}{(\mathrm{BNL}\_\mathrm{Dose})},\frac{1}{(\mathrm{STI}\_\mathrm{Depth})};$ Wherein EPI_THK is silicon epitaxy layer thickness; BNL_Dose is arsenic doping concn in wordline buried regions; STI_Depth is the degree of depth of shallow-trench isolation.

Preferably, the variation range of described epitaxy layer thickness is 2 ~ 5 μm; In wordline buried regions, the variation range of arsenic doping concn is at 1.0e15 ~ 7.0e15cm ^-2.

The present invention also provides a kind of extension double channel isolating diode to drive the realistic model of array, and this realistic model at least comprises: the silicon substrate area with the first conduction type; Be defined in the highly doped wordline buried region on silicon substrate; Described wordline buried region has the second conduction type; Be located at the diode array on highly doped silicon substrate; Be formed at the shallow trench isolation between described diode array; Wordline buried region is provided with two exits, and these two exits are connected to the first metal layer be positioned at above described diode array and the second metal level be positioned at above described the first metal layer simultaneously; Diode region field surface is connected to described the first metal layer.

Preferably, the second metal level be connected with described two exits forms the word line end of this diode; The first metal layer be connected with described Diode facets region forms the bit line end of diode.

Preferably, described first conduction type is P type, and described second conduction type is N-type.

Preferably, described realistic model comprises: the parasitic triode effect of diode array device inside, crossfire effect and substrate leakage current effect; Described parasitic triode is based on Gummel-Poon model, and wordline buried regions is the base of parasitic triode, and the anode of neighboring diode unit is respectively horizontal parasitic triode emitter and collector, and substrate terminal is the collector of vertical direction triode.The port current that triode forms network structure is: IF _(ni-1)=β _h× IW, IB=β _v× IW; IF _ni=IW+IF _(ni-1), IF _ni=IW+IB; wherein β _hfor horizontal direction parasitic triode electric current static gain; β _vfor vertical direction parasitic triode electric current static gain; g _mfor mutual conductance; IF, IW, ID, IB are respectively four ports of single diode electrical testing.

As mentioned above, extension double channel isolating diode of the present invention drives array modeling methods and sub circuit model, there is following beneficial effect: the modeling method of the extension double channel isolating diode array that the present invention proposes, and the parameter extraction of process modeling and device model and calibration steps, can effectively, on device simulation platform TCAD software, realize the design and optimization of device architecture accurately and quickly.The crosstalk effect of diode array device inside of multiport and the sub circuit model of leakage current effects, can the ghost effect of fast prediction device inside, for device performance optimization provides strong foundation.This model can be applied to various memory device, is particularly applied to phase transition storage, in high-density city, solves original driving element and takies the large difficult problem of chip area; Flow cost is solved high, the problems such as the test period is long in device layout; In optimal design, achieve and drop into exchanged effective device optimization scheme for device simulation, the minimum like this experiment of electronic circuit emulation.

Accompanying drawing explanation

Fig. 1 is shown as the schematic flow sheet that extension double channel isolating diode of the present invention drives array modeling methods.

Fig. 2 is shown as the device architecture schematic diagram of the two ditch isolating diode array of N*N extension of the present invention.

Fig. 3 is shown as the realistic model structural representation that extension double channel isolating diode of the present invention drives array.

Element numbers explanation

10 silicon substrate area

11 wordline buried region

12 diode arrays

13 shallow trench isolations

14,15 exits

16 the first metal layers

17 second metal levels

S1 ~ S6 step

Embodiment

Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this instructions can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this instructions also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.

Refer to Fig. 1 to Fig. 3.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.

As shown in Figure 1, Fig. 1 is shown as the schematic flow sheet that extension double channel isolating diode of the present invention drives array modeling methods.First implementation step one: the process modeling parameter and the device parameter that extract the diode array device under single device size, scale and basic process condition; Preferably, the process modeling parameter extracting the diode array device under single device size, scale and basic process condition in described step one comprises step: (a) sets up the diffusion model of different impurity in silicon; B () calibrates the diffusion model of each impurity in silicon according to the Seamlessly Multiple Data Sources Integration that each impurity distributes; C () extracts the process modeling parameter under one group of single size, scale and basic process condition, build the device architecture of N*N extension double channel isolating diode array with this.

Sprocess platform is set up the diffusion model of different impurity in silicon (Si), and according to the SIMS data calibration arsenic that each impurity distributes, phosphorus, boron, boron fluoride, the diffusion model of the impurity such as germanium in Si, extract one group of single size, process modeling parameter under scale and basic process condition, process modeling parameter described in the present embodiment comprises: PN junction area (AA), silicon epitaxy layer thickness (EPI_THK), the degree of depth (STI_Depth) of shallow-trench isolation, bit line isolation width (STI_CD), wordline isolation width (DT_CD), arsenic doping concn (BNL_Dose) in wordline buried regions, the wordline fill process time (HARP_time), wordline fill process maximum temperature (HARP_temp), build the device architecture of the two ditch isolating diode array of N*N extension of two dimension, utilize manufacturing process command statement in TCAD software, as shown in Figure 2, the Si substrate 10 that a region is is chosen in two-dimensional coordinate system, and there is the first conduction type (T1), then on substrate, define wordline buried regions 11 region of high-concentration dopant, there is the second conduction type (T2), Si Grown homotype silicon epitaxy layer after highly doped, adopt the shallow-trench isolation 13 between chemical etching technique formation wordline, then in shallow-trench isolation, monox is filled as dielectric isolation layer, by exposure, ion implantation and annealing process are formed at diode array 12 has the first conduction type (T1) region, and at wordline exit 14 and wordline exit 15 with form the second conduction type (T2) region, two exit surf zone definition nickel silicides of wordline, be connected with the first metal layer 16 by ground floor via hole (V1) again, and be connected with the second metal level 17 by second layer via hole (V2), form word line end (WL), diode region field surface defines nickel silicide equally, by ground floor via hole (V1) and the first metal layer 16, form diode bit line end (BL _ni), if the first conduction type is P type, then the second conduction type is N-type, and vice versa.

The device parameter extracting the diode array device under single device size, scale and basic process condition in described step one comprises step: (d) sets up the device electrical model under single size, scale and basic process condition on Sdevice platform: (e) adopts the method characterizing device electric property of four port emulation, and carry out Two-port netwerk IF, IR of single diode and the electrical testing of four port IF, IW, ID, IB: (f), according to measured data calibration device model parameter, extracts the index characterizing diode array performance simultaneously.Preferably, the index of described sign diode array performance comprises: diode series resistance R _s, with the contact resistance R of electrode _cT, metal interconnected line resistance R _m, leakage current IWL between wordline and wordline.

Have in the diode array of N*N: iR ≈ I ₀; IF=IW+ID+IB;

$R_s=\frac{((n_i+0.5)R_{\mathrm{BNL}}+R_{\mathrm{CT}}+R_M)\×((N-(n_i+0.5))R_{\mathrm{BNL}}+R_{\mathrm{CT}}+R_M)}{{\mathrm{NR}}_{\mathrm{BNL}}}+R_{\mathrm{CT}}+R_M;$

$R_{\mathrm{BNL}}\∝(\frac{1}{(\mathrm{BNL}\_\mathrm{Dose})},n,\mathrm{AA});\mathrm{IWL}\∝\frac{1}{(\mathrm{DT}\_\mathrm{CD})};$ Wherein, IF is diode bit line end electric current, ID is the bit line current (crossfire) of the diode of adjacent closedown, IW is word line end electric current, IB is diode array substrate leakage current, diode pull-down current when IR is two ends test, N*N represents the scale of diode array, n _ibe i-th diode in a wordline, R _cTand R _mbe respectively via hole V _iwith metal wire M _iresistance, be definite value, R _bNLfor the total resistance value of wordline buried regions BNL.

Then implementation step two: according to the process modeling parameter extracted in step one and device parameter, sets up the process modeling under different components size and scale and different technology conditions and device model.Preferably, the step setting up the process modeling under different components size and scale and different technology conditions in described step 2 comprises: (g) carries out grouping experiment to the test result of technological parameter in diode array device under described basic process condition; H () sets up the diode array process modeling of different components size and different array scale on Sprocess platform.The step setting up the device model under different components size and scale and different technology conditions in described step 2 comprises: (i), according to the diode array process modeling set up in described step (h), extracts the device electrology characteristic parameter of different components size, scale and different technology conditions; J () determines preferred technological parameter according to the simulation results.

Then implementation step three and step 4: according to the process modeling parameter under the parameter testing result verification different components size of experiment flow, scale and different technology conditions and device parameter; According to the process modeling parameter under the parameter testing result verification different components size of experiment flow, scale and different technology conditions and device parameter.The diode set up drives the interdependence between matrix ports electric current and geometric parameter, technological parameter to close: $\mathrm{ID}\∝(\mathrm{EPI}\_\mathrm{THK}),(\mathrm{BNL}\_\mathrm{Dose}),\frac{1}{(\mathrm{STI}\_\mathrm{Depth})};\mathrm{IB}\∝\frac{1}{(\mathrm{EPI}\_\mathrm{THK})},\frac{1}{(\mathrm{BNL}\_\mathrm{Dose})},\frac{1}{(\mathrm{STI}\_\mathrm{Depth})};$ Wherein EPI_THK is silicon epitaxy layer thickness; BNL_Dose is arsenic doping concn in wordline buried regions; STI_Depth is the degree of depth of shallow-trench isolation.Set up diode electric property and device geometries (including the area of source region AA, epitaxy layer thickness, the STI degree of depth, PN junction depth Xj etc.), interdependence relation between process modeling parameter (time and temperature etc. of ion implantation technology dosage and concentration, Technology for Heating Processing time and temperature, epitaxy technique) and device parameter (Electrodes, physical model statistic property etc.), and this model can be extended in process node of future generation and be applied.

Step 5: utilize the inner forward drive current of parasitic triode network model dummy diode array, relation between crossfire and substrate leakage current.

Step 6: the diode array inside forward drive current obtained in foundation step 5, the relation between crossfire and substrate leakage current, the process optimization condition of verification diode array device.With reference to the electrical testing data of diode array, adopt the relation of diode array endophyte triode network simulation diode array forward drive current and internal crosstalk electric current (ID) and substrate leakage current (IB), the process optimization condition of further checking diode array device, in conjunction with this electrical network model, the electrology characteristic curve of characterizing device multiport, for circuit design provides foundation; Diode array modeling under other process nodes can refer to the method.

The present invention also provides a kind of extension double channel isolating diode to drive the electronic circuit realistic model of array, and this realistic model comprises as shown in Figure 3: the silicon substrate area 10 with the first conduction type; Be defined in the highly doped wordline buried region 11 on silicon substrate; Described wordline buried region has the second conduction type; Be located at the diode array 12 on highly doped silicon substrate; Be formed at the shallow trench isolation 13 between described diode array; Wordline buried region is provided with two exits 14,15, and these two exits are connected to the first metal layer 16 be positioned at above described diode array and the second metal level 17 be positioned at above described the first metal layer simultaneously; Described diode region field surface is connected to described the first metal layer.Preferably, the second metal level be connected with described two exits forms the word line end of this diode; The first metal layer be connected with described Diode facets region forms the bit line end of diode.In the present embodiment, described first conduction type is N-type, and described second conduction type is P type.Meanwhile, described realistic model of the present invention comprises: the parasitic triode effect of diode array device inside, crossfire effect and substrate leakage current effect; Described parasitic triode is based on Gummel-Poon model, and wordline buried regions is the base of parasitic triode, and the anode of neighboring diode unit is respectively horizontal parasitic triode emitter and collector, and substrate terminal is the collector of vertical direction triode.The port current that triode forms network structure is: IF _(ni-1)=β _h× IW, IB=β _v× IW; iF _ni=IW+IF _(ni-1), IF _ni=IW+IB; Wherein β H is horizontal direction parasitic triode electric current static gain; β _vfor vertical direction parasitic triode electric current static gain; g _mfor mutual conductance; IF, IW, ID, IB are respectively four ports of single diode electrical testing.

Preferred case study on implementation provided by the invention, analyze from the physical arrangement of extension double channel diode and working mechanism, process modeling parameter AA, EPI_THK, STI_Depth, STI_CD, DT_CD, BNL_Dose, HARP_time, HARP_temp, being subject to device geometries, scale and process conditions affected, therefore, for similar (physical dimension is identical with process conditions) diode array, port current value (IF, IW, ID, IB) only with diode array scale N linear decrease; Device parameter μ, τ, R _s, R _cT, R _mbe subject to the impact of process conditions, constant is kept for the above-mentioned device parameters of the process node determined; Sub circuit model parameter AA, I _s, R _s, η, tt, C _j0, m, E _g, f _c, BV and g _m, be subject to the impact of geometrical structure parameter and process conditions, especially with process conditions interdependence strong correlation simultaneously.Wherein, the Parametric Representation in device model is as follows: AA:PN junction area; μ: carrier mobility; τ: carrier lifetime; R _s: diode series resistance; R _cT: with the contact resistance of electrode; R _m: metal interconnection line resistance; I _s: reverse saturation current; R _s: resistance in series; η: the ideal factor of diode; Tt: transit time; C _j0: zero offset electric capacity; M: the capacitance gradient factor; E _g: energy gap; f _c: barrier capacitance positively biased depletion-layer capacitance equation coefficients; BV: voltage breakdown; g _min: mutual conductance; β _h: horizontal direction parasitic triode electric current static gain; β _v: vertical direction parasitic triode electric current static gain.

The present embodiment provides the extension double channel isolating diode array emulation mode of a kind of 16*16.Comprise the following steps:

One, on Sprocess platform, according to SIMS data, the diffusion model of impurity in Si such as calibration arsenic, phosphorus, boron, boron fluoride, germanium etc., extracts the process modeling parameter under one group of single size and scale and basic process condition, comprise: AA, EPI_THK, STI_Depth, STI_CD, DT_CD, BNL_Dose, HARP_time, HARP_temp.

Two, on Sdevice platform, set up the device electrical model under single size and scale and basic process condition, adopt the method characterizing device electric property of four port emulation, prepare array device simultaneously and carry out the Two-port netwerk (IF of single diode, IR) and four port (IF, IW, ID, IB) electrical testing, according to measured data calibration device model parameter, extract diode series resistance (R simultaneously _s), with the contact resistance (R of electrode _cT), metal interconnection line resistance (R _m), the leakage currents (IWL) between wordline and wordline etc. characterize the index of diode array performance, for the 8th diode that array is middle, and resistance in series R during unlatching ₈can be expressed as:

$R_8=\frac{({8.5R}_{\mathrm{BNL}}+R_{\mathrm{CT}}+R_M)\×({7.5R}_{\mathrm{BNL}}+R_{\mathrm{CT}}+R_M)}{{16R}_{\mathrm{BNL}}}+R_{\mathrm{CT}}+R_M$

Three, the diode array process modeling of different components size and different array scale is set up, extract the device electrology characteristic parameter of different components size, scale and different technology conditions, preferred technological parameter is tentatively determined according to model emulation result, adopt the test result of different technology conditions flow experiment to calibrate all device models simultaneously, establish diode and drive interdependence relation between matrix ports electric current and geometric parameter, technological parameter:

$\mathrm{IF}\∝\frac{1}{(\mathrm{EPI}\_\mathrm{THK})},(\mathrm{BNL}\_\mathrm{Dose}),\frac{1}{(\mathrm{STI}\_\mathrm{Depth})}$

$\mathrm{ID}\∝(\mathrm{EPI}\_\mathrm{THK}),(\mathrm{BNL}\_\mathrm{Dose}),\frac{1}{(\mathrm{STI}\_\mathrm{Depth})}$

$\mathrm{IB}\∝\frac{1}{(\mathrm{EPI}\_\mathrm{THK})},\frac{1}{(\mathrm{BNL}\_\mathrm{Dose})},\frac{1}{(\mathrm{STI}\_\mathrm{Depth})}$

Wherein, epitaxy layer thickness EPI_THK variation range is at 2 ~ 5 μm, and BNL_Dose dopant dose variation range is at 1.0e15 ~ 7.0e15cm ^-2, the depth S TI_Depth variation range 2.8 ~ 3.3 μm of STI isolation, according to measured data, calibration device model, by numerical fitting, calibrates port output current (IF, IW, ID, IB).

Four, diode electric property and device geometries, interdependence relation between process modeling parameter and device parameter is set up, determine the optimized parameter of electric property, namely, IF/IR is maximum, under identical reversed bias voltage, IR is minimum, process parameter models corresponding when ID/IF and IB/IF is minimum;

Five, with reference to the electrical testing data of diode array, adopt the relation of diode array endophyte triode network simulation diode array forward drive current and internal crosstalk electric current (ID) and substrate leakage current (IB), the process optimization condition of further checking diode array device, in conjunction with this electrical network model, the electrology characteristic curve of characterizing device multiport, for circuit design provides foundation.

The present invention carries out modeling, emulation to the process modeling of the extension double channel isolating diode array device under different geometrical size, scale and process conditions, device model and sub circuit model and calibrates.From physical arrangement and the working mechanism of extension double channel isolating diode array, set up a set of from technique, device to sub circuit model, the interdependence relation between Modling model parameter.The method can be determined to affect diode array electrology characteristic relevant geometric parameter, technological parameter and device parameters effectively.By the electrical performance requirements of diode array device, in conjunction with device simulation result, select corresponding geometry, technological parameter fast, expediently.The method of this cover organs weight and emulation, not only can emulate the electric property of the diode array of any physical dimension, scale and process conditions, model after calibration can also meet the accuracy requirement of circuit design, and makes prediction and analysis to device generations performance.

In sum, the modeling method of the extension double channel isolating diode array that the present invention proposes, and the parameter extraction of process modeling and device model and calibration steps, can effectively, on device simulation platform TCAD software, realize the design and optimization of device architecture accurately and quickly.The crosstalk effect of diode array device inside of multiport and the sub circuit model of leakage current effects, can the ghost effect of fast prediction device inside, for device performance optimization provides strong foundation.This model can be applied to various memory device, is particularly applied to phase transition storage, in high-density city, solves original driving element and takies the large difficult problem of chip area; Flow cost is solved high, the problems such as the test period is long in device layout; In optimal design, achieve and drop into exchanged effective device optimization scheme for device simulation, the minimum like this experiment of electronic circuit emulation.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.

Claims (14)

1. extension double channel isolating diode drives a modeling method for array, and it is characterized in that, described modeling method at least comprises:

(1) process modeling parameter and the device parameter of the diode array device under single device size, scale and basic process condition is extracted;

(2) according to the process modeling parameter extracted in step (1) and device parameter, the process modeling under different components size and scale and different technology conditions and device model is set up;

(3) according to the process modeling parameter under the parameter testing result verification different components size of experiment flow, scale and different technology conditions and device parameter;

(4) the interdependence relation of diode electrology characteristic and device size, process modeling parameter and device parameter is set up according to the process modeling parameter after verification in step (3) and device parameter;

(5) the inner forward drive current of parasitic triode network model dummy diode array, relation between crossfire and substrate leakage current is utilized;

(6) the diode array inside forward drive current obtained in foundation step (5), the relation between crossfire and substrate leakage current, the process optimization condition of verification diode array device.

2. extension double channel isolating diode according to claim 1 drives the modeling method of array, it is characterized in that: the process modeling parameter extracting the diode array device under single device size, scale and basic process condition in described step (1) comprises step: (a) sets up the diffusion model of different impurity in silicon; B () calibrates the diffusion model of each impurity in silicon according to the Seamlessly Multiple Data Sources Integration that each impurity distributes; C () extracts the process modeling parameter under one group of single size, scale and basic process condition, build the device architecture of N*N extension double channel isolating diode array with this.

3. extension double channel isolating diode according to claim 2 drives the modeling method of array, it is characterized in that: the described impurity in described step (a) comprises arsenic, phosphorus, boron, boron fluoride and germanium.

4. extension double channel isolating diode according to claim 2 drives the modeling method of array, it is characterized in that: the described process modeling parameter in described step (c) comprises arsenic doping concn, wordline fill process maximum temperature, wordline fill process time in PN junction area, silicon epitaxy layer thickness, the shallow-trench isolation degree of depth, bit line isolation width, wordline isolation width, wordline buried regions.

5. extension double channel isolating diode according to claim 4 drives the modeling method of array, it is characterized in that: in described step (1), extract single device size, the device parameter of the diode array device under scale and basic process condition comprises step: (d) sets up single size on Sdevice platform, device electrical model under scale and basic process condition: (e) adopts the method characterizing device electric property of four ports emulation, and carry out the Two-port netwerk IF of single diode, IR and four port IF, IW, ID, the electrical testing of IB: (f) is according to measured data calibration device model parameter, extract the index characterizing diode array performance simultaneously.

6. extension double channel isolating diode according to claim 5 drives the modeling method of array, it is characterized in that: the index of described sign diode array performance comprises: diode series resistance R _s, with the contact resistance R of electrode _cT, metal interconnected line resistance R _m, leakage current IWL between wordline and wordline.

7. extension double channel isolating diode according to claim 6 drives the modeling method of array, it is characterized in that: the step setting up the process modeling under different components size and scale and different technology conditions in described step (2) comprises: (g) carries out grouping experiment to the test result of technological parameter in diode array device under described basic process condition; H () sets up the diode array process modeling of different components size and different array scale on Sprocess platform.

8. extension double channel isolating diode according to claim 7 drives the modeling method of array, it is characterized in that: the step setting up the device model under different components size and scale and different technology conditions in described step (2) comprises: (i), according to the diode array process modeling set up in described step (h), extracts the device electrology characteristic parameter of different components size, scale and different technology conditions; J () determines preferred technological parameter according to the simulation results.

9. extension double channel isolating diode according to claim 7 drives the modeling method of array, it is characterized in that: described in described step (4), the interdependence of diode electrology characteristic and device size, process modeling parameter and device parameter is closed and is: $\mathrm{IF}\∝\frac{1}{(\mathrm{EPI}\_\mathrm{THK})},(\mathrm{BNL}\_\mathrm{Dose}),\frac{1}{(\mathrm{STI}\_\mathrm{Depth})};\mathrm{ID}\∝(\mathrm{EPI}\_\mathrm{THK}),(\mathrm{BNL}\_\mathrm{Dose}),\frac{1}{(\mathrm{STI}\_\mathrm{Depth})};$ $\mathrm{IB}\∝\frac{1}{(\mathrm{EPI}\_\mathrm{THK})},\frac{1}{(\mathrm{BNL}\_\mathrm{Dose})},\frac{1}{(\mathrm{STI}\_\mathrm{Depth})};$ Wherein EPI_THK is silicon epitaxy layer thickness; BNL_Dose is arsenic doping concn in wordline buried regions; STI_Depth is the degree of depth of shallow-trench isolation.

10. extension double channel isolating diode according to claim 8 drives the modeling method of array, it is characterized in that: the variation range of described epitaxy layer thickness is 2 ~ 5 μm; In wordline buried regions, the variation range of arsenic doping concn is at 1.0e15 ~ 7.0e15cm ^-2.

11. 1 kinds of extension double channel isolating diodes drive the realistic model of array, it is characterized in that: this realistic model at least comprises: the silicon substrate area (10) with the first conduction type; Be defined in the highly doped wordline buried region (11) on silicon substrate; Described wordline buried region has the second conduction type; Be located at the diode array (12) on highly doped silicon substrate;

Be formed at the shallow trench isolation (13) between described diode array;

Wordline buried region is provided with two exits (14,15), these two exits are connected to the first metal layer (16) be positioned at above described diode array and the second metal level (17) be positioned at above described the first metal layer simultaneously; Described diode region field surface is connected to described the first metal layer.

12. extension double channel isolating diodes according to claim 11 drive the realistic model of array, it is characterized in that: the second metal level be connected with described two exits forms the word line end of this diode; The first metal layer be connected with described Diode facets region forms the bit line end of diode.

13. extension double channel isolating diodes according to claim 11 drive the realistic model of array, and it is characterized in that: described first conduction type is P type, described second conduction type is N-type.

14. extension double channel isolating diodes according to claim 12 drive the realistic model of arrays, it is characterized in that: described realistic model comprises: the parasitic triode effect of diode array device inside, crossfire effect and substrate leakage current effect; Described parasitic triode is based on Gummel-Poon model, and wordline buried regions is the base of parasitic triode, and the anode of neighboring diode unit is respectively horizontal parasitic triode emitter and collector, and substrate terminal is the collector of vertical direction triode.The port current that triode forms network structure is:

IF _(ni-1)=β _h× IW, IB=β _v× IW; IF _ni=IW+IF _(ni-1), IF _ni=IW+IB; wherein β _hfor horizontal direction parasitic triode electric current static gain; β _vfor vertical direction parasitic triode electric current static gain; g _mfor mutual conductance; IF, IW, ID, IB are respectively four ports of single diode electrical testing.