CN106560909A - Test structure and forming method and test method thereof - Google Patents
Test structure and forming method and test method thereof Download PDFInfo
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- CN106560909A CN106560909A CN201510642572.4A CN201510642572A CN106560909A CN 106560909 A CN106560909 A CN 106560909A CN 201510642572 A CN201510642572 A CN 201510642572A CN 106560909 A CN106560909 A CN 106560909A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
Provided is a test structure and a forming method and test method thereof. The test structure comprises an area to be tested and a supporting base of a peripheral area surrounding the area to be tested, a well region positioned in fin portions and a supporting base of the area to be tested and the peripheral area, an isolation layer placed on the surface of the supporting base, a first gate structure crossing the fin portions in the area to be tested, a source and drain area positioned in the fin portions of two sides of the first gate structure, multiple diode doped regions positioned in the fin portions of the peripheral area and first electric conducting structures arranged on the surfaces of the diode doped regions. The surfaces of the area to be tested and the supporting base of the peripheral area are provided with at least one strip of fin portion respectively, a plurality of fin portions of the area to be tested and the peripheral area are parallel, and two ends of at least one strip of fin portion of the area to be tested are extended into the peripheral area; the multiple diode doped regions surround the area to be tested, the multiple diode doped regions placed in the same fin portion are discrete with each other, and the diode doped regions are discrete with the source and drain area; the first electric conducting structures cross at least one strip of fin portion. The test structure can conduct detection and monitoring on the spontaneous heating of the supporting base.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of test structure and forming method thereof,
Method of testing.
Background technology
With developing rapidly for semiconductor fabrication, semiconductor device towards higher component density, with
And the direction of higher integrated level is developed.Transistor is just extensive at present as most basic semiconductor device
Using, therefore the raising of the component density and integrated level with semiconductor device, the grid of planar transistor
Size is also shorter and shorter, and traditional planar transistor dies down to the control ability of channel current, produces short ditch
Channel effect, produces leakage current, the final electric property for affecting semiconductor device.
In order to overcome the short-channel effect of transistor, leakage current, prior art is suppressed to propose fin field effect
Transistor (Fin FET) is answered, fin formula field effect transistor is a kind of common multi-gate device.Imitate fin field
The structure of transistor is answered to include：Positioned at the fin and dielectric layer of semiconductor substrate surface, the dielectric layer covers
The side wall of fin described in cover, and dielectric layer surface is less than at the top of fin；Positioned at dielectric layer surface, with
And top and the grid structure of sidewall surfaces of fin；Source in the fin of the grid structure both sides
Area and drain region.
However, the size with semiconductor device constantly reduces, the distance between fin is gradually little, causes fin
Heat-sinking capability between portion is deteriorated, and the heat accumulation in fin easily causes fin formula field effect transistor
Degradation.Therefore, know between the heat in fin and fin formula field effect transistor performance relation into
Judge one of key factor of reliability.
The content of the invention
The problem that the present invention is solved is to provide a kind of test structure and forming method thereof, method of testing, described
Test structure can be detected and be monitored to substrate spontaneous heating.
To solve the above problems, the present invention provides a kind of test structure, including：Substrate, the substrate bag
Include area to be measured and surround the substrate surface difference of the external zones in the area to be measured, the area to be measured and external zones
With at least one fin, some fins of the area to be measured and external zones are parallel to each other, the area to be measured
The two ends of at least one fin are extended in the external zones；Positioned at area to be measured and the fin and lining of external zones
Well region in bottom；Positioned at the sealing coat of the substrate surface, the sealing coat covers the part of the fin
Sidewall surfaces；Across the first grid structure of fin in area to be measured, the first grid structure is located to be measured
The partial sidewall and top surface of area's fin；Source-drain area in the fin of first grid structure both sides；Position
Some diode doped regions in external zones fin, some diode doped regions surround the area to be measured,
Some diode doped regions in same fin are mutually discrete, and the diode doped region with it is described
Source-drain area is mutually discrete；Positioned at first conductive structure on the diode doped region surface, described first leads
Electric structure is across at least one fin.
Optionally, also include：Across the second grid structure of fin in external zones, the second grid knot
The partial sidewall and top surface of the peripherally located area's fin of structure, some second grid parallelism structurals, institute
State second grid structure and first grid parallelism structural.
Optionally, between adjacent second grid structure there is in fin a diode doped region.
Optionally, the second grid structure is across one or some fins arranged in parallel.
Optionally, the second grid structure includes：Grid positioned at fin partial sidewall and top surface are situated between
Matter layer, the grid layer positioned at gate dielectric layer surface and positioned at grid layer and gate dielectric layer sidewall surfaces
Side wall.
Optionally, the material of the gate dielectric layer is silicon oxide；The material of the grid layer is polysilicon.
Optionally, the first grid structure includes：Grid positioned at fin partial sidewall and top surface are situated between
Matter layer, the grid layer positioned at gate dielectric layer surface and positioned at grid layer and gate dielectric layer sidewall surfaces
Side wall.
Optionally, the material of the gate dielectric layer is high K medium material；The material of the grid layer includes
Metal or metallic compound.
Optionally, also include：Positioned at second conductive structure on well region surface, second conductive structure is horizontal
Across at least one fin.
Optionally, also include：Positioned at the 3rd conductive structure on the source-drain area surface, the described 3rd is conductive
Structure is across at least two fins.
Optionally, the dopant ion type of the dopant ion type in the well region and diode doped region is not
Together.
Optionally, in the area to be measured, the quantity of the first grid structure is more than or equal to 1,
And each first grid structure is across one or some fins arranged in parallel.
Optionally, when the first grid number of structures in the area to be measured is more than 1, some first grids
Parallelism structural is arranged.
Optionally, at least one diode doped region is located in same fin with source-drain area.
Optionally, also include：Positioned at the dielectric layer of sealing coat, fin and first grid body structure surface；Institute
The first conductive structure is stated in the dielectric layer, and through the dielectric layer.
Optionally, first conductive structure is also located at the sidewall surfaces and part sealing coat table of part fin
Face.
Accordingly, the present invention also provides a kind of forming method of above-mentioned test structure, including：Lining is provided
Bottom, the substrate include area to be measured and surround the external zones in the area to be measured, the area to be measured and external zones
Substrate surface mutually put down with some fins of at least one fin, the area to be measured and external zones respectively
OK, the two ends of at least one fin of area to be measured are extended in the external zones；In the area to be measured and
Well region is formed in the fin and substrate of external zones；Sealing coat, the sealing coat are formed in the substrate surface
Cover the partial sidewall surface of the fin；It is developed across the first grid structure of fin in area to be measured, institute
State partial sidewall and top surface of the first grid structure positioned at area's fin to be measured；In first grid structure two
Source-drain area is formed in lateral fin portion；Some diode doped regions, some diodes are formed in external zones fin
Doped region surrounds the area to be measured, and some diode doped regions in same fin are mutually discrete, and
The diode doped region is mutually discrete with the source-drain area；The is formed on the diode doped region surface
One conductive structure, first conductive structure is across at least one fin.
Accordingly, the present invention also provides a kind of method of testing, it is characterised in that include：There is provided above-mentioned
Test structure described in one, the first grid structure and positioned at a group of first grid structure both sides
Source-drain area constitutes test transistor, and the diode doped region and well region constitute a diode, described to treat
Survey area and there is at least one test transistor, the external zones has some diodes；Open described to be measured
Transistor and diode；After the test transistor and diode is opened, at interval of preset time period
Afterwards, some diodes are carried out with a temperature test, the temperature of some diode doped regions is obtained；
After temperature test several times is carried out to some diodes, the temperature in external zones fin is obtained with the time
Variation relation information.
Optionally, include the step of the temperature test：The forward conduction voltage of some diodes is carried out
Detection；By the linear relationship between diode forward conducting voltage and fin temperature, obtain diode and mix
The temperature in miscellaneous area.
Compared with prior art, technical scheme has advantages below：
In the structure of the present invention, the fin portion surface in the area to be measured has first grid structure, and first
There is in the fin of grid structure both sides source-drain area；When raceway groove in the fin of the first grid structural base
When area opens, the fin in area to be measured starts heating.As at least one fin two ends of the area to be measured extend
To external zones, and some diode doped regions in external zones fin, and if in same fin
Dry diode doped region is mutually discrete, therefore, the heat in area's fin to be measured is easy to outside with carrier
Enclose the fin transmission in area.As some diode doped regions surround the area to be measured, therefore, it is possible to
Heat produced by enabling in area's fin to be measured is transferred in the fin of whole external zones.Every one section
Preset Time carries out temperature test to the diode doped region in the external zones, i.e., can obtain some two
The temperature of pole pipe doped region, and it is further able to obtain the fin temperature of external zones diverse location with the time
Variation relation information, for example, can draw the temperature isothermal line of external zones fin trend over time.
Therefore, by the test structure, the device in area to be measured can be known for the temperature of external zones diverse location
Degree affects such that it is able to which the processing procedure, structure and electrical property to device is adjusted.
Further, the fin portion surface in the external zones is also with some second grid structures across fin,
And some second grid parallelism structurals, and diode doped region is located at the fin between adjacent second grid structure
In portion.The second grid structure is used for the diode doped region for defining adjacent discrete, makes neighboring diode
Doped region is located at second grid structure both sides；And, the second grid structure and first grid structure
Structure is identical, and the second grid structure can be formed simultaneously with first grid structure, the second grid
The formation process of structure is simple.Directly two are formed as adulterating in fin using the second grid structure
The mask of pole pipe doped region, can make the formation work of some discrete diode doped region of formation in fin
Skill simplifies, and the accuracy to size of the diode doped region for being formed is improved, then performance is more homogeneous steady
It is fixed.
In the forming method of the present invention, the fin portion surface in the area to be measured forms first grid structure,
And source-drain area is formed in the fin of first grid structure both sides；When the fin of the first grid structural base
When in portion, channel region is opened, the fin in area to be measured starts heating.Due at least one fin of area to be measured
Two ends are extended in external zones, form some diode doped regions, and be located at same in external zones fin
Some diode doped regions in fin are mutually discrete, therefore, the heat in area's fin to be measured be easy to
Carrier to the periphery area fin transmission.As some diode doped regions for being formed surround described to be measured
Area, therefore, it is possible to enable heat produced in area's fin to be measured to be transferred to the fin of whole external zones
It is interior.Temperature test, energy are being carried out to the diode doped region in the external zones every one section of Preset Time
The temperature of some diode doped regions is enough obtained, and is further able to obtain the fin of external zones diverse location
Temperature relation information over time, therefore, the device in area to be measured can be known by the test structure
Part is affected for the temperature of external zones diverse location such that it is able to the processing procedure, structure and electrical property to device
Adjust.
In the method for testing of the present invention, due to the heat produced by area's fin to be measured can be transferred to it is whole
In individual external zones fin, temperature is being carried out to the external zones diode doped region every one section of Preset Time
Degree test, can obtain the temperature of some diode doped regions, and be further able to obtain the fin of external zones
Portion's temperature relation information over time, therefore, by the method for testing, area to be measured can be known
Device for external zones diverse location temperature affect such that it is able to the processing procedure, structure and electricity to device
Performance is adjusted.
Description of the drawings
Fig. 1 is a kind of overlooking the structure diagram of fin formula field effect transistor of the embodiment of the present invention；
Fig. 2 is cross-sectional views of the Fig. 1 along AA ' directions；
Fig. 3 to Figure 10 is the structural representation of the forming process of the test structure of the embodiment of the present invention；
Figure 11 is the method for testing schematic flow sheet of the embodiment of the present invention.
Specific embodiment
As stated in the Background Art, as the size of semiconductor device constantly reduces, the distance between fin is gradually
It is little, cause fin easily to gather heat, cause the degradation of fin formula field effect transistor.
Find through research, when transistor works, due to producing electric current in the channel region in substrate, then
The channel region can produce heat when opening equivalent to resistance, i.e., described channel region；And, the raceway groove
Area's heating can cause substrate to generate heat.For fin formula field effect transistor, channel region is formed in fin,
Then when channel region is opened, fin can be caused to generate heat.
Refer to Fig. 1 and Fig. 2, Fig. 1 be the embodiment of the present invention a kind of fin formula field effect transistor vertical view
Structural representation, Fig. 2 are cross-sectional views of the Fig. 1 along AA ' directions, including：Substrate 100；Position
In the fin 101 on 100 surface of substrate；Positioned at the sealing coat 102 on 100 surface of substrate, the sealing coat 102
The partial sidewall surface of the fin 101 is covered, and the surface of the sealing coat 102 is less than the fin
101 top surface；Across the grid structure 103 of the fin 101, the grid structure 103 is covered
The partial sidewall and top surface of the fin 101 and 102 surface of part sealing coat；Positioned at described
Source region and drain region 104 in 103 both sides fin 101 of grid structure.
Wherein, some fins 101 are arranged in parallel in X direction, and the grid structure 103 is across some
Fin 101.When fin formula field effect transistor works, the channel region between the source region and drain region 104 is opened
Open, electric current is produced in the channel region and is occurred, cause then fin 101 to generate heat.
However, with feature size downsizing, the device density raising of semiconductor device, the fin 101
Top size reduction in X direction, and the distance between adjacent fin 101 reduces.Due to the fin
Width of the size at the top of portion 101 in X direction for channel region, the channel region width reduce and can cause institute
The resistance increase of channel region is stated, makes the heating of channel region more serious so that spontaneous heating in the fin 101.
And the distance between adjacent fin 101 reduce cause spontaneous heating in the fin 101 heat cannot loss,
So as to the temperature for causing the fin 101 is gradually increasing.And 101 temperature of fin is raised and will cause fin
A series of electrical properties of formula field-effect transistor change, for example saturation current, subthreshold swing
(Sub-threshold Swing), causes the hydraulic performance decline of fin formula field effect transistor.Therefore, understand fin
Relation between the spontaneous heating in portion 101 and the electrical of fin formula field effect transistor becomes to regulate and control and improve fin
The important means of field-effect transistor.
In order to solve the above problems, the present invention provides a kind of test structure and forming method thereof, method of testing.
The test structure includes：Substrate, the substrate include the external zones in area to be measured and the encirclement area to be measured,
The substrate surface of the area to be measured and external zones has at least one fin, the area to be measured and periphery respectively
Some fins in area are parallel to each other, and the two ends of at least one fin of area to be measured extend to the external zones
It is interior；Positioned at the sealing coat of the substrate surface, the sealing coat covers the partial sidewall surface of the fin；
Well region in the fin and substrate of area to be measured and external zones；Across the first grid of fin in area to be measured
Structure, the first grid structure are located at the partial sidewall and top surface of area's fin to be measured；Positioned at first
Source-drain area in the fin of grid structure both sides；Some diode doped regions in peripherally located area's fin, if
Dry diode doped region surrounds the area to be measured, and some diode doped regions in same fin are mutual
It is discrete, and the diode doped region is mutually discrete with the source-drain area；Positioned at the diode doped region
First conductive structure on surface, first conductive structure is across at least one fin.
Wherein, the fin portion surface in the area to be measured has first grid structure, and first grid structure two
There is in the fin of side source-drain area；When in the fin of the first grid structural base, channel region is opened,
The fin in area to be measured starts heating.As at least one fin two ends of the area to be measured are extended in external zones,
And some diode doped regions in external zones fin, and some diode doping in same fin
Area is mutually discrete, therefore, the heat in area's fin to be measured be easy to carrier to the periphery area fin pass
Pass.As some diode doped regions surround the area to be measured, therefore, it is possible to make area's fin to be measured
Heat produced by interior can be transferred in the fin of whole external zones.Every one section of Preset Time to institute
Stating the diode doped region in external zones carries out temperature test, i.e., can obtain some diode doped regions
Temperature, and be further able to obtain the fin temperature relation information over time of external zones diverse location,
The temperature isothermal line of external zones fin trend over time can for example be drawn.Therefore, by described
Test structure, can know the device in area to be measured for the temperature of external zones diverse location affects, so as to
Processing procedure, structure and electrical property enough to device is adjusted.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 3 to Figure 10 is the structural representation of the forming process of the test structure of the embodiment of the present invention.
Refer to Fig. 3 and Fig. 4, Fig. 4 is cross-sectional views of the Fig. 3 along BB ' directions, there is provided substrate
200, the substrate 200 includes area to be measured 210 and surrounds the external zones 220 in the area to be measured 210, institute
200 surface of substrate for stating area to be measured 210 and external zones 220 has at least one fin 201 respectively, described
Some fins 201 of area to be measured 210 and external zones 220 are parallel to each other, the area to be measured 210 at least
The two ends of bar fin 201 are extended in the external zones 220；In the area to be measured 210 and external zones 220
Fin 201 and substrate 200 in form well region (sign).
The area to be measured 210 is used to form fin formula field effect transistor to be measured, the fin field effect to be measured
Transistor can constitute required semiconductor device or circuit structure.The external zones 220 is used to monitor heat
The situation of the transmission of area 220 to the periphery of fin 201 from area to be measured 210 is measured, if subsequently through detection form
Into the forward conduction voltage (V of the diode in external zones 220be), it is obtained in that the two of external zones 220
The temperature of pole pipe doped region, obtains the Temperature Distribution of 220 diverse location fin 201 of external zones with this.
In the present embodiment, the substrate 200 also includes interconnecting area 230, the interconnecting area of the substrate 200
230 surfaces also have fin 201, and the well region is also located at the substrate 200 and fin of the interconnecting area 230
In 201.201 surface of fin of the interconnecting area 230 is subsequently used for forming the second conductive structure, described
Second conductive structure is for being biased to well region.
201 quantity of fin in the area to be measured 210 is more than or equal to 1；And, when the area to be measured
When in 201, the quantity of fin 201 is more than 1, some fins 201 in area to be measured 210 are arranged in parallel.At this
In embodiment, there are in the area to be measured 201 3 fins 201 arranged in parallel.In other embodiments,
There are in the area to be measured 3～6 fins arranged in parallel.
201 two ends of fin in the area to be measured 210 are extended in external zones 220, subsequently can be same
One fin 201 is located at the source-drain area of first grid structure both sides and the diode in peripherally located area 220
Doped region.The first grid structure is used for the fin formula field effect transistor for constituting area to be measured 210, described
Diode doped region is used for the diode for constituting external zones 220.When the fin field effect crystalline substance in area to be measured 210
When body pipe works, the heat produced in the fin 201 in area to be measured 210 is transferred to easily by carrier
In the fin 201 of external zones 220 such that it is able to which the heat monitored in fin 201 in external zones 220 is passed
Pass trend and change.
201 quantity of fin in the external zones 220 be more than or equal to 1, and, the external zones 220
Interior part fin 201 extends from area to be measured 210.When the fin 201 in external zones 220 is counted
When amount is more than 1, some fins 201 of external zones 220 are parallel to each other, and the fin in external zones 220
201 are parallel to each other with the fin 201 in area to be measured 210.In the present embodiment, in the external zones 220
The fin 201 that surrounds in area to be measured 210 of fin 201, then by area to be measured 210 fin 201 from inside to outside
The heat for enclosing the transmission of 220 fin of area 201 is distributed in around the area to be measured 210, to be formed so as to pass through
Test structure, heat distribution that can be around Overall Acquisition area to be measured 210 and transmit situation.
In the present embodiment, the width at the top of the fin 201 is less than 20 nanometers, such as 14 nanometers；
In the area to be measured 210 and external zones 220, the distance between adjacent fin 201 is 50 nanometers～60
Nanometer.Due to the distance between adjacent fin 201 it is less, and width dimensions at the top of the fin 201
It is less so that heat is more easy to the accumulation in fin 201, and being more easy between fin 201 occurs heat
Transmission.
In the present embodiment, the forming step of the substrate 200 and fin 201 includes：Quasiconductor is provided
Substrate；The semiconductor base is etched, and some grooves, adjacent trenches is formed in the semiconductor base
Between semiconductor base form fin 201, the semiconductor base positioned at fin 201 and channel bottom formed
Substrate 200.The Semiconductor substrate is monocrystalline substrate, single-crystal germanium substrate, silicon-Germanium substrate or carborundum lining
Bottom, is monocrystalline substrate in the present embodiment.
In one embodiment, the well region can in etching semiconductor substrate with before forming fin 201,
Using in ion implantation technology formation and semiconductor base；It is after the semiconductor base is etched, described
Well region is located in formed substrate 200 and fin 201.
In another embodiment, the well region can after etching semiconductor substrate is to form fin 201,
Using ion implantation technology formed with the substrate 200 and fin 201 in.
In another embodiment, the forming step of the fin 201 includes：Using epitaxy technique in substrate
200 surfaces form fin layer；The fin layer is etched, and some grooves is formed in the fin layer, it is adjacent
Fin layer between groove forms fin 201.The substrate 200 is silicon substrate, silicon-Germanium substrate, carborundum
Substrate, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or III-V substrate,
Such as gallium nitride substrate or gallium arsenide substrate etc..The material of the fin layer is silicon, germanium, carborundum or silicon
Germanium.
In one embodiment, after the fin layer is etched to form fin 201, using ion implanting
Technique forms well region in the substrate 200 and fin 201.
In one embodiment, the fin formula field effect transistor for being formed in the area to be measured 210 is that PMOS is brilliant
Body pipe, the dopant ion in the well region are N-type ion, subsequently in the diode of the formation of external zones 220
Dopant ion in doped region is p-type ion.
In another embodiment, the fin formula field effect transistor for being formed in the area to be measured 210 is NMOS
Transistor, the dopant ion in the well region are p-type ion, subsequently in two poles of the formation of external zones 220
Dopant ion in pipe doped region is N-type ion.
Fig. 5 being refer to, sealing coat 202 being formed on 200 surface of the substrate, the sealing coat 202 is covered
The partial sidewall surface of the fin 201.
The sealing coat 202 is used to isolate adjacent fin 201.The material of the sealing coat 202 is oxidation
Silicon, silicon nitride, silicon oxynitride, low-K dielectric material (dielectric constant more than or equal to 2.5, less than 3.9),
One or more combination in ultralow K dielectric materials (dielectric constant is less than 2.5).In the present embodiment, institute
The material for stating sealing coat 202 is silicon oxide.
The forming step of the sealing coat 202 includes：Formed in the substrate 200 and 201 surface of fin
Isolating membrane；The isolating membrane is planarized till the top surface of the fin 201 is exposed；Flat
After the smoothization isolating membrane, the isolating membrane is etched back to, exposes the sidewall surfaces of part fin 201,
Form sealing coat 202.
Refer to Fig. 6 and Fig. 7, Fig. 7 is cross-sectional views of the Fig. 6 along BB ' directions, is developed across
The first grid structure 211 of fin 201 in area to be measured 210, the first grid structure 211 are located to be measured
The partial sidewall and top surface of 210 fin 201 of area；In 211 both sides fin 201 of first grid structure
Interior formation source-drain area 212；Some diode doped regions 221 are formed in 220 fin 201 of external zones, if
Dry diode doped region 221 surrounds the area to be measured 210, some diodes in same fin 201
Doped region 221 is mutually discrete, and the diode doped region 221 is mutually discrete with the source-drain area 212.
It should be noted that Fig. 6 is the structural representation for ignoring the first sub- dielectric layer 203 and source-drain area 212
Figure.
Also include in the present embodiment：The second grid structure 222 of fin 201 in external zones 220 is developed across,
The partial sidewall and top surface of 222 peripherally located area of second grid structure, 220 fin 201, if
Do the second grid structure 222 parallel, the second grid structure 222 and first grid structure 211
It is parallel.
The second grid structure 222 is formed in the manufacturing process for forming first grid structure 211 simultaneously.
The second grid structure 222 is used for as the mask for forming some discrete diode doped regions 221,
So as to avoid the step of being additionally formed mask layer, the step of manufacturing process can not only be reduced, Er Qieneng
Enough make between the size and neighboring diode doped region 221 of formed diode doped region 221 away from
From more accurate.
In other embodiments, additionally it is possible to not in the formation second grid structure of the external zones 220, institute
State diode doped region 221 to be formed in the fin 201 of external zones 220 by mask of patterned layer.Institute
State patterned layer can for patterned photoresist layer, hard mask layer, self assembly patterned layer or other cover
Film layer
The quantity of the first grid structure 211 is more than or equal to 1, and each first grid structure 211
Across one or some fin 201 arranged in parallel.In the present embodiment, the first grid structure
211 quantity is 1, and the first grid structure 211 is across 4 fins 201 in area to be measured 210.
In other embodiments, the first grid number of structures in the area to be measured is more than 1, then some first
Grid structure is arranged in parallel.
The second grid structure 222 is across one or some fin 201 arranged in parallel.In this enforcement
In example, fin 201 of the second grid structure 222 across some external zones 220.
As at least one fin 201 in the area to be measured 210 extends to external zones 220, and, at least
One extends to 201 surface of fin of external zones 220 from area to be measured 210 while being crossed with first grid knot
Structure 211 and second grid structure 222, and 201 surface of same fin is located at first grid structure 211
222 quantity of second grid structure is more than or equal to 1.
Due to positioned at 201 surface of same fin first grid structure 211 and second grid structure 222 it
Between share same source-drain area 212, heat in the fin 201 in area to be measured 210 can be enable to pass through current-carrying
The migration of son is transferred in the fin 201 of external zones 220 from the source-drain area 212 for sharing.
In the present embodiment, the first grid structure 211 and second grid structure 222 are high k metals
Grid structure (High-K Metal Gate, abbreviation HKMG), therefore, the first grid structure 211
Formed using rear grid technique (Gate Last) with second grid structure 222.
The forming step of first grid structure 211 and second grid structure 222 includes：It is developed across to be measured
First dummy gate structure of fin 201 in area 210, first dummy gate structure are located at area to be measured 210
The partial sidewall and top surface of fin 201, first dummy gate structure include dummy gate layer；Formed
Across some second dummy gate structures of fin 201 in external zones 220, the second dummy gate structure position
In the partial sidewall and top surface of 220 fin 201 of external zones, some second dummy gate structures are put down
OK, second dummy gate structure is parallel with the first dummy gate structure, and second dummy gate structure includes
Dummy gate layer；In the sealing coat 202 and 201 surface of fin and the first dummy gate structure and second
The sidewall surfaces of dummy gate structure form the first sub- dielectric layer 203, and the first sub- dielectric layer 203 exposes
The top surface of the dummy gate layer；The dummy gate layer is removed, is formed in the first sub- dielectric layer 203
Gate openings；Gate dielectric layer is formed in the inner wall surface of the gate openings；On the gate dielectric layer surface
Form the grid layer of the full gate openings of filling；The gate dielectric layer and grid layer are planarized until exposure
Till going out 203 surface of the described first sub- dielectric layer, first grid structure 211 is formed in area to be measured 210,
External zones 220 forms second grid structure 222.
The first grid structure 211 for being formed includes：Positioned at 201 partial sidewall of fin and top surface
Gate dielectric layer, the grid layer positioned at gate dielectric layer surface and it is located at grid layer and gate dielectric layer side wall table
The side wall in face.The second grid structure 222 for being formed includes：Positioned at 201 partial sidewall of fin and top
The gate dielectric layer on surface, the grid layer positioned at gate dielectric layer surface and it is located at grid layer and gate dielectric layer
The side wall of sidewall surfaces.
In the present embodiment, first dummy gate structure and the second dummy gate structure are formed simultaneously.At which
In its embodiment, first dummy gate structure and the second dummy gate structure successively can also be formed.
The material of the dummy gate layer is polysilicon, and the dummy gate layer is for the gate medium to be subsequently formed
Layer and grid layer take up space position.In the present embodiment, first dummy gate structure and the second pseudo- grid
Pole structure includes：Positioned at the side wall of dummy gate layer sidewall surfaces；The material of the side wall is silicon oxide, nitrogen
One or more combination in SiClx and silicon oxynitride.The side wall is used to define the dummy gate layer and source
Relative position and distance between drain region 212 or diode doped region 221.
In the present embodiment, also there is pseudo- gate dielectric layer between the dummy gate layer and fin 201；It is described
The material of pseudo- gate dielectric layer is silicon oxide, formation process is oxidation technology；The pseudo- gate dielectric layer for
When subsequently removing the dummy gate layer, the side wall and top surface that fin 201 exposes is protected from damage.
In the present embodiment, the dummy gate layer of area to be measured 210 and external zones 220 is removed, then described
Gate dielectric layer and grid layer are respectively formed in the gate openings of area to be measured 210 and external zones 220, then it is described to treat
The material for surveying the gate dielectric layer of area 210 and external zones 220 is high K medium material, the material of the grid layer
Material includes metal or metallic compound.
The formation process of the gate dielectric layer can be atom layer deposition process, the material of the gate dielectric layer
For high K medium material；The high K medium material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, oxidation
Lanthanum, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, Barium monoxide titanium, strontium oxide titanium or oxidation
Aluminum.The material of the grid layer includes metal or metallic compound.The material of the grid layer be metal and
One or more combination in metallic compound；The material of the grid layer includes copper, tungsten, aluminum or silver；
The material of the grid layer can also include the one kind in tantalum, titanium, tantalum nitride, titanium nitride, titanium-aluminium alloy
Or multiple combination.
In another embodiment, the dummy gate layer in only area to be measured 210 is removed, and in the gate openings
Interior formation gate dielectric layer and grid layer；The material of the gate dielectric layer of the area to be measured 210 and external zones 220
For high K medium material, the material of the grid layer includes metal or metallic compound.And it is described second pseudo-
Grid layer is retained, and second dummy gate structure is i.e. as second grid structure 222；Then the pseudo- grid are situated between
Gate dielectric layer of the matter layer as second grid structure 222, the dummy gate layer is used as second grid structure 222
Grid layer, i.e. the gate dielectric layer material of the second grid structure 222 is silicon oxide；The grid layer
Material be polysilicon.
In the present embodiment, after the first dummy gate structure and the second dummy gate structure is formed, form the
Before one sub- dielectric layer 203, also include：The shape in the fin 201 of the first dummy gate structure both sides
Into source-drain area 212；A diode is formed in fin 201 between adjacent second grid structure 222 to mix
Miscellaneous area 221.
In the present embodiment, the source-drain area 212 and the diode doped region 221 are included positioned at fin
There is in stressor layers in 201, the stressor layers dopant ion.In one embodiment, the fin for being formed
When field-effect transistor is PMOS transistor, the material of the stressor layers is SiGe, and it is described adulterate from
Son is p-type ion, and the stressor layers are for the channel region offer compressive stress in fin 201.Another
In embodiment, when the fin formula field effect transistor for being formed is nmos pass transistor, the material of the stressor layers
Expect for carborundum, and the dopant ion is N-type ion, the stressor layers are for into fin 201
Channel region provides tension.
In other embodiments, the fin formula field effect transistor for being formed is PMOS transistor or NMOS
Transistor, the material of the stressor layers can also be monocrystal silicon, and the stressor layers are only used for raising to be formed
212 surface of source-drain area.
In one embodiment, the diode doped region 221 is formed at adjacent using ion implantation technology
In fin 201 between two grid structures 222, the second grid structure 222 is noted as the ion
Enter the mask of technique, so as to the mask for ion implantation technology need not be additionally formed, reduce processing step,
And make the positions and dimensions of the diode doped region 221 more accurate.
Dopant ion type in the well region is different from the dopant ion type of diode doped region 221；
When the dopant ion in the well region is p-type ion, the dopant ion of the diode doped region 221
For N-type ion；When the dopant ion in the well region is N-type ion, the diode doped region 221
Dopant ion be p-type ion.The diode doped region 221 and well region constitute diode, and,
As, in the fin 201 of external zones 220, some diode doped regions 221 are mutually discrete, i.e. institute
Some diodes are formed with the fin for stating external zones 220.
It is additionally, since at least one fin, 201 two ends in the area to be measured 210 and extends to external zones 220
It is interior so that at least one diode doped region 221 is located in same fin 201, then with source-drain area 212
Heat produced by the fin 201 in the area to be measured 210 can to the periphery in the fin 201 in area 220
Transmission.Also, due to the forward conduction voltage of diode it is linear with the temperature of diode doped region 221
Relation, therefore, by the forward conduction voltage for detecting each diode, each diode doped region can be obtained
221 temperature, so as to be monitored to 201 temperature of fin of external zones 220.
The first sub- dielectric layer 203 is used to retain first dummy gate structure and the second dummy gate structure
Shape and position, subsequently to substitute the dummy gate layer with gate dielectric layer and grid layer.
The forming step of the first sub- dielectric layer 203 includes：In 202 surface of the sealing coat, fin
201 side wall and top surface, the first dummy gate structure and the second dummy gate structure surface form deielectric-coating；
The deielectric-coating is planarized till the top surface of the dummy gate layer is exposed, described first is formed
Sub- dielectric layer 203.
The flatening process is CMP process.In the present embodiment, the external zones 220
The second dummy gate structure for being formed can also be used to the device density for improving external zones 220, for described
Barrier effect is played in CMP process, it is to avoid the first sub- dielectric layer 203 that external zones 220 is formed
Surface indentation.
The forming step of the deielectric-coating is chemical vapor deposition method, physical gas-phase deposition or atom
Layer depositing operation.The material of the first sub- dielectric layer 203 be silicon oxide, silicon nitride, silicon oxynitride,
Low k dielectric materials (dielectric coefficient be more than or equal to 2.5, less than 3.9, for example porous silica or
Porous silicon nitride) or ultra-low k dielectric material (dielectric coefficient is less than 2.5, such as porous SiC OH).
In the present embodiment, the material of the described first sub- dielectric layer 203 is silicon oxide；The deielectric-coating
Formation process is fluid chemistry vapour deposition (Flowable Chemical Vapor Deposition, abbreviation
FCVD) technique, high-density plasma deposition (High Density Plasma, abbreviation HDP) technique,
One or more in plasma enhanced deposition technique.
Fig. 8 is refer to, and second is formed in the first grid structure 211 and 203 surface of the first sub- dielectric layer
Sub- dielectric layer 204.
The first sub- dielectric layer 203 and the second sub- dielectric layer 204 are constituted positioned at sealing coat 202, fin
201 and the dielectric layer on 211 surface of first grid structure.
The forming step of the second sub- dielectric layer 204 is chemical vapor deposition method, physical vapour deposition (PVD)
Technique or atom layer deposition process.The material of the second sub- dielectric layer 204 be silicon oxide, silicon nitride,
(dielectric coefficient is such as porous more than or equal to 2.5, less than 3.9 for silicon oxynitride, low k dielectric materials
Silicon oxide or porous silicon nitride) or ultra-low k dielectric material (dielectric coefficient be less than 2.5, such as porous
SiCOH)。
In the present embodiment, the material of the described second sub- dielectric layer 204 is silicon oxide；Second son is situated between
The formation process of matter layer 204 is chemical vapor deposition method, physical gas-phase deposition or ald
Technique；Chemical vapor deposition method includes high-density plasma deposition (High Density Plasma, abbreviation
HDP) technique or plasma enhanced deposition technique.
Refer to Fig. 9 and Figure 10, Figure 10 is cross-sectional views of the Fig. 9 along BB ' directions, described
221 surface of diode doped region forms the first conductive structure 223, and first conductive structure 223 is across extremely
A few fin 201.
It should be noted that Fig. 9 is to ignore the first sub- dielectric layer 203, the second sub- dielectric layer 204 and source and drain
The structural representation in area 212.
In the present embodiment, first conductive structure 223 be formed at adjacent second grid structure 222 it
Between the second sub- dielectric layer 204 and the first sub- dielectric layer 203 in, and first conductive structure 223
In 212 surface of source-drain area；I.e. described first conductive structure 223 be located at the dielectric layer in, and run through institute
State dielectric layer.First conductive structure 223 can be to two poles between adjacent second grid structure 222
Pipe doped region 221 is biased.
First conductive structure 223 across at least one fin 201, then first conductive structure 223
In addition to positioned at 212 surface of source-drain area, the sidewall surfaces and part for being also located at part fin 201 are isolated
202 surface of layer.In the present embodiment, each first conductive structure 223 is across a fin 201.
In the present embodiment, it is additionally included in 212 surface of the source-drain area and forms the 3rd conductive structure 206, institute
The 3rd conductive structure 206 is stated across at least two articles fins 201.3rd conductive structure 206 can be to
The source-drain area 212 of one grid structure, 211 both sides is biased.
In the present embodiment, it is additionally included in well region surface and forms the second conductive structure 205, described second is conductive
Structure 205 is for being biased to well region.Second conductive structure 205 is across at least one fin 201.
Second conductive structure 205 is formed at 230 surface of interconnecting area, and second conductive structure 205
In side wall and top surface and 202 surface of part sealing coat of part fin 201；Described second leads
The quantity of electric structure 205 is more than or equal to 1；When the quantity of second conductive structure 205 is more than 1,
Some second conductive structures 205 are arranged in parallel.
In other embodiments, also include：The 4th is formed at the top of part first grid structure 211 to lead
Electric structure.4th conductive structure is for being biased to the grid layer of first grid structure 211.
In the present embodiment, first conductive structure 223, the second conductive structure 205 and the 3rd conductive knot
Structure 206 is formed simultaneously.First conductive structure 223, the second conductive structure 205 and the 3rd conductive structure
206 forming step includes：Using etching technics in 220 adjacent first grid of area to be measured 210 and external zones
Between structure 211 and second grid structure 222, and adjacent second grid structure 222 between
One sub- dielectric layer 203 and the second sub- dielectric layer 204 form groove, and the groove exposes part source-drain area
212 surfaces, 221 surface of diode doped region, the sidewall surfaces of part fin 201 and part isolate
202 surface of layer；Conductive material is filled in 204 surface of the described second sub- dielectric layer and the groove；It is right
The conductive material carries out planarization until exposing the described second sub- dielectric layer 204, forms described.
The conductive material includes the one kind or many in copper, tungsten, aluminum, titanium, tantalum, titanium nitride and tantalum nitride
Plant combination；The formation process of the conductive material includes chemical vapor deposition method, physical vapour deposition (PVD) work
Skill, atom layer deposition process, electroplating technology or chemical plating process.
Accordingly, the embodiment of the present invention also provides a kind of test structure formed by employing said method, please
With continued reference to Fig. 9 and Figure 10, including：Substrate 200, the substrate 200 include area to be measured 210 and bag
Enclose 200 table of substrate of the external zones 220 in the area to be measured 210, the area to be measured 210 and external zones 220
Face has some fins 201 of at least one fin 201, the area to be measured 210 and external zones 220 respectively
It is parallel to each other, the two ends of 210 at least one fin 201 of the area to be measured extend to the external zones 220
It is interior；Well region in the fin 201 and substrate 200 of area to be measured 210 and external zones 220；Positioned at institute
The sealing coat 202 on 200 surface of substrate is stated, the sealing coat 202 covers the partial sidewall of the fin 201
Surface；Across the first grid structure 211 of fin 201 in area to be measured 210, the first grid structure
211 partial sidewalls and top surface for being located at 210 fin 201 of area to be measured；Positioned at first grid structure 211
Source-drain area 212 in both sides fin 201；Some diode doping in 220 fin 201 of peripherally located area
Area 221, some diode doped regions 221 surround the area to be measured 210, in same fin 201
Some diode doped regions 221 are mutually discrete, and the diode doped region 221 and the source-drain area 212
It is mutually discrete；Positioned at first conductive structure 223 on 221 surface of diode doped region, described first leads
Electric structure 223 is across at least one fin 201.
Illustrate below with reference to accompanying drawing.
In the present embodiment, also include：Across the second grid structure 222 of fin 201 in external zones 220,
The partial sidewall and top surface of 222 peripherally located area of second grid structure, 220 fin 201, if
Do the second grid structure 222 parallel, the second grid structure 222 and first grid structure 211
It is parallel.
There is a diode doped region 221 in fin 201 between adjacent second grid structure 222.Institute
Second grid structure 222 is stated across one or some fin 201 arranged in parallel；In the present embodiment,
The second grid structure 222 is across a fin 201.
The second grid structure 222 includes：Grid positioned at 201 partial sidewall of fin and top surface are situated between
Matter layer, the grid layer positioned at gate dielectric layer surface and positioned at grid layer and gate dielectric layer sidewall surfaces
Side wall.
In the present embodiment, the material of the gate dielectric layer of the second grid structure 222 is high K medium material
Material；The material of the grid layer includes metal or metallic compound.In another embodiment, the grid are situated between
The material of matter layer is silicon oxide；The material of the grid layer is polysilicon.
The first grid structure 211 includes：Grid positioned at 201 partial sidewall of fin and top surface are situated between
Matter layer, the grid layer positioned at gate dielectric layer surface and positioned at grid layer and gate dielectric layer sidewall surfaces
Side wall.In the present embodiment, the material of the gate dielectric layer of the first grid structure 211 is high K medium
Material；The material of the grid layer includes metal or metallic compound.
First conductive structure 223 is also located at portion in addition to positioned at 221 surface of diode doped region
Divide 202 surface of sidewall surfaces and part sealing coat of fin 201.Well region surface is also with the second conductive knot
Structure 205, second conductive structure 205 is across at least one fin 201；In the present embodiment, it is described
Second conductive structure 205 is across a fin 201.212 surface of the source-drain area is also with the 3rd conductive knot
Structure 206, the 3rd conductive structure 206 is across at least two articles fins 201；In the present embodiment, it is described
3 article fins 201 of 3rd conductive structure 206 across area to be measured 211.
In the present embodiment, also include：Positioned at sealing coat 202, fin 201 and first grid structure 211
The dielectric layer on surface；First conductive structure 223 be located at the dielectric layer in, and run through the medium
Layer.
Dopant ion type in the well region is different from the dopant ion type of diode doped region 221；
When the dopant ion in the well region be p-type ion when, the doping in the diode doped region 221 from
Son is N-type ion；When the dopant ion in the well region is N-type ion, the diode doped region
Dopant ion in 221 is p-type ion.
In the area to be measured 210, the quantity of the first grid structure 211 is more than or equal to 1,
And each first grid structure 211 is across one or some fin 201 arranged in parallel.When described to be measured
When 211 quantity of first grid structure in area 210 is more than 1, some 211 parallels of first grid structure
Row.
As the two ends of 210 at least one fin 201 of the area to be measured are extended in the external zones 220,
Therefore, at least one diode doped region 221 is located in same fin 201 with source-drain area 212.By institute
The heat stated produced by the channel region between source-drain area 212 and source-drain area 212 can be from the fin 201
It is transferred in external zones 220；And the well region of external zones 220 constitutes diode with diode doped region 221,
By the forward conduction voltage for detecting the diode, the temperature of the diode can be obtained.Therefore, lead to
The test structure of the present embodiment is crossed, can be to the Temperature Distribution in 220 fin 201 of external zones and change
Trend is monitored.
Accordingly, the embodiment of the present invention also provides a kind of method of testing carried out using above-mentioned test structure,
Refer to Fig. 9, Figure 10 and Figure 11.Figure 11 is the method for testing schematic flow sheet of the embodiment of the present invention,
The method of testing of the present embodiment includes：
Step S1, there is provided test structure as shown in Figure 9 and Figure 10, the first grid structure 211
And one group of source-drain area 212 positioned at 211 both sides of first grid structure constitutes test transistor, described two
Pole pipe doped region 221 and well region constitute a diode, and the area to be measured 210 is to be measured with least one
Transistor, the external zones 220 have some diodes.
Step S2, opens the test transistor and diode.
The channel region that the first transistor is opened in 211 bottom fin 201 of first grid structure is opened,
Even if opening the diode diode forward conducting.
In the area to be measured 210, after the channel region of 211 bottom of first grid structure is opened,
There is electric current so that 201 spontaneous heating of fin in area to be measured 210 in the channel region.Due to described to be measured
201 two ends of fin in area 210,220 interior extension of area to the periphery, then in 210 fin 201 of the area to be measured
Heat can be delivered in the fin 201 of external zones 220 by well region.Therefore, the area to be measured 210
Heat in fin 201 is capable of the fin 201 in area 220 to the periphery and is transmitted so that 220 fin of external zones
201 diverse location temperature is changed over.
Step S3, after the test transistor and diode is opened, at interval of preset time period after,
Some diodes are carried out with a temperature test, the temperature of some diode doped regions 221 is obtained.
As external zones 220 has some diodes, and the diode is uniformly distributed in area to be measured 210
Around, therefore by temperature test being carried out to each diode respectively, can obtain the diode place fin
The temperature in portion 201；Then obtain the temperature of diverse location in 220 some fins 201 of external zones.
The step of temperature test, includes：The forward conduction voltage of some diodes is detected；It is logical
The linear relationship crossed between 201 temperature of diode forward conducting voltage and fin, obtains diode doped region
221 temperature.
Due to the forward conduction voltage of the diode it is linear with the temperature of diode doped region 221,
The temperature of the diode doped region 221 is higher, and the forward conduction voltage of the diode is higher.
Therefore, by obtaining the forward conduction voltage of each transistor seconds, i.e., place two can be calculated
The temperature of pole pipe doped region 221.So as to obtain current time, some diode doping in external zones 220
The temperature in area 221, thus obtains the temperature point state in 220 fin 201 of external zones；For example, can
Draw out in current time, the isollaothermic chart of 220 some fins 201 of external zones.
Step S4, after temperature test several times is carried out to some diodes, obtains 220 fin of external zones
Temperature in portion 201 relation information over time.
Specifically, obtain in 220 some fins 201 of external zones, the temperature of diverse location is changed over
And the change for producing, speed that the temperature of such as each diverse location fin 201 is raised and lowered etc..Cause
This, passes through formed test structure and is tested, can monitor in external zones 220 distribution of heat and
Situation of change, can be improved to semiconductor device based on this.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (19)
1. a kind of test structure, it is characterised in that include：
Substrate, the substrate include area to be measured and surround the external zones in the area to be measured, the area to be measured and
The substrate surface of external zones has some fins of at least one fin, the area to be measured and external zones respectively
It is parallel to each other, the two ends of at least one fin of area to be measured are extended in the external zones；
Well region in the fin and substrate of area to be measured and external zones；
Positioned at the sealing coat of the substrate surface, the sealing coat covers the partial sidewall surface of the fin；
Across the first grid structure of fin in area to be measured, the first grid structure is located at area's fin to be measured
Partial sidewall and top surface；
Source-drain area in the fin of first grid structure both sides；
Some diode doped regions in peripherally located area's fin, some diode doped regions surround described in treat
Area is surveyed, some diode doped regions in same fin are mutually discrete, and the diode doped region
It is mutually discrete with the source-drain area；
Positioned at first conductive structure on the diode doped region surface, first conductive structure is across extremely
A few fin.
2. test structure as claimed in claim 1, it is characterised in that also include：Across fin in external zones
Second grid structure, the partial sidewall and top table of the peripherally located area's fin of the second grid structure
Face, some second grid parallelism structurals, the second grid structure and first grid parallelism structural.
3. test structure as claimed in claim 2, it is characterised in that the fin between adjacent second grid structure
There is in portion a diode doped region.
4. test structure as claimed in claim 2, it is characterised in that the second grid structure is across
Or some fins arranged in parallel.
5. test structure as claimed in claim 2, it is characterised in that the second grid structure includes：Position
Gate dielectric layer in fin partial sidewall and top surface, the grid layer positioned at gate dielectric layer surface, with
And positioned at grid layer and the side wall of gate dielectric layer sidewall surfaces.
6. test structure as claimed in claim 5, it is characterised in that the material of the gate dielectric layer is oxidation
Silicon；The material of the grid layer is polysilicon.
7. test structure as claimed in claim 1, it is characterised in that the first grid structure includes：Position
Gate dielectric layer in fin partial sidewall and top surface, the grid layer positioned at gate dielectric layer surface, with
And positioned at grid layer and the side wall of gate dielectric layer sidewall surfaces.
8. the test structure as described in claim 5 or 7, it is characterised in that the material of the gate dielectric layer is
High K medium material；The material of the grid layer includes metal or metallic compound.
9. test structure as claimed in claim 1, it is characterised in that also include：Positioned at the of well region surface
Two conductive structures, second conductive structure is across at least one fin.
10. test structure as claimed in claim 1, it is characterised in that also include：Positioned at the source-drain area table
3rd conductive structure in face, the 3rd conductive structure is across at least two articles fins.
11. test structures as claimed in claim 1, it is characterised in that the dopant ion type in the well region
It is different from the dopant ion type of diode doped region.
12. test structures as claimed in claim 1, it is characterised in that in the area to be measured, described first
The quantity of grid structure is more than or equal to 1, and each first grid structure is across one or some
Fin arranged in parallel.
13. test structures as claimed in claim 12, it is characterised in that the first grid in the area to be measured
When number of structures is more than 1, some first grid parallelism structural arrangements.
14. test structures as claimed in claim 1, it is characterised in that at least one diode doped region and source
Drain region is located in same fin.
15. test structures as claimed in claim 1, it is characterised in that also include：Positioned at sealing coat, fin
With the dielectric layer of first grid body structure surface；First conductive structure be located at the dielectric layer in, and
Through the dielectric layer.
16. test structures as claimed in claim 1, it is characterised in that first conductive structure is also located at portion
Divide the sidewall surfaces and part insulation surface of fin.
17. a kind of forming methods of test structure, for forming the test as described in any one of claim 1 to 16
Structure, it is characterised in that include：
Substrate is provided, the substrate includes area to be measured and surrounds the external zones in the area to be measured, described to be measured
The substrate surface of area and external zones is some with least one fin, the area to be measured and external zones respectively
Fin is parallel to each other, and the two ends of at least one fin of area to be measured are extended in the external zones；
Well region is formed in the fin and substrate of the area to be measured and external zones；
Sealing coat is formed in the substrate surface, the sealing coat covers the partial sidewall surface of the fin；
The first grid structure of fin in area to be measured is developed across, the first grid structure is located at area to be measured
The partial sidewall and top surface of fin；
Source-drain area is formed in the fin of first grid structure both sides；
Form some diode doped regions in external zones fin, some diode doped regions surround described in treat
Area is surveyed, some diode doped regions in same fin are mutually discrete, and the diode doped region
It is mutually discrete with the source-drain area；
The first conductive structure is formed on the diode doped region surface, first conductive structure is across extremely
A few fin.
18. a kind of method of testings, it is characterised in that include：
Test structure as described in any one of claim 1 to 16 is provided, the first grid structure and
One group of source-drain area positioned at first grid structure both sides constitutes test transistor, the diode doped region and
Well region constitutes a diode, and the area to be measured has at least one test transistor, the external zones tool
There are some diodes；
Open the test transistor and diode；
After the test transistor and diode is opened, at interval of preset time period after, to some
Diode carries out a temperature test, obtains the temperature of some diode doped regions；
After temperature test several times is carried out to some diodes, obtain external zones fin in temperature with
The variation relation information of time.
19. method of testings as claimed in claim 18, it is characterised in that include the step of the temperature test：
The forward conduction voltage of some diodes is detected；By diode forward conducting voltage and fin
Linear relationship between temperature, obtains the temperature of diode doped region.
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| CN108107059A (en) * | 2017-11-16 | 2018-06-01 | 上海华力微电子有限公司 | A kind of detection structure and detection method of contact hole bottom tungsten bolt defect |
| CN110620056A (en) * | 2018-06-18 | 2019-12-27 | 三星电子株式会社 | Method for detecting failure of semiconductor device |
| WO2023197400A1 (en) * | 2022-04-12 | 2023-10-19 | 长鑫存储技术有限公司 | Semiconductor layout structure and semiconductor test structure |
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| CN106560909B (en) | 2019-05-28 |
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