CN104391819A - Network interconnection architecture of multi-level and multi-processing unit reconfigurable array - Google Patents
Network interconnection architecture of multi-level and multi-processing unit reconfigurable array Download PDFInfo
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- CN104391819A CN104391819A CN201410653241.6A CN201410653241A CN104391819A CN 104391819 A CN104391819 A CN 104391819A CN 201410653241 A CN201410653241 A CN 201410653241A CN 104391819 A CN104391819 A CN 104391819A
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Abstract
The invention relates to the technical field of integrated circuits, and provides a device for realizing a reconfigurable processing unit array. The device has the advantages that at the premise of guaranteeing the data interaction rate, the interconnection flexibility is furthest improved, the number of interconnection lines is reduced, and the power consumption is decreased. The device adopts the technical scheme that a network interconnection architecture of a multi-level and multi-processing unit reconfigurable array comprises a three-level interconnection architecture, namely that for first level of interconnection, the two-dimensional mesh network connection is adopted; for second level of interconnection, the second level of interconnection is realized on the basis of direct data interaction of the adjacent processing units, every four reconstruction processing units are connected with a switch box, and the data interaction of every two of the four reconstruction processing units is realized through the corresponding switch box; for the third level of interconnection, the connection of the two-dimensional mesh network between the switch boxes is adopted. The device is mainly applied to the design and production of the integrated circuits.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of interconnection structure for reconfigurable processing array.
Technical background
Reconfigurable arrays is a kind of processor by certain interconnection mode, different algorithms being carried out to parallel processing by the processing unit of some.Design cycle compared to traditional ASIC is long, design cost is high and can not the making full use of algorithm concurrency and can only realize instruction level parallelism of its specificity and general processor, and reconfigurable processor has and well can balance in performance, dirigibility and cost etc.Processor based on reconfigurable arrays can solve the matching problem that array scale and algorithm calculate scale easily, can realize block level and the operation of grand level concurrence performance more flexibly.Meanwhile, the processor based on reconfigurable arrays simplifies the control difficulty of data stream, and its memory access cost is more much smaller than the processor based on instruction, and has same versatility, with the obvious advantage.
The reconfigurable processing unit array of current main flow adopts the point-to-point overall situation to be connected with the mode of part interconnection mostly, the globally interconnected data interaction can carried out fast between any processing unit, but too much interconnection line causes the increase of array area and the loss of power consumption.Part interconnects, and is that the array element of part in array interconnects, reduce interconnections and then reduce power consumption and area, but part interconnection makes Algorithm mapping difficulty increase, this is because will consider whether can interconnect between processing unit in Algorithm mapping process, thus determine mapping scheme.Part interconnection generally has two-dimensional network to interconnect, two-dimensional network interconnects and adjacent processing units interconnection between row/column, two-dimensional network interconnection and row/column between adjacent processing units interconnection and row/column between processing unit totally interconnected, chessboard distance is the processing unit interconnection etc. of 2.
In sum, no matter the overall situation of employing or part interconnection all belong to point-to-point interconnection and have certain drawback.
Summary of the invention
In order to overcome the deficiencies in the prior art, providing the device realizing reconfigurable processing unit array, realizing the dirigibility of interconnection under the prerequisite of data interaction speed can be ensured to greatest extent and reducing interconnection line number, reduce power consumption.For this reason, the technical scheme that the present invention takes is, the network interconnection architecture of the reconfigurable arrays of multistage multiplied unit, comprises three grades of interconnect architecture:
The first order interconnects: two-dimentional mesh network connects, and namely adjacent processing unit directly can carry out data interaction;
The second level interconnects: second-level interconnect can be carried out in the basis of direct interaction in adjacent processing units data, namely every 4 reconfigurable processing units are connected with a switch enclosure, carried out the data interaction of any two by switch enclosure between these 4 basic processing units, the data interaction can being undertaken based on switch enclosure by 3 kinds of modes between 4 processing units: by switch enclosure, each reconfigurable processing unit can both carry out data interaction with other three processing units;
Third level interconnection is the connection of the two-dimentional mesh network between switch enclosure.
Third level interconnection is the connection of two-dimentional mesh network between switch enclosure is be achieved by the switch enclosure port increased in the interconnection of the second level, being specially switch enclosure port number is n+4, except being connected with 4 reconfigurable processing units, all the other ports are connected with peripheral switch box, form switch enclosure two dimension mesh network.
Each switch enclosure port is 6 or 8, and wherein 4 ports are used for being connected with 4 reconfigurable processing units, and 2 or 4 correspondences of remainder are connected with 2 of surrounding or 4 switch enclosures, forms switch enclosure two dimension mesh network.
Compared with the prior art, technical characterstic of the present invention and effect:
The mode that two-dimentional mesh network interconnection of the present invention and two kinds of logic interconnection structures of switch enclosure combine can make the interconnection of whole reconfigurable arrays can be configured according to the different of algorithm, make its dirigibility and quite totally interconnected, but interconnection line number greatly reduces, and the mode that two kinds of logic interconnection structures combine can continue to run for cost to reduce system performance when in reconfigurable arrays, certain paths breaks down, makes the stability of whole reconfigurable array structure greatly improve.
Accompanying drawing explanation
The two-dimentional mesh cellular logic interconnection structure of Fig. 1 16 reconfigurable processing units.
Fig. 24 logic interconnection structures between processing unit and switch enclosure.
Fig. 34 port switch box schematic diagram (represented by dotted arrows switch enclosure, solid line is institute's likely connected mode, and in figure, line is non-intersect between two).
3 kinds of modes (dotted line is switch enclosure, and in figure, line is non-intersect between two) that the processing unit that Fig. 4 is connected with same switch enclosure is connected by switch enclosure.
The connected mode (dotted line is switch enclosure, and under often kind of configuration, port interconnects between two to have 4 paths to ensure at the most, and in figure, line is non-intersect between two) of each port of Fig. 58 port switch box.
The reconfigurable arrays logic interconnection structure of Fig. 6 16 processing units.
Embodiment
The present invention is the multiplied unit reconfigurable arrays logic interconnection structure be combined with switch enclosure based on two-dimentional mesh network.As shown in Figure 1, we are for 4x4 array here, but this invention is not only limited to this size, and it can be applicable to the two-dimentional mesh network architecture of arbitrary dimension.
In the present invention, first reconfigurable processing unit array carries out level interconnect, and two-dimentional mesh network connects, and namely adjacent processing unit directly can carry out data interaction.This interactive mode is that in interconnection mode involved in the present invention, data interaction is fastest.This interconnection mode ensure that the demand can sharing a upper computation period result of calculation to adjacent two processing units, and this is that most rudimentary algorithm maps demand.Mesh network is mesh network.
For 16 processing units, its two-dimentional mesh structure as shown in Figure 1.Second-level interconnect can be carried out in the basis of direct interaction in adjacent processing units data, namely every 4 reconfigurable processing units are connected with a switch enclosure, as shown in Figure 2.The data interaction of any two can be carried out by switch enclosure between these 4 basic processing units.Its concrete connected mode as shown in Figure 3.What provide in Fig. 3 is the switch enclosure schematic diagram of 4 ports.The data interaction can being undertaken based on switch enclosure by 3 kinds of modes between 4 processing units, as shown in Figure 4.By switch enclosure, each reconfigurable processing unit can carry out data interaction with other three processing units.Wherein first two connected mode is for adjacent two reconfigurable processing units.They supplement connected mode to the one of data direct interaction.When certain interconnection vias be directly connected break down or data congestion time, switch enclosure can be utilized to be coupled together by two adjacent processing units of this in related pathways, carry out data interaction.The third connected mode be for the processing unit of two on diagonal line between data interaction.In immediate data is mutual, the processing unit on diagonal line directly cannot carry out data interaction, must by the routing of XY, and other processing unit that detours can realize data interaction.Not only reduce the efficiency of data transmission like this, also add power consumption.In the present invention, utilize switch enclosure, the connection of diagonal line processing unit by switch enclosure can be realized.In this way, not only avoid the competition for data path, also improve transfer efficiency, reduce power consumption.
Third level interconnection is the connection of the two-dimentional mesh network between switch enclosure, as shown in Figure 6.Each switch enclosure can carry out data interaction by direct-connected with its excess-three switch enclosure.In the mesh network architecture of 4x4 as shown in Figure 6, due to needs connection four reconfigurable processing units and at least two switch enclosures, therefore each switch enclosure at least needs 6 FPDP.As shown in Figure 5, in order to ensure the extensibility of structure, each switch enclosure has 8 input/output port, connection between 4 switch enclosures connected comprising coupled 4 reconfigurable processing units and be adjacent, can interconnect between two according to configuration between these 8 ports, thus make to carry out data interaction between non-conterminous two processing units, and multiple different interconnection structure can be formed, requirement to accommodate different algorithms, each reconfigurable processing unit in the processing unit be connected with same switch enclosure can be interconnected by two kinds of modes, namely the point-to-point direct interconnection in two-dimentional mesh network and the interconnection by switch enclosure, thereby increase reliability of structure.4 port switch boxes in 8 port switch boxes and Fig. 3,4 are similar.Like this, each switch enclosure just can with around 4 reconfigurable processing units and up and down 4 adjacent switch boxes be connected, carry out the direct interaction of data.Certainly, the FPDP of switch enclosure is not limited only to 8, can adjust according to concrete implementation.
In sum, the combination of these three grades interconnection just constitutes the reconfigurable arrays logic interconnection structure of overall multiplied unit.This interconnection structure can realize the direct interconnection of adjacent reconfigurable processing unit and the data interaction by the reconfigurable processing unit on the diagonal line of switch enclosure, on this basis, by the connection of adjacent switch box, the indirect data that can realize between non-conterminous processing unit is mutual.This interactive mode is that data interaction provides multiple choices, can reduce blocking up and competing of data path, improves the transfer efficiency of data, and particularly those are to the strict data interaction of timing requirements, reduce the power consumption of system, improve the performance of system.From in Fig. 5, Fig. 6, it can also be seen that the connected mode of switch enclosure proposed by the invention has a variety of, do not enumerate at this.When different demands, according to the difference of application, user can require that self-defined different connection scheme is to improve the efficiency of interconnection.From figure, also can find out that these switch enclosures can form closed-loop path, so also have multiple by the connected mode of switch enclosure between non-conterminous reconfigurable processing unit, such as, PE_33 is transmitted data to from processing unit PE_11, data transmission can be carried out by switch enclosure s_box_11, s_box_12 and s_box_22; Also data transmission can be carried out by switch enclosure s_box_11, s_box_21 and s_box_22.This also substantially increases dirigibility and the versatility of reconfigurable processing unit array.
The logic interconnection structure adopting 16 processing units is as shown in Figure 5 example, and the reconfigurable arrays logic interconnection structure of the multistage multiplied unit proposed in the present invention can divide 3 grades:
The first order is two-dimentional mesh networking logic interconnection, and as shown in Figure 1, the interconnection structure of two-dimentional mesh network is the logic interconnection structure on basis the most, and the immediate data that it can realize between adjacent processing units is mutual.This structure can adapt to general algorithm mapping requirement on the basis using less interconnection line.
The second level is the logic interconnection of every 4 processing units and a switch enclosure, as shown in Fig. 2, Fig. 5.PE_11, PE_12, PE_21, PE_22 interconnect with S_box_11 respectively; In like manner PE_13, PE_14, PE_23, PE_24 and S_box_12 interconnection; PE_31, PE_32, PE_41, PE_42 and S_box_21 interconnect; PE_33, PE_34, PE_43, PE_44 and S_box_22 interconnect, and these 4 processing units be connected with switch enclosure take 4 switch enclosure ports.Data interaction is carried out by switch enclosure between these processing units, and without the need to passing through other processing unit.
Interconnection between third level interconnection box box.As shown in Figure 6.In 16 pe array, adopt 4 switch enclosures altogether, so in this instance, the port number of switch enclosure just can be defined as 6, thus saves hardware resource.2 ports of each switch enclosure are used for interconnecting with other switch enclosures, form the third level network architecture.
By these three grades of interconnection structures, these overall 16 reconfigurable processing unit array interconnect architecture can two kinds of interconnection modes of achievement unit divisional processing unit: by the point-to-point direct interconnection of two-dimensional network and the indirect interconnection by switch enclosure.These two kinds of interconnection modes complement each other, and when some interconnection line of pe array breaks down or blocks up, can continue to run reconfigurable system, improve the reliability of system to reduce performance for cost.Can be realized the interconnection of any two processing units in 16 processing units by 4 switch enclosures, certain interconnection line also can change according to configuration difference, improves dirigibility and the versatility of reconfigurable arrays like this.
Claims (3)
1. a network interconnection architecture for the reconfigurable arrays of multistage multiplied unit, is characterized in that, comprises three grades of interconnect architecture:
The first order interconnects: two-dimentional mesh network connects, and namely adjacent processing unit directly can carry out data interaction;
The second level interconnects: second-level interconnect can be carried out in the basis of direct interaction in adjacent processing units data, namely every 4 reconfigurable processing units are connected with a switch enclosure, carried out the data interaction of any two by switch enclosure between these 4 basic processing units, the data interaction can being undertaken based on switch enclosure by 3 kinds of modes between 4 processing units: by switch enclosure, each reconfigurable processing unit can both carry out data interaction with other three processing units;
Third level interconnection is the connection of the two-dimentional mesh network between switch enclosure.
2. the network interconnection architecture of the reconfigurable arrays of multistage multiplied unit as claimed in claim 1, it is characterized in that, third level interconnection is the connection of two-dimentional mesh network between switch enclosure is be achieved by the switch enclosure port increased in the interconnection of the second level, being specially switch enclosure port number is n+4, except being connected with 4 reconfigurable processing units, all the other ports are connected with peripheral switch box, form switch enclosure two dimension mesh network.
3. the network interconnection architecture of the reconfigurable arrays of multistage multiplied unit as claimed in claim 1 or 2, it is characterized in that, each switch enclosure port is 6 or 8, wherein 4 ports are used for being connected with 4 reconfigurable processing units, 2 or 4 correspondences of remainder are connected with 2 of surrounding or 4 switch enclosures, form switch enclosure two dimension mesh network.
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| CN112486905A (en) * | 2020-12-18 | 2021-03-12 | 清华大学 | Reconfigurable isomerization PEA interconnection method |
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