CN104391784B - Method and device for fault injection attack based on simulation - Google Patents
Method and device for fault injection attack based on simulation Download PDFInfo
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- CN104391784B CN104391784B CN201410427401.5A CN201410427401A CN104391784B CN 104391784 B CN104391784 B CN 104391784B CN 201410427401 A CN201410427401 A CN 201410427401A CN 104391784 B CN104391784 B CN 104391784B
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Abstract
The invention discloses a method and a device for fault injection attack based on simulation. Under the condition of using no special instrument equipment, before the chip flowing, the fault injection attack is implemented, and a protecting effect for the anti-fault injection safety design of the chip is evaluated. According to the invention, the fault injection attack for the chip is realized in a simulating mode, and the evaluation and analysis for the protecting effect for the safety design of the chip are realized with the minimum cost and the highest efficiency in any link of a chip developing flow under the condition of being independent from the specific realization of a chip safety protection scheme.
Description
Technical field
The present invention relates to chip system security attack technology, refer specifically to a kind of fault injection attacks method based on emulation and
Device.The method can be applicable to during the simulating, verifying of safety chip, it is ensured that be quantified by emulation mode before chip flow
Protective capacities of the safety chip to fault injection attacks.
Background technology
In information security field, the development of integrated circuit and the continuous development of application technology, the safe core such as smart card
Piece carries more and more personal and trade secret information.With measurement and the continuous progress of analytical technology, for password
Attack is no longer limited only to cryptographic algorithm itself, also increasingly mature for the attack of its carrier chip and constantly develop, therefore
The safety problem of chip itself also gradually gets more and more people's extensive concerning.
For failure of chip injection attacks, realize that error detection, fault-tolerant, error correction basic protection Design thought are to add redundancy,
Realize detection and error correction to mistake.From in implementation, redundancy can be increased on hardware, such as addition check bit, module
Replicate etc..Redundancy can also be increased on software, such as repeatedly calculated.From in the type of redundancy, the type of addition redundancy can
To be divided into spatial redundancy, time redundancy, information redundancy.The basic mode of spatial redundancy is to replicate, and can be that equivalent is replicated, and also may be used
Being differential DNA replication.The basic mode of time redundancy is to repeat.Information redundancy refers to add check bit etc..
These means of defences, than larger, especially for smart card, thus bring to chip operational performance and area effect
Performance is reduced, and the cost that area and power consumption increase is likely difficult to what is received.Therefore how within the most short time, with minimum generation
Valency assesses as early as possible the Prevention-Security effect of fail-safe design, so as to preferred cost performance highest defends design, to safe core
Piece system design is significant.
Mainly attack for the evaluating method of safety protection of chip design.Wherein fault injection attacks principle is by changing
Become the ambient parameter of chip operation, such as voltage, temperature, light intensity, ionizing ray, or by changing chip internal device property,
So as to change the electrical property of chip, make chip internal circuits break down, induce the failure behaviour of chip, cause chip to malfunction.
And the error result of chip output can be used to derive the sensitive informations such as the key of needs.
Common methods have using active probe change chip internal signal value, by chip interface on power supply injecting voltage
Burr, injects clock bur or reset burr in clock, reset, or changes core using laser irradiation, electromagnetic signal interference
Piece internal components electrical characteristics.
Analyze visible by more than, usual fault injection attacks are required to implement using special instruments and equipment, and
The chip that silicon chip form can only be directed to is realized carrying out.It is a kind of or many that simultaneous faults injection attacks would generally cause chip internal to produce
Failure is planted, its quantity is difficult to control to, and concrete defective device, signal are invisible, and failure behaviour is difficult to observe.To safety protection of chip
For design evaluation and test, equipment needed thereby is of a high price, and the required time cycle is extremely long, and attack effect is not direct, and analysis is complicated, right
Reviewer's technical merit has high demands.
The content of the invention
Present invention solves the technical problem that being to inject protection Design for failure of chip, there is provided a kind of event based on emulation
Barrier injection attacks method.The method need not use special instruments and equipment, before chip flow, you can implement direct fault location and attack
Hit, the protection effect of chip fail-safe design is evaluated and tested.The method can independently of the implementation of safety protection circuit,
Any link of chip development flow process is used.Emulation mode realizes fault injection attacks, is capable of achieving the maximum controllable of direct fault location
Property and the maximum observability of chip failure behavior, are greatly improved evaluation and test and the analysis efficiency of safety protection of chip design,
Ensure the safety of chip circuitry indirectly.
Technical scheme is as follows：
A kind of fault injection attacks method based on emulation, it is characterised in that comprise the steps：
1) objective of defense is designed according to chip secure to be measured, sets up the excitation text of correspondence chip running environment or Run-time scenario
Gather in part storehouse.
2) according to the safe design objective of defense of chip circuit to be measured, the fault database of correspondence fault type is set up；
3) chip circuit to be measured is connected with excitation library by encouraging load of file control；
4) chip circuit to be measured is connected with fault database by direct fault location control；
5) it is reference chip circuit by chip circuit to be measured backup, by encouraging load of file control by reference chip circuit
It is connected with excitation library；
6) Simulation Control selects to specify excitation from excitation library, while load operating is in chip circuit to be measured and reference
Chip circuit, selects the failure of specified type from fault database, and in excitation run duration chip circuit to be measured is injected into.According to event
The requirement of barrier injection attacks, in the once complete fault injection attacks of scheduling and matching, the injection of the multiple multiple failures of correspondence swashs
Encourage multiple automatic loading and the operation of file；
7) it is all anti-with safety in online acquisition chip circuit to be measured and reference chip circuit during simulation run
The related information of shield design object；
8) during simulation run, monitor in real time chip circuit excitation operation to be measured and direct fault location are controlled, and judge single
Whether secondary direct fault location terminates, and whether single activation operation terminates.By comparing chip circuit to be measured and reference chip circuit
Output, judges whether chip circuit to be measured fails；
9) after fault injection attacks terminate, according to the emulation data message of collection, analyze chip circuit to be measured and whether can
The selected direct fault location of enough defence, defence efficiency and reliability.The attack effect of simulated fault injection implementation method can be analyzed simultaneously
Rate.
Wherein above-mentioned steps 1) in the objective of defense is designed according to chip secure to be measured, set up correspondence chip running environment or fortune
The excitation library set of row scene, including following content：
21) the hardware circuit realization of protection is injected for failure of chip, the chip running environment of the correspondence objective of defense is set up
Or the excitation library set of Run-time scenario；
22) software for injecting protection Design for failure of chip realizes that foundation includes the chip operation of software protecting design
The excitation library set of environment or Run-time scenario；
Above-mentioned steps 2) in set up and cover the fault database set of the targeted fault type of protection Design and comprise the steps,
31) extract in chip circuit to be measured in security protection target zone, implement the signal list attacked；
32) mode that made a mistake by signal to attack is defined, such as signal numerical value is fixed, reversely；
33) time point of signal fault in chip circuit to be measured is defined；
34) time range that signal fault is maintained in chip circuit to be measured is defined；
Above-mentioned steps 3) chip circuit to be measured is connected with excitation library by encouraging load of file control, comprising as follows
Content：
41) load of file control is encouraged to set up the drive connection of chip circuit to be measured and selected excitation file；
42) by selected excitation file configuration chip circuit running environment to be measured and Run-time scenario；
It is above-mentioned to state step 4) chip circuit to be measured is connected with fault database by direct fault location control, comprise the steps,
51) direct fault location control selects one or more failures by parameter configuration from fault database；
52) direct fault location control sets up chip to be measured with the drive connection of selected failure；
Above-mentioned steps 5) by chip circuit to be measured backup be reference chip circuit, by encourage load of file control will refer to
Chip circuit is connected with excitation library, comprises the steps of,
61) on emulation platform, while exampleization chip circuit to be measured is reference chip circuit；
62) load of file control is encouraged, the drive connection of reference chip circuit and selected excitation file is set up；
63) by selected excitation file configuration reference chip circuit running environment and Run-time scenario；
64) reference chip circuit is completely the same with the drive connection of excitation file with chip circuit to be measured, and that what is selected swashs
Encourage file completely the same；
Above-mentioned steps 6) in Simulation Control excitation operation and direct fault location comprise the steps,
71) select current when implementing to attack from excitation library, chip circuit to be measured and reference chip circuit work bar
Excitation file corresponding to part and operative scenario；
72) the current fault type for implementing fault injection attacks is selected from fault database；
73) the excitation file by encouraging load of file control selected runs on chip circuit to be measured and reference chip simultaneously
Circuit；
74) by direct fault location control in excitation run duration every time, according to selected fault type, in the time of definition
The mistake of definition mode is set successively in point, time range on definition signal position, is occurred one by state modulator failure
Or many places；
75) after single failure injection terminates, control is selected excitation and is run again, and dispatches direct fault location next time, until
The corresponding direct fault location emulation of this selected fault attacks all terminates；
It is an advantage of the current invention that：
1) Test and analysis to safe design protectiving scheme can be completed before chip flow；
2) by loading different excitation files, any chip operation running environment and Run-time scenario are capable of achieving, or are realized
Evaluation and test to software protecting design；
3) be likely to occur fault type can be constructed with emulation mode, and direct fault location is intuitively controllable；
4) simulated environment connects chip circuit to be measured and reference chip circuit simultaneously, and chip running, failure procedure are interior
The complete Observable of portion's signal condition, output result.
5) with reference to Simulation Control script, reviewer need to only set excitation file, direct fault location type, residual excitation fortune
Row, attack control, Data acquisition and issuance can whole automatizatioies carry out.For the evaluation and test of failure of chip injection attacks protectiving scheme,
Analysis, modification provide facility.
Description of the drawings
Fig. 1 is that the platform of the inventive method realizes frame diagram.
Specific embodiment
Below in conjunction with the accompanying drawings the invention will be further described with specific embodiment.
As shown in figure 1, a kind of fault injection attacks method based on emulation, its platform realizes frame diagram, including encourages text
Part library unit, failure library unit, the excitation automatic load units of file, direct fault location control unit, chip circuit to be measured, refer to core
Piece circuit, emulation automatic data collection unit, simulation process monitoring unit, data result analytic unit and Simulation Control unit.
Chip circuit to be measured, refers to the chip circuit design with safety and Protection to be evaluated.Include but are not limited to：
Algoritic module unit, such as DES, AES, storage control unit, CPU or full chips etc..
Reference chip circuit, refers to and is not injected into fault attacks, with chip circuit function identical chip circuit design to be measured.Can
With directly backup multiplexing chip circuit to be measured.
Excitation file library unit, is responsible for all chip running environment that storage chip circuit safety and Protection to be measured is directed to
Or the excitation file of Run-time scenario.Can be the computing excitation file of various patterns to algorithm unit.To storage control unit,
Can be various access action excitation files.Can be the excitation file of various logic instruction to CPU.To full chip, Ke Yishi
The excitation file of any scene under any configuration condition.When protection Design scheme to be measured is designed comprising software protecting, excitation text
Part can be the action with software protecting design or scene excitation.
The automatic load units of excitation file, are responsible for reading the excitation file selected in excitation storehouse automatically, while being loaded into
In chip circuit to be measured and reference chip circuit, and realize to chip circuit to be measured and the drive connection of reference chip circuit.
Failure library unit, is responsible for the targeted all fault types of storage chip circuit safety and Protection to be measured.Failure
Type definition includes：For injecting all signals in fault coverage, the mode that signal makes a mistake, such as numerical value are fixed, numerical value
Reversely, data flow is out of order etc., the time point that signal breaks down, time range that failure is maintained etc.；
Direct fault location control unit, is responsible for after emulation starts, and according to selected fault injection attacks type, is matched somebody with somebody by parameter
Put single emulation and one or more failures are selected from fault database, and set up the connection for selecting failure and chip under test circuit signal
Driving relationship.
Emulation automatic data collection unit, in being responsible for all simulation processes of collection, chip circuit to be measured and reference chip are electric
All signal messages related to safety and Protection target in road, including signal condition, the critical internal signal of injection failure
State, module output signal state etc..Collection result is exported gives result data analytic unit.
Simulation process monitoring unit, is responsible for monitoring chip circuit to be measured and receives excitation and the output data after direct fault location,
Monitoring reference chip circuit receives the output data after excitation, and the setting in excitation judges whether single emulation correctly ties
Whether beam, chip circuit to be measured fails, and to emulation controller judgement information is exported.Simultaneously according to selected fault type
Definition judges whether this direct fault location terminates, and to emulation controller judgement information is exported.
Result data analytic unit, is responsible for what is exported according to emulation automatic data collection unit and simulation process monitoring unit
Information, whether can defend selected direct fault location, while statistical analysiss defence effect if analyzing the safe design of chip circuit to be measured
Rate.As option, can be according to direct fault location and the proportionate relationship for causing chip that failure occurs, the control of statistical analysiss direct fault location
The injection efficiency of unit, feeds back to emulation platform and realizes doing further perfect.
Simulation Control unit, is the management program of whole simulated fault injection platform, and user can select current core to be measured
The excitation of piece circuit operation, and injection fault type.By encouraging the automatic load units of file, it is same that excitation operation is selected in control
When run on chip circuit to be measured and reference chip circuit.By direct fault location component in particular point in time, to chip to be measured electricity
The signal specific on road arranges one or more failures of specific mode, and maintains specific time range.Additionally, Simulation Control list
Supervisory control and data acquisition (SCADA) of unit's control to chip circuit to be measured and reference chip circuit emulation run, finally terminates in all emulation
Afterwards, the analytical calculation of control data analyzer and final evaluation result is exported.
The above is only the preferred implementation of the present invention, it is noted that the ordinary skill of the art is developed
Personnel, without departing from the inventive concept of the premise, can also make some improvements and modifications, and these improvements and modifications also should be regarded
For in the scope of the present invention.
Claims (8)
1. it is a kind of based on the fault injection attacks method for emulating, it is characterised in that to comprise the steps：
1) objective of defense is designed according to chip secure to be measured, sets up the excitation file of correspondence chip running environment or Run-time scenario
Storehouse；
2) according to the safe design objective of defense of chip circuit to be measured, the fault database of correspondence fault type is set up；
3) chip circuit to be measured is connected with excitation library by encouraging load of file control；
4) chip circuit to be measured is connected with fault database by direct fault location control；
5) by chip circuit to be measured backup be reference chip circuit, by encourage load of file control by reference chip circuit with swash
Encourage library to be connected；
6) Simulation Control selects to specify excitation from excitation library, while load operating is in chip circuit to be measured and reference chip
Circuit, selects the failure of specified type from fault database, and in excitation run duration chip circuit to be measured is injected into；Noted according to failure
Enter the requirement of attack, in the once complete fault injection attacks of scheduling and matching, the injection of the multiple multiple failures of correspondence, excitation text
The multiple automatic loading of part and operation；
7) it is all to set with security protection in online acquisition chip circuit to be measured and reference chip circuit during simulation run
The related information of meter target；
8) during simulation run, monitor in real time chip circuit excitation operation to be measured and direct fault location are controlled, and judge single event
Whether barrier injection terminates, and whether single activation operation terminates；By the output for comparing chip circuit to be measured and reference chip circuit,
Judge whether chip circuit to be measured fails；
9) after fault injection attacks terminate, according to the emulation data message of collection, analyze whether chip circuit to be measured can be prevented
Drive selected direct fault location, defence efficiency and reliability.
2. it is according to claim 1 a kind of based on the fault injection attacks method for emulating, it is characterised in that the step 1)
Further include following steps：
21) the hardware circuit realization of protection is injected for failure of chip, the chip running environment or fortune of the correspondence objective of defense is set up
The excitation library set of row scene；
22) software for injecting protection Design for failure of chip realizes that foundation includes the chip running environment of software protecting design
Or the excitation library set of Run-time scenario.
3. it is according to claim 1 a kind of based on the fault injection attacks method for emulating, it is characterised in that the step 2)
Further include following steps：
31) extract in chip circuit to be measured in security protection target zone, implement the signal list attacked；
32) mode made a mistake by signal to attack is defined；
33) time point of signal fault in chip circuit to be measured is defined；
34) time range that signal fault is maintained in chip circuit to be measured is defined.
4. it is according to claim 1 a kind of based on the fault injection attacks method for emulating, it is characterised in that the step 3)
Further include following steps：
41) load of file control is encouraged to set up the drive connection of chip circuit to be measured and selected excitation file；
42) by selected excitation file configuration chip circuit running environment to be measured and Run-time scenario.
5. it is according to claim 1 a kind of based on the fault injection attacks method for emulating, it is characterised in that the step 4)
Further include following steps：
51) one or more failure in fault database is selected by state modulator；
52) drive connection for selecting failure and chip circuit to be measured is set up.
6. it is according to claim 1 a kind of based on the fault injection attacks method for emulating, it is characterised in that the step 5)
Further include following steps：
61) on emulation platform, while exampleization chip circuit to be measured is reference chip circuit；
62) load of file control is encouraged, the drive connection of reference chip circuit and selected excitation file is set up；
63) by selected excitation file configuration reference chip circuit running environment and Run-time scenario；
64) reference chip circuit is completely the same with the drive connection of excitation file with chip circuit to be measured, the excitation text selected
Part is completely the same.
7. it is according to claim 1 a kind of based on the fault injection attacks method for emulating, it is characterised in that the step 6)
Further include following steps：
71) when selecting current enforcement to attack from excitation library, the excitation file corresponding to chip circuit working condition to be measured；
72) the current fault type for implementing fault injection attacks is selected from fault database；
73) control selected excitation file and run on chip circuit to be measured and reference chip circuit simultaneously；
74) in excitation run duration every time, according to selected fault type, exist successively in the time point, time range in definition
The mistake of definition mode is set on definition signal position, is occurred one or many places by state modulator failure；
75) after single direct fault location terminates, control is selected excitation and is run again, and dispatches next direct fault location, until this
The fault injection attacks of selection type all terminate.
8. it is a kind of based on emulation fault injection attacks device, it is characterised in that including excitation file library unit, failure library unit,
The automatic load units of excitation file, direct fault location control unit, chip circuit to be measured, reference chip circuit, emulation data are automatic
Collecting unit, simulation process monitoring unit, data result analytic unit and Simulation Control unit, wherein：
Excitation file library unit, is responsible for all chip running environment or fortune that storage chip circuit safety and Protection to be measured is directed to
The excitation file of row scene；
The automatic load units of excitation file, are responsible for reading the excitation file selected in excitation storehouse automatically, while being loaded into be measured
In chip circuit and reference chip circuit, and realize to chip circuit to be measured and the drive connection of reference chip circuit；
Failure library unit, is responsible for the targeted all fault types of storage chip circuit safety and Protection to be measured；
Direct fault location control unit, is responsible for after emulation starts, according to selected fault injection attacks type, by parameter configuration list
Secondary emulation selects one or more failures from fault database, and sets up the connection driving for selecting failure and chip under test circuit signal
Relation；
Emulation automatic data collection unit, in being responsible for all simulation processes of collection, in chip circuit to be measured and reference chip circuit
All signal messages related to safety and Protection target；
Simulation process monitoring unit, is responsible for monitoring chip circuit to be measured and receives excitation and the output data after direct fault location, monitoring
Reference chip circuit receives the output data after excitation, and the setting in excitation judges whether single emulation correctly terminates, and treats
Survey whether chip circuit fails, to emulation controller judgement information is exported；Defined according to selected fault type simultaneously
Judge whether this direct fault location terminates, to emulation controller judgement information is exported；
Result data analytic unit, is responsible for the letter according to emulation automatic data collection unit and the output of simulation process monitoring unit
Breath, whether can defend selected direct fault location, while statistical analysiss defence efficiency if analyzing the safe design of chip circuit to be measured；
Simulation Control unit, is responsible for selecting the excitation of current chip circuit operation to be measured, and injection fault type；By excitation
The automatic load units of file, control selectes excitation operation and runs on chip circuit to be measured and reference chip circuit simultaneously；By event
Barrier fill assembly arranges one or more failures of specific mode in particular point in time to the signal specific of chip circuit to be measured,
And maintain specific time range；Supervisory control and data acquisition (SCADA) to chip circuit to be measured and reference chip circuit emulation run,
After all emulation terminates, the analytical calculation of control data analyzer simultaneously exports final evaluation result.
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| CN106294036A (en) * | 2015-05-21 | 2017-01-04 | 阿里巴巴集团控股有限公司 | A kind of hardware fault verification method, device and client |
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| CN105376058B (en) * | 2015-10-08 | 2018-08-10 | 深圳先进技术研究院 | A kind of security assessment method and device of the hardware based on RSA Algorithm |
| CN106371989A (en) * | 2016-05-06 | 2017-02-01 | 北京中电华大电子设计有限责任公司 | Efficient and secure attack fault injection method adopting batch processing mode |
| CN106326053B (en) * | 2016-08-25 | 2022-02-01 | 深圳先进技术研究院 | Chip safety testing method and system based on fault injection |
| CN106484575B (en) * | 2016-09-29 | 2019-12-10 | 北京润科通用技术有限公司 | ARINC429 bus fault injection system |
| CN106777529A (en) * | 2016-11-23 | 2017-05-31 | 天津大学 | Integrated circuit fault-resistant injection attacks capability assessment method based on FPGA |
| CN106771962B (en) * | 2016-11-29 | 2019-07-19 | 天津大学 | A kind of Fault of Integrated Circuits injection attacks analogy method based on partial scan |
| CN109559583B (en) * | 2017-09-27 | 2022-04-05 | 华为技术有限公司 | Fault simulation method and device |
| CN108255736B (en) * | 2018-02-12 | 2022-02-08 | 苏州盛科通信股份有限公司 | Quality evaluation method and device for circuit test platform |
| CN112132999A (en) * | 2019-06-25 | 2020-12-25 | 国民技术股份有限公司 | Safety testing method and system for intelligent access control equipment |
| WO2021046771A1 (en) * | 2019-09-11 | 2021-03-18 | 华为技术有限公司 | Security detection method and device |
| CN111983429B (en) * | 2020-08-19 | 2023-07-18 | Oppo广东移动通信有限公司 | Chip verification system, chip verification method, terminal and storage medium |
| CN112464294A (en) * | 2020-12-11 | 2021-03-09 | 北京智慧云测信息技术有限公司 | Fault injection attack method and device and electronic equipment |
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