CN104378108A - Clock signal outputting method and circuit - Google Patents
Clock signal outputting method and circuit Download PDFInfo
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- CN104378108A CN104378108A CN201410736566.0A CN201410736566A CN104378108A CN 104378108 A CN104378108 A CN 104378108A CN 201410736566 A CN201410736566 A CN 201410736566A CN 104378108 A CN104378108 A CN 104378108A
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Abstract
The invention discloses a clock signal outputting method. The method includes subjecting a fractional part of a phase-locked loop parameter to spectrum spreading according to a triangular wave signal; superposing carry obtained by subjecting the fractional part of the phase-locked loop to spectrum spreading and an integral part of the phase-locked loop; superposing the fractional part, subjected to spectrum spreading, of the phase-locked loop and the integral part, subjected to superposition, of the phase-locked loop to obtain a doubled frequency parameter; according to the doubled frequency parameter, subjecting a reference clock to frequency doubling to output a clock signal. According to the method, the fractional part of the phase-locked loop parameter is subjected to spectrum spreading through the triangular wave signal, the fractional part of the phase-locked loop parameter subjected to spectrum spreading is not a fixed value but a triangularly linearly changing value, and thus, energy output of the output clock signal is not under the single frequency but evenly distributed to a small frequency range; energy value of each frequency is low, and EMI (electromagnetic interference) is reduced.
Description
Technical field
The application relates to chip anti-interference process technical field, more particularly, relates to a kind of clock signal output intent and circuit.
Background technology
Electromagnetic interference (Electromagnetic Interference, EMI) is a kind of meeting by causing unexpected response or the actual effect thus affect the energy of electric/electronic performance of working completely, and it comprises conducted interference and radiated interference.Conducted interference to refer to by conducting medium the signal coupling (interference) on an electric network to another electric network.Radiated interference refer to interference source by space its signal coupling (interference) to another electric network.EMI is produced by radiation field or inductive voltage and current.High clock frequency in current high-speed digital system and minor face rate also can cause system to occur EMI problem.
Controlled by rational circuitry design, shielding, ground connection, filtration, isolation, separation and orientation, circuit impedance level in prior art, cable designs and noise elimination etc. to be to solve EMI problem, but these schemes are all make an issue of on external circuit, from source, the high clock frequency solved in high-speed digital system does not cause system to occur the problem of EMI, and add the cost of peripheral circuit, make complex circuit designs.
Summary of the invention
In view of this, the application provides a kind of clock signal output intent and circuit, the cost of the increase peripheral circuit caused during for solving and adopting technical scheme traditional in prior art to solve EMI problem, make complex circuit designs and less than the high clock frequency solved in high-speed digital system causes system to occur the problem of EMI from source, this application discloses a kind of clock signal output intent and circuit.
To achieve these goals, the existing scheme proposed is as follows:
A kind of clock signal output intent, comprising:
Obtain pll parameter, reference clock and triangular signal, described pll parameter comprises integer part and fractional part;
Carry out exhibition frequently according to triangular signal to the fractional part of described pll parameter, the fractional part of the pll parameter made is triangular wave change;
Carry out the fractional part of described phase-locked loop to open up the carry obtained frequently to superpose with the integer part of described phase-locked loop;
By the fractional part of the phase-locked loop after exhibition frequently with superpose after integer part superimposed, obtain frequency parameter;
According to described frequency parameter, frequency multiplication is carried out to described reference clock, clock signal.
Preferably, in above-mentioned clock signal output intent, exhibition is carried out frequently to the fractional part of described pll parameter, comprising:
Upwards modulated triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
Preferably, in above-mentioned clock signal output intent, exhibition is carried out frequently to the fractional part of described pll parameter, comprising:
Downward modulation triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
Preferably, in above-mentioned clock signal output intent, exhibition is carried out frequently to the fractional part of described pll parameter, comprising:
Central modulation triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
Preferably, in above-mentioned clock signal output intent, exhibition is carried out frequently to the fractional part of described pll parameter, comprising:
Any modulated triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
A kind of clock signal output circuit, comprising:
Triangular signal generator based, for exporting triangular signal;
First adder, for obtaining the described triangular signal of triangular signal generator based output and the fractional part of pll parameter, and according to described triangular signal, exhibition is carried out frequently to the fractional part of described pll parameter, obtain opening up fractional part and the carry of the pll parameter frequently;
Second adder, the carry that integer part and described first adder for obtaining pll parameter export, superposes the integer part of described carry with described pll parameter, obtains the integer part of the pll parameter after superposing;
Phase-locked loop, superposes for the integer part obtained after the fractional part of the pll parameter after obtaining described exhibition frequently and superposition, obtains frequency parameter, carry out frequency multiplication, clock signal according to frequency parameter to the reference clock got.
Preferably, in above-mentioned clock signal output circuit, described triangular signal generator based for for exporting the triangular signal generator based of upwards modulated triangular wave.
Preferably, in above-mentioned clock signal output circuit, described triangular signal generator based for for exporting the triangular signal generator based of downward modulation triangular wave.
Preferably, in above-mentioned clock signal output circuit, described triangular signal generator based be triangular signal generator based for output center modulated triangular wave.
Preferably, in above-mentioned clock signal output circuit, described triangular signal generator based for for exporting the triangular signal generator based of any modulated triangular wave.
As can be seen from above-mentioned technical scheme, in clock signal output intent disclosed in the present application, by adopting triangular signal, exhibition is carried out frequently to the fractional part of described pll parameter, the fractional part of the pll parameter after Zhan Pin is no longer a fixing value, but the value of a change in triangular linear, thus the frequency causing phase-locked loop to export is not just a single value yet, but the value of small linear change near former single value, may be larger than single value, also possibility little (type decided by triangular wave), therefore, the Energy transmission of the clock signal exported is not also just in single frequency, but be assigned in the frequency of a small scope uniformly, the energy value of so each frequency is just very low, because this reducing EMI interference.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, below the accompanying drawing used required in embodiment or description of the prior art is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the application, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The flow chart of Fig. 1 a kind of clock signal output intent disclosed in the embodiment of the present application;
Fig. 2 is the oscillogram of upwards modulated triangular wave;
Fig. 3 is the design sketch of the clock signal adopting upwards modulated triangular wave to modulate;
Fig. 4 is the oscillogram of downward modulation triangular wave;
Fig. 5 adopts the design sketch to the clock signal gone out by modulated triangular modulation;
The oscillogram of modulated triangular wave centered by Fig. 6;
Fig. 7 is the design sketch of the clock signal adopting central modulation triangular modulation to go out;
Fig. 8 is the design sketch of the clock signal after adopting central modulation triangular wave change modulation range;
Fig. 9 is the oscillogram of any modulated triangular wave;
Figure 10 is the design sketch of the clock signal adopting any modulated triangular wave to modulate;
The structure chart of Figure 11 a kind of clock signal output circuit disclosed in the embodiment of the present application.
Embodiment
Be directed to the cost of the increase peripheral circuit caused when adopting technical scheme traditional in prior art to solve EMI problem, make complex circuit designs and less than the high clock frequency solved in high-speed digital system causes system to occur the problem of EMI from source, this application discloses a kind of clock signal output intent and circuit.
Below in conjunction with the accompanying drawing in the embodiment of the present application, be clearly and completely described the technical scheme in the embodiment of the present application, obviously, described embodiment is only some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the application's protection.
The flow chart of Fig. 1 a kind of clock signal output intent disclosed in the embodiment of the present application.
See Fig. 1, clock signal output intent disclosed in the present application comprises the following steps:
Step S101: obtain pll parameter, reference clock and triangular signal;
Step S102: exhibition is carried out frequently to the fractional part of pll parameter according to triangular signal, the fractional part of the pll parameter made is triangular wave change;
Step S103: carry out the fractional part of phase-locked loop to open up the carry obtained frequently and superpose with the integer part of phase-locked loop;
Step S104: by the fractional part of the phase-locked loop after exhibition frequently with superpose after integer part superimposed, obtain frequency parameter;
Step S105: frequency multiplication is carried out to described reference clock, clock signal according to frequency parameter.
Below the principle that the reduction EMI of the application's said method disturbs is described:
Applicant finds after deliberation, what be subject to EMI restriction is peak emission amount (peakemission) in characteristic frequency, instead of in the average peak amount of whole frequency spectrum, therefore in the application's said method, by adopting triangular signal, exhibition is carried out frequently to the fractional part of described pll parameter, the fractional part of the pll parameter after Zhan Pin is no longer a fixing value, but the value of a change in triangular linear, thus the frequency causing phase-locked loop to export is not just a single value yet, but the value of small linear change near former single value, may be larger than single value, also possibility little (type decided by triangular wave), therefore, the Energy transmission of the clock signal exported is not also just in single frequency, but be assigned in the frequency of a small scope uniformly, the energy value of so each frequency is just very low, because this reducing EMI interference.
Be understandable that, according to the difference of user's request, the type of described triangular wave disclosed in the above embodiments of the present application can be polytype, such as, see Fig. 2, the type of the triangular wave in the above embodiments of the present application can be the upwards modulated triangular wave shown in Fig. 2, namely, upwards modulated triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter, its modulation effect as shown in Figure 3, wherein k is the frequency of clock signal before modulation, the value of n and m is all can get arbitrarily within the scope of the clock signal allowed, k is not more than n, namely, the frequency k of the clock signal that the minimum value n of the frequency of the clock signal of the output after modulation exports before being not less than modulation.See Fig. 4, the type of the triangular wave in the above embodiments of the present application also can be the downward modulation triangular wave shown in Fig. 4, namely, downward modulation triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter, its modulation effect as shown in Figure 5, wherein k is the frequency of clock signal before modulation, the value of n and m is all can get arbitrarily within the scope of the clock signal allowed, k is not less than m, that is, the frequency k of the clock signal that the maximum m of the frequency of the clock signal of the output after modulation exports before being not more than modulation.See Fig. 6, the type of the triangular wave in the above embodiments of the present application can be again the central modulation triangular wave shown in Fig. 6, namely, central modulation triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter, its modulation effect as shown in Figure 7, wherein k is the frequency of clock signal before modulation, the value of n and m is all can get arbitrarily within the scope of the clock signal allowed, k=(n+m)/2, that is, the frequency of the clock signal that the mean value of the frequency of the clock signal of the output after modulation exports before equaling to modulate.See Fig. 8, design sketch centered by it after modulated triangular wave change modulation range, when when n and m value changes time, scope becomes large, then amplitude diminishes, thus the value of EMI is fallen lower, but it is larger that the result caused is the rocking of output clock (jitter), therefore in actual application, user comprehensively the value of EMI and clock jitter can select the value of suitable n and m, to reach optimum efficiency.Certainly, described triangular signal can also be any modulated triangular wave as shown in Figure 9, and its modulation effect as shown in Figure 10, modulates the frequency f=k of front clock signal.So-called any modulation refers to the frequency f scope after modulation: n<f<m, wherein the value of n and m is all can get arbitrarily in the scope allowed, therefore can need according to user the scope controlling arbitrarily clock signal frequency, thus can the value of better control EMI more accurately.Modulation arbitrarily can be utilized in addition exactly the difficulty of some coilings is avoided when back-end chip coiling.If the maximum of such as upwards modulating is excessive, around not going down, can modulate maximum reduction by any thus coiling is carried out smoothly when coiling.
It is appreciated of course that, in the application's said method, described triangular signal is the representational class waveform signal of most, and other ripples can also be adopted except described triangular wave to carry out exhibition frequently to the fractional part of described pll parameter, such as sine wave, cosine wave etc.
The structure chart of Figure 11 a kind of clock signal output circuit disclosed in the embodiment of the present application.
Be understandable that, corresponding to said method, disclosed herein as well is a kind of clock signal output circuit corresponding with said method, both can use for reference mutually, and see Figure 11, this circuit comprises:
Triangular signal generator based 1, for exporting triangular signal;
First adder 2, for obtaining the described triangular signal of triangular signal generator based output and the fractional part FRAC of pll parameter, and according to described triangular signal, exhibition is carried out frequently to the fractional part FRAC of described pll parameter, obtain opening up fractional part frac_sum and the carry carry of the pll parameter frequently;
Second adder 3, for the carry carry that the integer part INT and described first adder 2 that obtain pll parameter export, described carry carry is superposed with the integer part INT of described pll parameter, obtains the integer part int_sum of the pll parameter after superposing;
Phase-locked loop 4 (PLL), for obtaining and the integer part int_sum obtained after the fractional part frac_sum of the pll parameter after described exhibition frequently and superposition being superposed, obtain frequency parameter, according to frequency parameter, frequency multiplication is carried out, clock signal to the reference clock Refernce clock got.
Corresponding with said method, described triangular signal generator based 1 can for for exporting the triangular signal generator based of upwards modulated triangular wave or for exporting the triangular signal generator based of downward modulation triangular wave or for the triangular signal generator based of output center modulated triangular wave or for exporting the triangular signal generator based of any modulated triangular wave.
Certainly, describedly triangular signal generator basedly the replacement such as sine wave signal generator, cosine wave signal generator can also be adopted.
It should be noted that in addition, utilize the clock-signal generator of method disclosed in the above embodiments of the present application or circuit and for the electric equipment of this clock-signal generator all within the open scope of the application.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the application.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from the spirit or scope of the application, can realize in other embodiments.Therefore, the application can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a clock signal output intent, is characterized in that, comprising:
Obtain pll parameter, reference clock and triangular signal, described pll parameter comprises integer part and fractional part;
Carry out exhibition frequently according to triangular signal to the fractional part of described pll parameter, the fractional part of the pll parameter made is triangular wave change;
Carry out the fractional part of described phase-locked loop to open up the carry obtained frequently to superpose with the integer part of described phase-locked loop;
By the fractional part of the phase-locked loop obtained after exhibition frequently with superpose after integer part superimposed, obtain frequency parameter;
According to described frequency parameter, frequency multiplication is carried out to described reference clock, clock signal.
2. clock signal output intent according to claim 1, is characterized in that, carries out exhibition frequently, comprising the fractional part of described pll parameter:
Upwards modulated triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
3. clock signal output intent according to claim 1, is characterized in that, carries out exhibition frequently, comprising the fractional part of described pll parameter:
Downward modulation triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
4. clock signal output intent according to claim 1, is characterized in that, carries out exhibition frequently, comprising the fractional part of described pll parameter:
Central modulation triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
5. clock signal output intent according to claim 1, is characterized in that, carries out exhibition frequently, comprising the fractional part of described pll parameter:
Any modulated triangular wave is adopted to carry out exhibition frequently to the fractional part of described pll parameter.
6. a clock signal output circuit, is characterized in that, comprising:
Triangular signal generator based, for exporting triangular signal;
First adder, for obtaining the described triangular signal of triangular signal generator based output and the fractional part of pll parameter, and according to described triangular signal, exhibition is carried out frequently to the fractional part of described pll parameter, obtain opening up fractional part and the carry of the pll parameter frequently;
Second adder, the carry that integer part and described first adder for obtaining pll parameter export, superposes the integer part of described carry with described pll parameter, obtains the integer part of the pll parameter after superposing;
Phase-locked loop, superposes for the integer part obtained after the fractional part of the pll parameter after obtaining described exhibition frequently and superposition, obtains frequency parameter, carry out frequency multiplication, clock signal according to frequency parameter to the reference clock got.
7. clock signal output circuit according to claim 6, is characterized in that, comprising:
Described triangular signal generator based for for exporting the triangular signal generator based of upwards modulated triangular wave.
8. clock signal output circuit according to claim 6, is characterized in that, comprising:
Described triangular signal generator based for for exporting the triangular signal generator based of downward modulation triangular wave.
9. clock signal output circuit according to claim 6, is characterized in that, comprising:
Described triangular signal generator based be triangular signal generator based for output center modulated triangular wave.
10. clock signal output circuit according to claim 6, is characterized in that, comprising:
Described triangular signal generator based for for exporting the triangular signal generator based of any modulated triangular wave.
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| CN201410736566.0A CN104378108B (en) | 2014-12-04 | 2014-12-04 | A kind of clock signal output intent and circuit |
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| CN201410736566.0A CN104378108B (en) | 2014-12-04 | 2014-12-04 | A kind of clock signal output intent and circuit |
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| CN104378108B CN104378108B (en) | 2017-10-03 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106155973A (en) * | 2016-07-26 | 2016-11-23 | 中国科学院上海应用物理研究所 | The digital low of energy flexible configuration clock frequency controls processor |
| CN107896109A (en) * | 2016-10-03 | 2018-04-10 | 亚德诺半导体集团 | The generation of zigzag slope is quickly established in phase-locked loop |
| CN109683677A (en) * | 2018-12-21 | 2019-04-26 | 深圳市车联天下信息科技有限公司 | For reducing the method and device of the radiation interference of I.MX6 chip |
| TWI746411B (en) * | 2021-05-24 | 2021-11-11 | 穩脈科技股份有限公司 | Clock generating circuit and calibration circuit thereof |
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| US5631920A (en) * | 1993-11-29 | 1997-05-20 | Lexmark International, Inc. | Spread spectrum clock generator |
| CN101404569A (en) * | 2007-11-23 | 2009-04-08 | 硅谷数模半导体（北京）有限公司 | Apparatus and method for frequency expansion of reference clock signal |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106155973A (en) * | 2016-07-26 | 2016-11-23 | 中国科学院上海应用物理研究所 | The digital low of energy flexible configuration clock frequency controls processor |
| CN106155973B (en) * | 2016-07-26 | 2019-04-02 | 中国科学院上海应用物理研究所 | The digital low control processor of energy flexible configuration clock frequency |
| CN107896109A (en) * | 2016-10-03 | 2018-04-10 | 亚德诺半导体集团 | The generation of zigzag slope is quickly established in phase-locked loop |
| CN109683677A (en) * | 2018-12-21 | 2019-04-26 | 深圳市车联天下信息科技有限公司 | For reducing the method and device of the radiation interference of I.MX6 chip |
| TWI746411B (en) * | 2021-05-24 | 2021-11-11 | 穩脈科技股份有限公司 | Clock generating circuit and calibration circuit thereof |
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