CN104377141A - Method for detecting actual critical dimension and etching depth of deep groove structure in wafer - Google Patents
Method for detecting actual critical dimension and etching depth of deep groove structure in wafer Download PDFInfo
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- CN104377141A CN104377141A CN201310358577.5A CN201310358577A CN104377141A CN 104377141 A CN104377141 A CN 104377141A CN 201310358577 A CN201310358577 A CN 201310358577A CN 104377141 A CN104377141 A CN 104377141A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
The invention discloses a method for detecting the actual critical dimension and the etching depth of a deep groove structure in wafer. The method includes the steps that S1, multiple holes penetrating through a substrate layer are formed so that the sum of lengths of the holes is larger than a preset critical dimension of the deep groove structure; S2, positions, corresponding to the holes in the substrate layer, on an epitaxial layer are etched to form the deep groove structure; S3, the wafer is irradiated from the epitaxial layer to the substrate layer, and a bright field area and a dark field area are formed on the surface of the substrate layer; S4, the number of holes in the bright field area is recognized, and the actual critical dimension of the deep groove structure is calculated; S5, if the actual critical dimension of the deep groove structure is smaller than the preset critical dimension, the step S2 is repeated, and if it is recognized that the holes in the substrate layer are connected, it is indicated that the deep groove structure of the epitaxial layer is etched. By means of the method, the actual critical dimension of the deep groove structure can be controlled, the problems of incomplete etching and over etching are avoided, process stability is good, and repeatability is good.
Description
Technical field
The present invention relates to field of semiconductor technology, be specifically related to deep plough groove etched technology field, particularly relate to and a kind ofly detect the actual critical size of deep groove structure and the method for etching depth in wafer.
Background technology
In semiconductor manufacturing special process, as integrated circuit in the manufacturing process of semiconductor device that uses, often need to use deep groove structure to realize certain special performance, etching depth is greater than 300 μm, etch critical dimension (Critical dimension, CD) be greater than 500 μm, and rest on predetermined etching stop layer after deep plough groove etched (DSIE) technique.But the process time needed for DSIE technique is longer, etching depth comparatively dark (degree of depth can reach hundreds of μm), cause finally judging whether DSIE etching depth reaches desired depth accurately, easily there is over etching or etch the phenomenons such as incomplete, causing the performance failure of wafer after DSIE technique.
In prior art; step instrument is adopted to measure DSIE etching depth; but when close to default etching depth; due to the depth calculation error of the protective film of measure error and effects on surface; easily cause the error of calculation to actual etching depth; and accurately cannot judge that bottom arrives the actual CD of desired depth, thus occur etching problem that is incomplete or over etching.And utilize step instrument measure step consuming time longer, take the actual process time reduce production capacity, and technology stability and repeatability poor, can not according to actual process situation judge etching direction, reduce process repeatability and predictability.
Summary of the invention
In view of this, embodiment of the present invention proposition is a kind of detects the actual critical size of deep groove structure and the method for etching depth in wafer, by forming the multiple holes running through described substrate layer at substrate layer, light is irradiated described wafer from epitaxial loayer to substrate layer direction, bright field district and details in a play not acted out on stage, but told through dialogues district is formed on the surface at described substrate layer, calculate the actual critical size of deep groove structure according to the number in the hole in described bright field district, solve the technical problem that above background technology part is mentioned.
Embodiment of the present invention proposition is a kind of detects the actual critical size of deep groove structure and the method for etching depth in wafer, the substrate layer that described wafer comprises epitaxial loayer, is positioned at the etching stop layer on described epitaxial loayer and is positioned on etching stop layer, described method comprises:
S1, described substrate layer is formed and runs through multiple holes of described substrate layer, the critical size in each hole in described multiple hole and number and pitch of holes set according to the default critical size of deep groove structure to be produced, with the default critical size making the total length in described multiple hole be greater than described deep groove structure, wherein, the critical size in described each hole is D2, number is N, described pitch of holes is d, the total length in described multiple hole is L, the default critical size of described deep groove structure is D, then L=D2 × N+d × (N-1), L>D;
S2, the position in the described multiple hole corresponded in described substrate layer in described epitaxial loayer to be etched, to form deep groove structure;
S3, irradiate described wafer from described epitaxial loayer to described substrate layer direction with light, form bright field district and details in a play not acted out on stage, but told through dialogues district on the surface at described substrate layer, wherein, described bright field district is corresponding through the deep groove structure region of this epitaxial loayer with light;
S4, identify the number in hole described in described bright field district, calculate the actual critical size of described deep groove structure according to the number in described hole, wherein, the number in described hole is N1, and the actual critical size of described deep groove structure is D1;
If the actual critical size of the described deep groove structure of S5 is less than the default critical size of described deep groove structure, i.e. D1<D, then instruction etching not exclusively, the adjustment subsequent technique time, returns step S2; If connecting appears in the hole on the described substrate layer identified, then show the deep groove structure over etching of epitaxial loayer.
Further, described step S3 comprises:
Described wafer is downward with epitaxial loayer, substrate layer is upwards placed on microscopical transparent objective table;
The light launched of described microscopical light source through the multiple holes on the deep groove structure of described wafer, etching stop layer, substrate layer, forms described bright field district at described substrate layer successively on the surface.
Further, described in described identification described bright field district, the number in hole adopts artificial reading manner.
Further, the number in hole described in the described bright field district of described identification adopts image recognition mode.
Further, the actual critical size that the described number according to described hole calculates described deep groove structure is obtained by following formula:
D1=D2×N1+d×(N1-1)。
Further, described etching is dry etching or wet etching.
Further, described dry etching is plasma etching or reactive ion etching.
Further, the material of described substrate layer and described epitaxial loayer is silicon, and the material of described etching stop layer is silicon dioxide.
In the detection wafer that the embodiment of the present invention proposes, the actual critical size of deep groove structure and the method for etching depth have following features: by forming the multiple holes running through described substrate layer at substrate layer, light is irradiated described wafer from epitaxial loayer to substrate layer direction, bright field district and details in a play not acted out on stage, but told through dialogues district is formed on the surface at described substrate layer, calculate the actual critical size of deep groove structure according to the number in the hole in described bright field district, and can etching depth be judged.Method described in the embodiment of the present invention can control the actual critical size of deep groove structure accurately, and can etching depth be judged, the adjusting process time, stop the problem etching incomplete sum over etching, and technology stability and repeatability good, according to the actual conditions adjusting process condition of wafer, the steady quality of wafer can be ensured.
Accompanying drawing explanation
Fig. 1 is the flow chart of the actual critical size of deep groove structure and the method for etching depth in the detection wafer in first embodiment of the invention;
Fig. 2 is the schematic cross-section of wafer before the etching in the embodiment of the present invention;
Fig. 3 is the schematic cross-section running through multiple holes of described substrate layer in substrate layer formation in the embodiment of the present invention;
Fig. 4 is the schematic cross-section after epitaxial loayer etches deep groove structure in the embodiment of the present invention.
Fig. 2-Fig. 4 description of reference numerals: 1 represents epitaxial loayer, 2 represent etching stop layer, and 3 represent substrate layer, and 4 represent the hole on substrate layer, and 5 represent deep groove structure; D2 represents the critical size in hole, and d represents pitch of holes, and L represents the total length in described multiple hole, and D represents the default critical size of described deep groove structure.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
Figure 1 illustrates the first embodiment of the present invention.
Fig. 1 is the realization flow 100 of the actual critical size of deep groove structure and the method for etching depth in the detection wafer in first embodiment of the invention.Fig. 2 shows the schematic cross-section of the front wafer of etching, as shown in Figure 2, and the substrate layer 3 that described wafer comprises epitaxial loayer 1, is positioned at the etching stop layer 2 on epitaxial loayer 1 and is positioned on etching stop layer 2.Wherein, the material of described substrate layer 3 and described epitaxial loayer 1 is silicon, and the material of described etching stop layer 2 is silicon dioxide.It will be understood by those skilled in the art that the material of described substrate layer 3, described epitaxial loayer 1 and described etching stop layer 2 also can be other materials.
In detection wafer in first embodiment of the invention, details are as follows for the realization flow 100 of the actual critical size of deep groove structure and the method for etching depth:
In a step 101, substrate layer is formed the multiple holes running through this substrate layer, the critical size in each hole in described multiple hole and number and pitch of holes set according to the default critical size of deep groove structure to be produced, with the default critical size making the total length in described multiple hole be greater than described deep groove structure.
In the present embodiment, the substrate layer of wafer forms by etching or additive method the multiple holes running through this substrate layer, the critical size in each hole in described multiple hole and number and pitch of holes set according to the default critical size of deep groove structure to be produced, with the default critical size making the total length in described multiple hole be greater than described deep groove structure.Wherein, the critical size in described each hole is D2, and number is N, and described pitch of holes is d, and the total length in described multiple hole is L, and the default critical size of described deep groove structure is D, then L=D2 × N+d × (N-1), L>D.The degree of depth in described multiple hole is the thickness of described substrate layer, and usually, the thickness of described substrate layer is at about 20 μm.Fig. 3 shows the schematic cross-section implementing wafer after this step, as shown in Figure 3,1 represents epitaxial loayer, 2 represent etching stop layer, 3 represent substrate layer, and 4 represent the hole formed on substrate layer, and L represents the total length in described multiple hole, D2 represents the critical size in described each hole, and d represents described pitch of holes.As can be seen from Figure 3, porose critical size and the degree of depth are all identical, and spacing is also identical.
In a step 102, the position in the multiple holes corresponded in substrate layer in epitaxial loayer is etched, to form deep groove structure.
In the present embodiment, the position in the multiple holes corresponded in substrate layer in epitaxial loayer is etched, to form deep groove structure.Described etching is dry etching or wet etching, and described dry etching is plasma etching or reactive ion etching, and lithographic method can be selected as required.Fig. 4 shows the schematic cross-section implementing wafer after this step, and Fig. 4 is only a schematic diagram, represents the perfect condition that deep groove structure just etches into predetermined depth and default critical size and etches completely.As shown in Figure 4, L represents the total length in described multiple hole, D2 represents the critical size in described each hole, d represents described pitch of holes, D represents the default critical size of deep groove structure, L=D2 × N+d × (N-1), the total length in the described multiple hole on substrate layer is greater than the default critical size of deep groove structure on epitaxial loayer, i.e. L>D.
In step 103, with light from epitaxial loayer to substrate layer direction irradiate wafer, form bright field district and details in a play not acted out on stage, but told through dialogues district on the surface at described substrate layer.
In the present embodiment, with the direction irradiate wafer of light from epitaxial loayer to substrate layer, can form bright field district and details in a play not acted out on stage, but told through dialogues district on the surface of described substrate layer, wherein, described bright field district is corresponding through the deep groove structure region of this epitaxial loayer with light.Be incident on light on the epitaxial loayer outside deep groove structure thicker due to the thickness of the epitaxial loayer be not etched away, and be not through, thus on the surface of described substrate layer, form the part darker relative to described bright field district, be called details in a play not acted out on stage, but told through dialogues district.Contrast Fig. 4, light, from epitaxial loayer 1 to the direction irradiate wafer of substrate layer 3, through the multiple holes 4 on deep groove structure 5, etching stop layer 2 and epitaxial loayer 1, can form brighter region, be called bright field district on the surface of substrate layer 3; Because the thickness of the epitaxial loayer 1 be not etched away is thicker, light can not be through, thus on the surface of described substrate layer 3, form the part darker relative to described bright field district, is called details in a play not acted out on stage, but told through dialogues district.
Step 103 also can comprise following sub-step:
Sub-step 1031, described wafer is downward with epitaxial loayer, substrate layer is upwards placed on microscopical transparent objective table.Described microscopical objective table needs to select material that is transparent, printing opacity, is beneficial to passing of light.
Sub-step 1032, the light of described microscopical light source transmitting passes the multiple holes on the deep groove structure of described wafer, etching stop layer, substrate layer successively, forms bright field district on the surface at described substrate layer.The light that light source below described microscopical objective table is launched is successively through the multiple holes on the deep groove structure on the epitaxial loayer of the wafer be placed on transparent objective table, etching stop layer, substrate layer, bright field district can be formed on the surface of described substrate layer, corresponding with it, region dark compared with bright field district on the surface of described substrate layer is details in a play not acted out on stage, but told through dialogues district.
At step 104, identify the number of bright field district mesopore, calculate the actual critical size of deep groove structure according to the number in described hole.
In the present embodiment, first identify the number in the hole in the bright field district of substrate layer, by artificial mode identification of reading, also can pass through the mode identification of image recognition here.Described artificial reading, is that people is placed in the wafer on transparent objective table by microscopic examination, reads out the number in the hole in described bright field district.Described image recognition, being by taking pictures to the substrate layer of the wafer be irradiated by light, identifying the number in the hole in bright field district by the mode of image recognition.Image recognition mode adopts prior art to carry out, and repeats no more here.
In the present embodiment, after identifying the number of bright field district mesopore, the actual critical size of deep groove structure just can be calculated according to the number in described hole, wherein, the number in described hole is N1, the actual critical size of described deep groove structure is D1, then the actual critical size D1 of described deep groove structure can be obtained by following formula:
D1=D2×N1+d×(N1-1)
In formula, D2 represents the critical size in described each hole, and d represents pitch of holes.
In step 105, if the actual critical size of deep groove structure is less than the default critical size of deep groove structure, then instruction etching not exclusively, the adjustment subsequent technique time, returns and performs step 102; If connecting appears in the hole on the substrate layer identified, then show the deep groove structure over etching of epitaxial loayer.
In the present embodiment, if the actual critical size of the deep groove structure calculated is less than the default critical size of deep groove structure, i.e. D1<D, here the situation not forming bright field district on substrate layer is comprised, then instruction etching not exclusively, comprise the situation that etching depth does not arrive default etching depth, according to the actual critical size adjustment subsequent technique time of described deep groove structure, return and perform step 102.
In the present embodiment, if connecting appears in the hole on the substrate layer identified, then the deep groove structure over etching of epitaxial loayer is shown.
The present embodiment by forming the multiple holes running through substrate layer on the substrate layer of wafer, light is made to irradiate described wafer along epitaxial loayer to substrate layer direction, the substrate layer of wafer is formed bright field district and details in a play not acted out on stage, but told through dialogues district, calculated the actual critical size of deep groove structure by the number in the hole in bright field district, and can etching depth be judged.Method described in the present embodiment can control the actual critical size of deep groove structure accurately, and can etching depth be judged, the adjustment subsequent technique time, stop the problem etching incomplete sum over etching, and technology stability and repeatability good, according to the actual conditions adjusting process condition of wafer, the steady quality of wafer can be ensured.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (8)
1. detect the actual critical size of deep groove structure and a method for etching depth in wafer, the substrate layer that described wafer comprises epitaxial loayer, is positioned at the etching stop layer on described epitaxial loayer and is positioned on etching stop layer, is characterized in that, described method comprises:
S1, described substrate layer is formed and runs through multiple holes of this substrate layer, the critical size in each hole in described multiple hole and number and pitch of holes set according to the default critical size of deep groove structure to be produced, with the default critical size making the total length in described multiple hole be greater than described deep groove structure, wherein, the critical size in described each hole is D2, number is N, described pitch of holes is d, the total length in described multiple hole is L, the default critical size of described deep groove structure is D, then L=D2 × N+d × (N-1), L>D;
S2, the position in the described multiple hole corresponded in described substrate layer in described epitaxial loayer to be etched, to form deep groove structure;
S3, irradiate described wafer from described epitaxial loayer to described substrate layer direction with light, form bright field district and details in a play not acted out on stage, but told through dialogues district on the surface at described substrate layer, wherein, described bright field district is corresponding through the deep groove structure region of this epitaxial loayer with light;
S4, identify the number in hole described in described bright field district, calculate the actual critical size of described deep groove structure according to the number in described hole, wherein, the number in described hole is N1, and the actual critical size of described deep groove structure is D1;
If the actual critical size of the described deep groove structure of S5 is less than the default critical size of described deep groove structure, i.e. D1<D, then instruction etching not exclusively, the adjustment subsequent technique time, returns step S2; If connecting appears in the hole on the described substrate layer identified, then show the deep groove structure over etching of epitaxial loayer.
2. the actual critical size of deep groove structure and the method for etching depth in detection wafer according to claim 1, it is characterized in that, described step S3 comprises:
Described wafer is downward with epitaxial loayer, substrate layer is upwards placed on microscopical transparent objective table;
The light launched of described microscopical light source through the multiple holes on the deep groove structure of described wafer, etching stop layer, substrate layer, forms described bright field district at described substrate layer successively on the surface.
3. the actual critical size of deep groove structure and the method for etching depth in detection wafer according to claim 1, is characterized in that, described in described identification described bright field district, the number in hole adopts artificial reading manner.
4. the actual critical size of deep groove structure and the method for etching depth in detection wafer according to claim 1, is characterized in that, the number in hole described in the described bright field district of described identification adopts image recognition mode.
5. the actual critical size of deep groove structure and the method for etching depth in detection wafer according to claim 1, it is characterized in that, the actual critical size that the described number according to described hole calculates described deep groove structure is obtained by following formula:
D1=D2×N1+d×(N1-1)。
6. the actual critical size of deep groove structure and the method for etching depth in detection wafer according to claim 1, it is characterized in that, described etching is dry etching or wet etching.
7. the actual critical size of deep groove structure and the method for etching depth in detection wafer according to claim 6, it is characterized in that, described dry etching is plasma etching or reactive ion etching.
8. the actual critical size of deep groove structure and the method for etching depth in detection wafer according to claim 1, is characterized in that, the material of described substrate layer and described epitaxial loayer is silicon, and the material of described etching stop layer is silicon dioxide.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111128776A (en) * | 2019-12-05 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for measuring deep groove depth |
CN112908878A (en) * | 2021-01-20 | 2021-06-04 | 江西慧光微电子有限公司 | Processing method and processing device for electronic product |
CN113394127A (en) * | 2021-06-16 | 2021-09-14 | 长江存储科技有限责任公司 | Method for monitoring critical dimension of 3D memory bridging structure |
CN113628985A (en) * | 2021-07-07 | 2021-11-09 | 华虹半导体(无锡)有限公司 | Detection method for film thickness uniformity |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004212553A (en) * | 2002-12-27 | 2004-07-29 | Ricoh Co Ltd | Polarizing diffractive optical element, optical pickup device, and optical disk drive system |
CN1701420A (en) * | 2002-09-25 | 2005-11-23 | 兰姆研究有限公司 | Apparatus and method for controlling etch depth |
US20070148792A1 (en) * | 2005-12-27 | 2007-06-28 | Marx David S | Wafer measurement system and apparatus |
CN101581571A (en) * | 2009-06-19 | 2009-11-18 | 武汉钢铁(集团)公司 | Method for measuring pit depth with scanning electronic microscope |
CN102402126A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Structure for detecting lighting conditions in lithography and detection method thereof |
CN103065942A (en) * | 2013-01-08 | 2013-04-24 | 无锡华润上华半导体有限公司 | Method for controlling quirk corrosion formative semi-conducting film thickness and semiconductor structure |
CN103245300A (en) * | 2012-02-13 | 2013-08-14 | 深南电路有限公司 | Depth-control drill test device and test method for PCB (printed circuit board) |
-
2013
- 2013-08-16 CN CN201310358577.5A patent/CN104377141B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1701420A (en) * | 2002-09-25 | 2005-11-23 | 兰姆研究有限公司 | Apparatus and method for controlling etch depth |
JP2004212553A (en) * | 2002-12-27 | 2004-07-29 | Ricoh Co Ltd | Polarizing diffractive optical element, optical pickup device, and optical disk drive system |
US20070148792A1 (en) * | 2005-12-27 | 2007-06-28 | Marx David S | Wafer measurement system and apparatus |
CN101581571A (en) * | 2009-06-19 | 2009-11-18 | 武汉钢铁(集团)公司 | Method for measuring pit depth with scanning electronic microscope |
CN102402126A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Structure for detecting lighting conditions in lithography and detection method thereof |
CN103245300A (en) * | 2012-02-13 | 2013-08-14 | 深南电路有限公司 | Depth-control drill test device and test method for PCB (printed circuit board) |
CN103065942A (en) * | 2013-01-08 | 2013-04-24 | 无锡华润上华半导体有限公司 | Method for controlling quirk corrosion formative semi-conducting film thickness and semiconductor structure |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111128776A (en) * | 2019-12-05 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for measuring deep groove depth |
CN111128776B (en) * | 2019-12-05 | 2022-07-19 | 华虹半导体(无锡)有限公司 | Method for measuring deep groove depth |
CN112908878A (en) * | 2021-01-20 | 2021-06-04 | 江西慧光微电子有限公司 | Processing method and processing device for electronic product |
CN113394127A (en) * | 2021-06-16 | 2021-09-14 | 长江存储科技有限责任公司 | Method for monitoring critical dimension of 3D memory bridging structure |
CN113394127B (en) * | 2021-06-16 | 2022-04-19 | 长江存储科技有限责任公司 | Method for monitoring critical dimension of 3D memory bridging structure |
CN113628985A (en) * | 2021-07-07 | 2021-11-09 | 华虹半导体(无锡)有限公司 | Detection method for film thickness uniformity |
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