CN104375547B - The system of sense terminals load - Google Patents
The system of sense terminals load Download PDFInfo
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- CN104375547B CN104375547B CN201410453527.XA CN201410453527A CN104375547B CN 104375547 B CN104375547 B CN 104375547B CN 201410453527 A CN201410453527 A CN 201410453527A CN 104375547 B CN104375547 B CN 104375547B
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Abstract
The invention discloses a kind of system of sense terminals load, whether load is connected with for sense terminals in high-speed differential signal transmitting procedure, comprise transmitting terminal driving circuit, load detecting circuit, receiving terminal circuit and two electric capacity, wherein, load detecting circuit comprises the first detection electronic circuit and second and detects electronic circuit, first detects electronic circuit is connected between transmitting terminal driving circuit and an electric capacity, second detects electronic circuit is connected between transmitting terminal driving circuit and another electric capacity, first detects electronic circuit comprises direct supply, first resistance, second resistance, 3rd resistance, switch, timer, current source, reference resistance and comparer, the output terminal of comparer exports the first testing result, second detects electronic circuit has and detects the identical architectural feature of electronic circuit with first, and the second output terminal detecting the comparer of electronic circuit exports the second testing result.The system of sense terminals load of the present invention, can sense terminals load accurately and rapidly, and structure is simple, and shared chip area is little, low in energy consumption.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of system of sense terminals load.
Background technology
In high-speed serial data transmission system, electronic equipment carries out between plate or between sheet in the process of high speed data transfer, and the transmitting terminal of electronic equipment need detect counterpart device receiving end and whether be mounted with load by transmission medium, thus judges whether to send high-speed data.Due in high-speed serial communication system, the existence of the factors such as the mismatch of the stray capacitance produced between plate or between sheet and transmission medium and transmission and receiving-end impedance, can cause larger interference to testing circuit, have a strong impact on the accuracy of testing result.And the system of existing sense terminals load does not all have the characteristic of the fast and low-power consumption of high noise immunity, accurately determination range, detection speed, can not detect the load of receiving end exactly.
Therefore, be necessary to provide a kind of system of sense terminals load of improvement to overcome above-mentioned defect.
Summary of the invention
The object of this invention is to provide a kind of system of sense terminals load, this system can sense terminals load accurately and rapidly, and structure is simple, and shared chip area is little, low in energy consumption.
For achieving the above object, the invention provides a kind of system of sense terminals load, whether load is connected with for sense terminals in high-speed differential signal transmitting procedure, comprise transmitting terminal driving circuit, load detecting circuit, receiving terminal circuit and two electric capacity, electric capacity described in two is connected between described transmitting terminal driving circuit and receiving terminal circuit, described load detecting circuit to be connected to described in described transmitting terminal driving circuit and two between electric capacity, wherein, described load detecting circuit comprises the first detection electronic circuit and second and detects electronic circuit, described first detects electronic circuit is connected between described transmitting terminal driving circuit and an electric capacity, described second detects electronic circuit is connected between described transmitting terminal driving circuit and another electric capacity, described first detects electronic circuit comprises direct supply, first resistance, second resistance, 3rd resistance, switch, timer, current source, reference resistance and comparer, described first resistance is all connected with direct supply with one end of the 3rd resistance, the other end of described first resistance, one end of second resistance, one end of switch, one end of one electric capacity is all connected with the reverse input end of described comparer, the other end of described 3rd resistance is connected with the other end of described switch, the other end ground connection of described second resistance, described timer controls closing/closing of described switch according to setting-up time timing, one end of described current source, one end of reference resistance is all connected with the positive input of described comparer, the other end of described current source is connected with the control end of described comparer, the output terminal of described comparer exports the first testing result, described second detects electronic circuit has and detects the identical architectural feature of electronic circuit with first, and the described second output terminal detecting the comparer of electronic circuit exports the second testing result.
Preferably, described load detecting circuit also comprises a Logic judgment electronic circuit, described first testing result and the second testing result all input described Logic judgment electronic circuit, and two testing results of described Logic judgment electronic circuit to input carry out logic analysis, export judged result.
Preferably, within the T1 time that system electrification starts, described timer controls described switch and disconnects, and in time T1-T2, described timer controls described switch and closes, and after time t 2, described timer controls described switch and disconnects.
Preferably, described first resistance is equal with the resistance of the second resistance, and the resistance of described 3rd resistance is 1/4th of described first resistance.
Compared with prior art, the system of sense terminals load of the present invention contrasts described first respectively by contrast and detects the magnitude of voltage that electronic circuit and second detects comparer two input end of electronic circuit, accurately can judge whether described receiving terminal circuit is connected with load, therefore, the system of sense terminals load of the present invention can sense terminals load accurately and rapidly, and structure is simple, shared chip area is little, low in energy consumption.
By following description also by reference to the accompanying drawings, the present invention will become more clear, and these accompanying drawings are for explaining embodiments of the invention.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the system of sense terminals load of the present invention.
Fig. 2 is the circuit diagram that the system first of sense terminals load of the present invention detects electronic circuit.
Fig. 3 is the change in voltage figure that the system first of sense terminals load of the present invention detects electronic circuit node n.
Embodiment
With reference now to accompanying drawing, describe embodiments of the invention, element numbers similar in accompanying drawing represents similar element.As mentioned above, the invention provides a kind of system of sense terminals load, this system can sense terminals load accurately and rapidly, and structure is simple, and shared chip area is little, low in energy consumption.
Please refer to Fig. 1, Fig. 1 is the structured flowchart of the system of sense terminals load of the present invention.As shown in the figure, whether the system of sense terminals load of the present invention, be connected with load for sense terminals in high-speed differential signal transmitting procedure, and it comprises transmitting terminal driving circuit, load detecting circuit, receiving terminal circuit and two electric capacity C1, C2; Electric capacity C1, C2 described in two are connected between described transmitting terminal driving circuit and receiving terminal circuit, respectively in order to transmitting two paths differential signal between described transmitting terminal driving circuit and receiving terminal circuit, described load detecting circuit to be connected to described in described transmitting terminal driving circuit and two between electric capacity C1, C2, is used for detecting receiving terminal circuit (terminal) and whether is connected with load.
Particularly, please combine with reference to figure 2, described load detecting circuit comprises the first detection electronic circuit and second and detects electronic circuit again.Described first detects electronic circuit is connected between described transmitting terminal driving circuit and an electric capacity C1, and the node be connected with described electric capacity C1 is Txp, described second detects electronic circuit is connected between described transmitting terminal driving circuit and another electric capacity C2, and the node be connected with described electric capacity C2 is Txn, namely described first detection electronic circuit and second detects electronic circuit and is connected to described transmitting terminal driving circuit on the transmission channel of a road differential signal of described receiving terminal circuit.Described first detects electronic circuit comprises direct supply V
dd, the first resistance R1, the second resistance R2, the 3rd resistance R3, K switch 1, timer (not shown), current source I1, reference resistance R
refand comparer COMP; One end of described first resistance R1 and the 3rd resistance R3 all with direct supply V
ddconnect, the other end of described first resistance R1, one end of the second resistance R2, one end of K switch 1, one end of an electric capacity C1 jointly connect, and form node Txp, and described node Txp is connected with the reverse input end of described comparer COMP; The other end of described 3rd resistance R3 is connected with the other end of described K switch 1, the other end ground connection of described second resistance R2, and described timer controls closing/closing of described K switch 1 according to setting-up time timing; One end of described current source I1, reference resistance R
refone end jointly connect, and form node det, described node det is connected with the positive input of described comparer COMP, and the other end of described current source I1 is connected with the control end of described comparer COMP, thus described comparer COMP is by the described reference resistance R of contrast
refthe voltage (voltage of node det) at two ends and the voltage of node Txp and export the first testing result by its output terminal.Described second detects electronic circuit has and detects the identical architectural feature of electronic circuit with first, difference is only, described second detects electronic circuit is connected between described transmitting terminal driving circuit and described electric capacity C2, and the described second output terminal detecting the comparer of electronic circuit exports the second testing result, the architectural feature no longer detecting electronic circuit to second at this is carefully stated.As a preferred embodiment of the present invention, described load detecting circuit also comprises a Logic judgment electronic circuit (not shown), described first testing result and the second testing result all input described Logic judgment electronic circuit, two testing results of described Logic judgment electronic circuit to input carry out logic analysis, export judged result; Thus by exporting judged result accurately to the logic analysis of two testing results, make when there being one to make a mistake in two testing results, still exportable judged result accurately after described Logic judgment electronic circuit, to ensure precision and the accuracy of testing result.
In a preferred embodiment of the invention, within the T1 time that system electrification starts, described timer controls described K switch 1 and disconnects, in time T1-T2, described timer controls described K switch 1 and closes, and described timer controls described K switch 1 and disconnects after time t 2; In embody rule of the present invention, the time, T1, T2 can set according to the design parameter of the system of sense terminals load; Wherein, node Txp change in voltage in time as shown in Figure 3, when A curve represents that receiving terminal circuit is connected with load, the change in voltage situation of node Txp, when B curve represents that receiving terminal circuit does not connect load, the change in voltage situation of node Txp.Further, in the present invention, described first resistance R1 is equal with the resistance of the second resistance R2, i.e. R1=R2, and the resistance of described 3rd resistance R3 is 1/4th, i.e. R3=R1/4=R2/4 of described first resistance R1 resistance.
Under request in person again combine with reference to figure 2 and Fig. 3, the principle of work of the system of sense terminals load of the present invention is described.
One, when receiving terminal circuit does not connect load (terminator):
Ac coupling capacitor C1 is in open circuit, and owing to not having the effect of electric capacity, first detects electronic circuit upon power-up of the system in the T1 time, and timer described in this time period controls described K switch 1 and disconnects, the voltage V of node Txp
txpfor:
Due to now, comparer COMP does not open, wouldn't positive input voltage (voltage of the node det) V of comparison node Txp and comparer COMP
det.
Wherein, the voltage of the positive input of comparer COMP is:
Within the T1-T2 time period, timer controls described K switch 1 and closes, the voltage V of node Txp
hifor:
Now comparer COMP starts working, and because of R1=R2, can be drawn: V by contrast (3) formula with (2) formula
det< V
hi, therefore the output terminal of comparer COMP exports the first testing result outa is low, shows that described first detects electronic circuit and terminator do not detected, and the first testing result outa is inputed to described Logic judgment electronic circuit; It is identical that described second detection electronic circuit detects electronic circuit to the Cleaning Principle of another road differential signal path and described first, the second testing result outb that its comparer exports the most at last exports described Logic judgment electronic circuit to, thus by Logic judgment electronic circuit to the process of two comparative result outa and outb, export final detection result, thus pass through the Output rusults of described Logic judgment electronic circuit, can judge that described receiving terminal circuit does not connect load.
Two, when receiving terminal circuit is connected with terminator Rxn and Rxp:
Now receiving end driving circuit is that terminator Rxp provides stable common mode voltage V
com, and in the present invention,
then, by the known V of (2) formula
com< V
det.
And require that the first detection electronic circuit must, upon power-up of the system in the T1 time, charge to the forward end of ac coupling capacitor C1, make the voltage of node Txp reach the common mode voltage V with terminator end
comequal.Now described timer controls described switch k1 and disconnects.The now voltage V of node Txp
txpfor:
V in formula
0during for system electrification, the initial voltage of node Txp, its value is 0.
V
tfor the magnitude of voltage of node Txp after system stability, and
The resistance of whole circuit when Re is alternating current equivalent
The duration of charging of T needed for electric capacity C1, T≤T1
Therefore above formula is reduced to
Due to T1>>R
e× C
1, therefore when T1, the voltage stabilization of node Txp is at V
com.
Within the T1-T2 time period, described timer controls described K switch 1 and closes, and now continues to charge to ac coupling capacitor C1, but now, due to the effect of the 3rd resistance R3, the voltage of node Txp at this moment between section be:
R
efor resistance during alternating current equivalent
The time interval between usual T1-T2 is very short, and by the conventional design of those skilled in the art usually by this time interval value is:
Δt＝T
2-T
1＝0.08·R
1·C
1(10)
According to (8), (10) formula, the voltage obtaining egress Txp at the voltage of T2 time point is:
V
p≈0.6588·V
dd(11)
Known by (2) formula and (11) formula, the now voltage V of node Txp
pbe less than V
det, and now because comparer COMP works, therefore the first testing result outa that comparer exports is high level, shows that described first detection electronic circuit detects terminator, and the first testing result outa is inputed to described Logic judgment electronic circuit; It is identical that described second detection electronic circuit detects electronic circuit to the Cleaning Principle of another road differential signal path and described first, the second testing result outb that its comparer exports the most at last exports described Logic judgment electronic circuit to, thus by Logic judgment electronic circuit to the process of two testing result outa and outb, export final detection result, thus pass through the Output rusults of described Logic judgment electronic circuit, can judge that described receiving terminal circuit is connected with load
In the present invention, no matter whether receiving terminal circuit is connected with load, after time T2, in order to ensure the correctness of the testing result that described Logic judgment electronic circuit exports, described first detects electronic circuit and second detects the comparer of electronic circuit and Logic judgment electronic circuit does not all work, now described timer controls described switch k1 and disconnects, and the quick changes in voltage of node Txp is the voltage before the T1 moment, to prepare the testing of next round.
From the above, by the voltage contrasting node Txp and node det in time T1-T2, the system of sense terminals load of the present invention can judge whether described receiving terminal circuit is connected with load, therefore can sense terminals load rapidly, and structure is simple, shared chip area is little, low in energy consumption; In addition, by described logic subcircuit, the analysis again that the first detection electronic circuit and second detects the testing result that electronic circuit exports is judged, ensure that the accuracy of testing result.
More than in conjunction with most preferred embodiment, invention has been described, but the present invention is not limited to the embodiment of above announcement, and should contain various carry out according to essence of the present invention amendment, equivalent combinations.
Claims (4)
1. the system of a sense terminals load, whether load is connected with for sense terminals in high-speed differential signal transmitting procedure, comprise transmitting terminal driving circuit, load detecting circuit, receiving terminal circuit and two electric capacity, electric capacity described in two is connected between described transmitting terminal driving circuit and receiving terminal circuit, described load detecting circuit to be connected to described in described transmitting terminal driving circuit and two between electric capacity, it is characterized in that, described load detecting circuit comprises the first detection electronic circuit and second and detects electronic circuit, described first detects electronic circuit is connected between described transmitting terminal driving circuit and an electric capacity, described second detects electronic circuit is connected between described transmitting terminal driving circuit and another electric capacity, and described two electric capacity are respectively in order to transmitting two paths differential signal between described transmitting terminal driving circuit and receiving terminal circuit, described first detects electronic circuit comprises direct supply, first resistance, second resistance, 3rd resistance, switch, timer, current source, reference resistance and comparer, described first resistance is all connected with direct supply with one end of the 3rd resistance, the other end of described first resistance, one end of second resistance, one end of switch, one end of one electric capacity is all connected with the reverse input end of described comparer, the other end of described 3rd resistance is connected with the other end of described switch, the other end ground connection of described second resistance, described timer controls closing/closing of described switch according to setting-up time timing, one end of described current source, one end of reference resistance is all connected with the positive input of described comparer, the other end of described current source is connected with the control end of described comparer, the output terminal of described comparer exports the first testing result, described second detects electronic circuit has and detects the identical architectural feature of electronic circuit with first, and the described second output terminal detecting the comparer of electronic circuit exports the second testing result.
2. the system of sense terminals load as claimed in claim 1, it is characterized in that, described load detecting circuit also comprises a Logic judgment electronic circuit, described first testing result and the second testing result all input described Logic judgment electronic circuit, two testing results of described Logic judgment electronic circuit to input carry out logic analysis, export judged result.
3. the system of sense terminals load as claimed in claim 1, it is characterized in that, within the T1 time that system electrification starts, described timer controls described switch and disconnects, in time T1-T2, described timer controls described switch and closes, and after time t 2, described timer controls described switch and disconnects.
4. the system of sense terminals load as claimed in claim 3, it is characterized in that, described first resistance is equal with the resistance of the second resistance, and the resistance of described 3rd resistance is 1/4th of described first resistance.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410453527.XA CN104375547B (en) | 2014-09-05 | 2014-09-05 | The system of sense terminals load |
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|---|---|---|---|
| CN201410453527.XA CN104375547B (en) | 2014-09-05 | 2014-09-05 | The system of sense terminals load |
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| CN104375547B true CN104375547B (en) | 2016-01-06 |
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| JP6695574B2 (en) * | 2016-07-29 | 2020-05-20 | ザインエレクトロニクス株式会社 | Transmission device and transmission / reception system |
| CN109116902A (en) * | 2017-06-22 | 2019-01-01 | 台达电子工业股份有限公司 | Judging unit and its control method, power supply device and its control method |
| CN113311230B (en) * | 2020-02-27 | 2022-12-06 | 成都纳能微电子有限公司 | Terminal impedance detection circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1128927A (en) * | 1994-09-30 | 1996-08-14 | 美国电报电话公司 | Testing circuit for loading terminals |
| WO2010038480A1 (en) * | 2008-10-02 | 2010-04-08 | ホーチキ株式会社 | Transmission input circuit |
| CN201509235U (en) * | 2009-09-25 | 2010-06-16 | 宇龙计算机通信科技(深圳)有限公司 | Headphone detection circuit of mobile terminal and mobile terminal thereof |
| JP2011254475A (en) * | 2010-06-01 | 2011-12-15 | Toshiba Corp | Alteration detection apparatus and alteration detection method |
-
2014
- 2014-09-05 CN CN201410453527.XA patent/CN104375547B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1128927A (en) * | 1994-09-30 | 1996-08-14 | 美国电报电话公司 | Testing circuit for loading terminals |
| WO2010038480A1 (en) * | 2008-10-02 | 2010-04-08 | ホーチキ株式会社 | Transmission input circuit |
| CN201509235U (en) * | 2009-09-25 | 2010-06-16 | 宇龙计算机通信科技(深圳)有限公司 | Headphone detection circuit of mobile terminal and mobile terminal thereof |
| JP2011254475A (en) * | 2010-06-01 | 2011-12-15 | Toshiba Corp | Alteration detection apparatus and alteration detection method |
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