CN104375079A - Chip - Google Patents
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- CN104375079A CN104375079A CN201410625284.3A CN201410625284A CN104375079A CN 104375079 A CN104375079 A CN 104375079A CN 201410625284 A CN201410625284 A CN 201410625284A CN 104375079 A CN104375079 A CN 104375079A
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Abstract
The invention provides a chip which comprises testing modules used for testing the chip. The chip is characterized in that the chip further comprises an encrypted circuit and a test control circuit, the encrypted circuit receives input passwords from the outside, compares the received input passwords with preset passwords and outputs a test control signal to the test control circuit according to a comparison result, and the test control circuit receives a testing module selecting signal and outputs a test signal to the testing module according to the testing module selecting signal and the test control signal, so that testing of the chip is controlled.
Description
Technical field
The present invention relates to semiconductor applications, more particularly, relate to a kind of chip comprising test module.
Background technology
Along with the development of semiconductor technology, the chip that more and more can realize difference in functionality is applied in the electronic equipments such as such as mobile phone, notebook computer, panel computer.Therefore, in order to ensure that the chip produced can realize the function of expecting, before chip is installed to electronic equipment, need comprehensively to test chip.
At present, in order to the kernel information of protect IC, the test of chip usually can be completed before being encapsulated by chip.Further, when encapsulating chip, the test pin of chip is not connected in outer enclosure.That is, user can not find the pin being connected to test pattern in the outer enclosure of chip, also just cannot enter the kernel of chip.But after user removes the outer enclosure of chip, the test pin of chip will be exposed to outside.
Fig. 1 illustrates the schematic diagram of existing chip.As shown in Figure 1, existing chip 100 comprises: for the decode logic 10, the test module 20 for test chip kernel portion, the kernel 30 that process the signal of selection test module.As shown in Figure 1, when chip does not have outer enclosure, user can by the test pin input of chip for selecting the signal of test module to decode logic 10, signal after process can be outputted to test module 20 by decode logic 10, to choose test module 20, afterwards, user just can enter into the kernel 30 of chip by test module 20, and then learn the kernel information of chip, thus cause safety problem.
Therefore, existing chip can not meet the demand of the kernel information of protect IC.
Summary of the invention
The object of the present invention is to provide a kind of chip, thus can the kernel information of protect IC effectively.
The invention provides a kind of chip, described chip comprises the test module for testing chip, it is characterized in that, described chip also comprises: encrypted circuit, test control circuit, wherein, encrypted circuit inputs password from external reception, the input password of reception and prescribed password are compared, and export test control signal to test control circuit according to comparative result, test control circuit receives test module and selects signal, and select signal and test control signal to export test signal to test module, to control the test to chip based on test module.
Alternatively, test control signal comprises testing and control enable signal and testing and control disable signal, test module is selected signal to comprise and is selected enable signal and selection disable signal, test signal comprises test enable signal for allowing test module to test chip and for forbidding the test disable signal that test module is tested chip, wherein, when inputting password and being identical with described prescribed password, encrypted circuit exports testing and control enable signal to test control circuit; When inputting password and being different from described prescribed password, encrypted circuit exports testing and control disable signal to test control circuit, wherein, test control circuit exports test enable signal to test module based on selection enable signal and testing and control enable signal, wherein, test control circuit exports test disable signal to test module based on selection disable signal and testing and control enable signal, selects signal and testing and control disable signal to export test disable signal to test module based on test module.
Alternatively, described chip comprises multiple test module, and described test control circuit comprises multiple test control circuit unit, wherein, each test control circuit unit corresponds to a test module, and each test module receives test signal from corresponding test control circuit unit.
Alternatively, test control signal comprises testing and control enable signal and testing and control disable signal, described prescribed password comprises at least one grade password, and, each grade password corresponds at least one test module, wherein, input password compares with each grade password by encrypted circuit respectively, determine whether there is the grade password identical with input password at least one grade password described, when there is the grade password identical with input password at least one grade password described, the test control circuit unit that the test module that testing and control enable signal outputs to by encrypted circuit with the grade codon pair existed is answered is corresponding respectively, and test control circuit unit testing and control disable signal outputted to except receiving the test control circuit unit of testing and control enable signal, when there is not the grade password identical with input password at least one password described, testing and control disable signal is outputted to all test control circuit unit by encrypted circuit.
Alternatively, described test control circuit unit is and door, wherein, receives test module respectively select signal and test control signal with door, and select signal and test control signal to carry out and computing the test module received, export test signal to corresponding test module.
Alternatively, also comprise: storer, store described prescribed password.
Alternatively, storer also stores predetermined cryptographic algorithm and secret key, and wherein, encrypted circuit comprises: cryptography processing units, from external reception input password, and based on the cryptographic algorithm stored and secret key, the input password of reception is converted to additive cipher; Comparing unit, compares the described prescribed password of additive cipher and storage, and exports test control signal to test control circuit according to comparative result.
Alternatively, described predetermined cryptographic algorithm is in DES algorithm, MD5 algorithm and RSA Algorithm.
According to chip of the present invention; can be encrypted by test module to chip by encrypted circuit and test control circuit; when the outer enclosure of chip is removed; because user does not know the password entering test pattern; also just chip core part is not entered by test pattern, thus can the kernel information of protect IC effectively.
Accompanying drawing explanation
By the detailed description of carrying out below in conjunction with accompanying drawing, above and other objects, features and advantages of the present invention will become apparent, wherein:
Fig. 1 illustrates the schematic diagram of existing chip.
Fig. 2 illustrates the schematic diagram of the chip according to exemplary embodiment of the present invention.
Fig. 3 illustrates the block diagram according to the encrypted circuit in the chip of Fig. 2 of exemplary embodiment of the present invention.
Fig. 4 illustrates the schematic diagram comprising the chip of multiple test module according to exemplary embodiment of the present invention.
Embodiment
Now, describe different example embodiment more fully with reference to the accompanying drawings, wherein, some exemplary embodiments are shown in the drawings, and wherein, identical label represents identical parts all the time.
Fig. 2 shows the schematic diagram of the chip according to exemplary embodiment of the present invention.
As shown in Figure 2, except the decode logic 10 shown in Fig. 1, test module 20, kernel 30, the chip 200 according to exemplary embodiment of the present invention also comprises: encrypted circuit 40, test control circuit 50.
Specifically, the input password PW of reception and prescribed password, for from external reception input password PW, compare, and export test control signal TCS to test control circuit 50 according to comparative result by encrypted circuit 40.
Exemplarily, the test control signal TCS that encrypted circuit 40 exports can comprise testing and control enable signal TCS-ON and testing and control disable signal TCS-OFF.When encrypted circuit 40 is identical with prescribed password from the input password PW of external reception, encrypted circuit 40 exports testing and control enable signal TCS-ON to test control circuit 50; When inputting password PW and being different from described prescribed password, encrypted circuit 40 exports testing and control disable signal TCS-OFF to test control circuit 50.
As preferred exemplary, conveniently obtaining the above-mentioned prescribed password mentioned, also can comprising the storer for storing described prescribed password according to the chip of exemplary embodiment of the present invention.
In addition, in order to improve the decoding difficulty of password, the original password arranged at first can not be stored in memory as described prescribed password, and original password is changed by predetermined cryptographic algorithm and secret key, the original password after conversion is stored in memory as described prescribed password.Therefore, as preferred exemplary, storer also can store cryptographic algorithm for changing original password (that is, for obtaining described prescribed password) and secret key.Exemplarily, described predetermined cryptographic algorithm is in DES algorithm, MD5 algorithm and RSA Algorithm.
Here, storer can be circuit, the device of any power down that can realize memory function not obliterated data, such as, and ROM (read-only memory) (ROM), flash memory (Flash Memory) etc.
Fig. 3 illustrates the block diagram according to the encrypted circuit 40 in the chip 200 of Fig. 2 of exemplary embodiment of the present invention.
As shown in Figure 3, the encrypted circuit 40 in chip 200 comprises: cryptography processing units 41, comparing unit 42.
The input password PW of reception for inputting password PW from external reception, and is converted to additive cipher based on the cryptographic algorithm stored and secret key by cryptography processing units 41.Here, cryptography processing units 41, by the conversion regime identical with conversion original password, utilizes the cryptographic algorithm of storage and secret key that the input password PW of reception is converted to additive cipher.
Comparing unit 42 for the described prescribed password of additive cipher and storage being compared, and exports test control signal TCS to test control circuit 50 according to comparative result.Such as, when additive cipher is identical with the described prescribed password of storage, comparing unit 42 exports testing and control enable signal TCS-ON to test control circuit 50, when additive cipher is different from described prescribed password, comparing unit 42 exports testing and control disable signal TCS-OFF to test control circuit 50.
Referring again to Fig. 2, test control circuit 50 selects signal TMS for receiving test module, and select signal TMS and test control signal TCS to export test signal TS to test module 20, to control the test (that is, to the test of the kernel 30 of chip) to chip based on test module.
Exemplarily, test module is selected signal TMS to comprise to select enable signal TMS-ON and select disable signal TMS-OFF, and test signal TS can comprise test enable signal TS-ON for allowing test module 20 pairs of chips to test and for forbidding the test disable signal TS-OFF that test module 20 pairs of chips are tested.
Test control circuit 50 can export test enable signal TS-ON to test module 20 based on selection enable signal TMS-ON and testing and control enable signal TCS-ON, tests to allow test module 20 pairs of chips.
Test control circuit 50 also can export test disable signal TS-OFF to test module 20 based on selection disable signal TMS-OFF and testing and control enable signal TCS-ON; Signal TMS and testing and control disable signal TCS-OFF is selected to export test disable signal TS-OFF to test module 20, to forbid that test module 20 pairs of chips are tested based on test module.
In addition, along with chip core 30 part becomes increasingly complex, when testing chip, multiple test module (such as, jtag test module (boundary scan testing), SCAN test module (sweep test), BIST test module (selftest), macro test module (utilizing grand test) etc.) is often needed more fully to test chip.According to chip of the present invention, when chip comprises multiple test module, the test control circuit 50 of chip can comprise multiple test control circuit unit, and, each test control circuit unit may correspond in a test module, and each test module receives test signal TS from corresponding test control circuit unit.
Fig. 4 illustrates the schematic diagram comprising the chip of multiple test module according to exemplary embodiment of the present invention.
As shown in Figure 4, except the decode logic 10 shown in Fig. 2, kernel 30, encrypted circuit 40, chip 300 also comprises n test module (test module 20-1 is to test module 20-n), a n test control circuit unit (test control circuit unit 50-1 is to test control circuit unit 50-n), n be greater than 1 integer.Further, each test control circuit unit corresponds to a test module, and each test module receives test signal TS from corresponding test control circuit unit.Such as, the 1st test control circuit unit 50-1 corresponds to the 1st test module 20-1, and the 1st test module 20-1 receives test signal TS from the 1st test control circuit unit 50-1; 2nd test control circuit unit 50-2 corresponds to the 2nd test module 20-2, and the 2nd test module 20-2 receives test signal TS from the 2nd test control circuit unit 50-2; 3rd test control circuit unit 50-3 corresponds to the 3rd test module 20-3, and the 3rd test module 20-3 receives test signal TS from the 3rd test control circuit unit 50-3; Similarly, the n-th test control circuit unit 50-n corresponds to the n-th test module 20-n, the n-th test module 20-n and receives test signal TS from the n-th test control circuit unit 50-n.
Exemplarily, the test control signal TCS that encrypted circuit 40 exports comprises testing and control enable signal TCS-ON and testing and control disable signal TCS-OFF.Preferably, the above-mentioned prescribed password mentioned can comprise at least one grade password, and each grade password corresponds at least one test module.Such as, first grade password in multiple grade password corresponds to first test module 20-1, and second grade password corresponds to second test module 20-2, the 3rd test module 20-3 and the n-th test module 20-n etc.
In this case, input password PW can compare with each grade password by encrypted circuit 40 respectively, determines whether there is the grade password identical with input password PW at least one grade password described:
When there is the grade password identical with input password PW at least one grade password described, the test module that testing and control enable signal TCS-ON outputs to the grade codon pair existed is answered is distinguished corresponding test control circuit unit by encrypted circuit 40, and testing and control disable signal TCS-OFF is outputted to the test control circuit unit except receiving the test control circuit unit of testing and control enable signal TCS-ON.Such as, the test module that the grade codon pair identical with input password PW existed is answered is respectively: test module 20-2, test module 20-3, test module 20-n, the test control circuit unit that test module 20-2 is corresponding is 50-2, the test control circuit unit that test module 20-3 is corresponding is 50-3, and the test control circuit unit that test module 20-n is corresponding is 50-n.So, testing and control enable signal TCS-ON is outputted to test control circuit unit 50-2, test control circuit unit 50-3 and test control circuit unit 50-n by encrypted circuit 40, and testing and control disable signal TCS-OFF is outputted to the test control circuit unit except test control circuit unit 50-2, test control circuit unit 50-3 and test control circuit unit 50-n.
When there is not the grade password identical with input password at least one password described, testing and control disable signal TCS-OFF is outputted to all test control circuit unit by encrypted circuit 40.
As preferred exemplary, the above-mentioned test control circuit unit mentioned can be and door.Here, test module can be received respectively with door and select signal TMS and test control signal TCS, and select signal TMS and test control signal TCS to carry out and computing the test module received, export test signal TS to corresponding test module.
Should be appreciated that, when test control circuit is with door, select enable signal TMS-ON, testing and control enable signal TCS-ON, test enable signal TS-ON should be all 1, select disable signal TMS-OFF, testing and control disable signal TCS-OFF, test disable signal TS-OFF should be all 0, and, when the test module received with door selects signal TMS for select enable signal TMS-ON=1, when the test control signal TCS received is testing and control enable signal TCS-ON=1, test enable signal TS-ON=1 is exported to corresponding test module to Men Caihui, otherwise, all disable signal TS-OFF=0 is tested to corresponding test module by exporting to door.
Should be appreciated that, test control circuit unit of the present invention is not limited to and door.Different according to the form of the signal being input to test control circuit unit, also realize test control circuit unit by other modes.Such as, when the signal being input to test control circuit unit is when selecting enable signal TMS-ON=0 and testing and control enable signal TCS-ON=0, test control circuit unit can be implemented as rejection gate, now, test enable signal TS-ON, selection disable signal TMS-OFF, testing and control disable signal TCS-OFF should be all 1, and test disable signal TS-OFF should be 0.
In addition, test control circuit unit also can be implemented as circuit, the device that special Programmable Logic Controller, special chip etc. have controlling functions.
According to chip of the present invention; can be encrypted by test module to chip by encrypted circuit and test control circuit; when the outer enclosure of chip is removed; user does not know the password entering test pattern; also just chip core part is not entered by test pattern, thus can the kernel information of protect IC effectively.
Although specifically show with reference to its exemplary embodiment and describe the present invention, but it should be appreciated by those skilled in the art, when not departing from the spirit and scope of the present invention that claim limits, the various changes in form and details can be carried out to it.
Claims (8)
1. a chip, described chip comprises the test module for testing chip, it is characterized in that, described chip also comprises: encrypted circuit, test control circuit,
Wherein, encrypted circuit inputs password from external reception, the input password of reception and prescribed password is compared, and exports test control signal to test control circuit according to comparative result,
Test control circuit receives test module and selects signal, and selects signal and test control signal to export test signal to test module, to control the test to chip based on test module.
2. chip as claimed in claim 1, it is characterized in that, test control signal comprises testing and control enable signal and testing and control disable signal, test module is selected signal to comprise and is selected enable signal and selection disable signal, test signal comprises test enable signal for allowing test module to test chip and for forbidding the test disable signal that test module is tested chip
Wherein, when inputting password and being identical with described prescribed password, encrypted circuit exports testing and control enable signal to test control circuit; When inputting password and being different from described prescribed password, encrypted circuit exports testing and control disable signal to test control circuit,
Wherein, test control circuit exports test enable signal to test module based on selection enable signal and testing and control enable signal,
Wherein, test control circuit exports test disable signal to test module based on selection disable signal and testing and control enable signal, selects signal and testing and control disable signal to export test disable signal to test module based on test module.
3. chip as claimed in claim 1, it is characterized in that, described chip comprises multiple test module, described test control circuit comprises multiple test control circuit unit, wherein, each test control circuit unit corresponds to a test module, and each test module receives test signal from corresponding test control circuit unit.
4. chip as claimed in claim 3, it is characterized in that, test control signal comprises testing and control enable signal and testing and control disable signal, described prescribed password comprises at least one grade password, further, each grade password corresponds at least one test module
Wherein, input password compares with each grade password by encrypted circuit respectively, determines whether there is the grade password identical with input password at least one grade password described,
When there is the grade password identical with input password at least one grade password described, the test control circuit unit that the test module that testing and control enable signal outputs to by encrypted circuit with the grade codon pair existed is answered is corresponding respectively, and test control circuit unit testing and control disable signal outputted to except receiving the test control circuit unit of testing and control enable signal
When there is not the grade password identical with input password at least one password described, testing and control disable signal is outputted to all test control circuit unit by encrypted circuit.
5. chip as claimed in claim 3, it is characterized in that, described test control circuit unit is and door, wherein,
Receive test module respectively with door and select signal and test control signal, and select signal and test control signal to carry out and computing the test module received, export test signal to corresponding test module.
6. chip as claimed in claim 1, also comprises:
Storer, stores described prescribed password.
7. chip as claimed in claim 6, it is characterized in that, storer also stores predetermined cryptographic algorithm and secret key,
Wherein, encrypted circuit comprises:
Cryptography processing units, from external reception input password, and is converted to additive cipher based on the cryptographic algorithm stored and secret key by the input password of reception;
Comparing unit, compares the described prescribed password of additive cipher and storage, and exports test control signal to test control circuit according to comparative result.
8. chip as claimed in claim 7, it is characterized in that, described predetermined cryptographic algorithm is one in DES algorithm, MD5 algorithm and RSA Algorithm.
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| CN201410625284.3A CN104375079B (en) | 2014-11-07 | 2014-11-07 | Chip |
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| CN201410625284.3A CN104375079B (en) | 2014-11-07 | 2014-11-07 | Chip |
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| CN104375079A true CN104375079A (en) | 2015-02-25 |
| CN104375079B CN104375079B (en) | 2018-03-27 |
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| CN107783028A (en) * | 2017-10-16 | 2018-03-09 | 苏州国芯科技有限公司 | A kind of chip enters the control method and system of test pattern |
| CN108196181A (en) * | 2017-12-18 | 2018-06-22 | 上海艾为电子技术股份有限公司 | A kind of chip test mode access method, into system and chip |
| CN108875413A (en) * | 2017-05-12 | 2018-11-23 | 晨星半导体股份有限公司 | Functional circuit enable method and the chip for applying it |
| CN112044374A (en) * | 2020-09-01 | 2020-12-08 | 杨欢 | Chip for chain polymerization based on microfluidic technology |
| CN113055173A (en) * | 2021-04-02 | 2021-06-29 | 深圳市嘉兴南电科技有限公司 | Transient suppression protection chip for 5G communication equipment |
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| JP2004257898A (en) * | 2003-02-26 | 2004-09-16 | Renesas Technology Corp | Device for testing semiconductor integrated circuit and method of manufacturing semiconductor integrated circuit using same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108875413A (en) * | 2017-05-12 | 2018-11-23 | 晨星半导体股份有限公司 | Functional circuit enable method and the chip for applying it |
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| CN108196181A (en) * | 2017-12-18 | 2018-06-22 | 上海艾为电子技术股份有限公司 | A kind of chip test mode access method, into system and chip |
| CN112044374A (en) * | 2020-09-01 | 2020-12-08 | 杨欢 | Chip for chain polymerization based on microfluidic technology |
| CN113055173A (en) * | 2021-04-02 | 2021-06-29 | 深圳市嘉兴南电科技有限公司 | Transient suppression protection chip for 5G communication equipment |
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| Publication number | Publication date |
|---|---|
| CN104375079B (en) | 2018-03-27 |
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