CN104375047B - A kind of verifying attachment of analog input combining unit phase accuracy - Google Patents
A kind of verifying attachment of analog input combining unit phase accuracy Download PDFInfo
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- CN104375047B CN104375047B CN201410758809.0A CN201410758809A CN104375047B CN 104375047 B CN104375047 B CN 104375047B CN 201410758809 A CN201410758809 A CN 201410758809A CN 104375047 B CN104375047 B CN 104375047B
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Abstract
The invention discloses a kind of verifying attachment of analog input combining unit phase accuracy, it is mainly made up of CPU, on-site programmable gate array FPGA, ethernet mac, ethernet PHY, Ethernet fiber optic receiver, universal optical fibre receiver, D/A converter, temperature compensating crystal oscillator, low pass filter, A/D converter, precision transformer and local bus.The CPU, FPGA, A/D converter, D/A converter are interconnected by the local bus, and CPU enters line access by the local bus to the data of FPGA, A/D converter, D/A converter.Signal is to verifying attachment, combining unit to be measured and AC analogue signal source during external clock unit output light IRIG of the present invention B yards couple, make verifying attachment, combining unit synchronization to be measured, ensure that the frequency of AC analogue signal source is accurate simultaneously, so as to realize that phase accuracy is checked.
Description
Technical field
The present invention relates to a kind of verifying attachment of analog input combining unit phase accuracy, belong to power system relay
Protection inspection field.
Background technology
In intelligent substation, protection, monitoring, the sampling of metering system are the sides of routine transformer and combining unit of sampling
What formula was realized, sampling element is moved forward by devices such as original protection, observing and controlling, meterings and is distributed to the respectively combining unit sampled on the spot
Complete.Combining unit sampling is all needed by the link such as analog (A/D) conversion, data processing and transmission, it is necessary to when certain
Between.Therefore, the digital sample of intelligent substation eventually receives SV and needs necessarily from primary current, control source to protection device
Time delay.
Combining unit is according to transformer phase delay, wave filter time delay, the data delay of acquisition module, itself wait, place
Reason and the Time Calculation for sending go out time delay of the digital sample from a signal input to final output SV and (are defined as specified time delay
Te, in units of microsecond), and be contained in being sent together with SV in SV messages.Protection device receives multiple combining units
SV after, according to respective specified time delay and protect the clock signal of itself to carry out compensation of delay to sampled data, so as to obtain
Take the true samples moment of sampled point.Therefore, the degree of accuracy of specified time delay directly determines phase accuracy.
The content of the invention
Because specified time delay is made up of multiple links, it is difficult to pass through prior art means direct measurement.Therefore, mesh of the present invention
Be be that a kind of verifying attachment of analog input combining unit phase accuracy is provided, from the operation principle of combining unit and
The angle of external behavior set out and its phase accuracy is tested, it is to avoid to the direct measurement of specified time delay.
To achieve the above object, the present invention is realized using following technical scheme：
A kind of verifying attachment of analog input combining unit phase accuracy, it includes CPU processor, field-programmable
Gate array FPGA, ethernet mac, ethernet PHY, Ethernet fiber optic receiver, universal optical fibre receiver, D/A converter, constant temperature
Crystal oscillator, low pass filter, A/D converter, precision transformer and local bus part composition；CPU, FPGA, A/D conversion
Device, D/A converter are interconnected by the local bus, the CPU by the local bus to the FPGA, A/D converter,
The data of D/A converter enter line access；The precision transformer realizes primary voltage, electric current to the conversion of secondary voltage, and defeated
Go out secondary voltage to company and state the low pass filter；The low pass filter realizes anti-aliasing filter, and export it is filtered after
Secondary voltage to the A/D converter, low pass filter uses second-order low-pass filter, and cut-off frequency is 20kHz；The A/
D converters complete analog quantity to the conversion of digital quantity, and sample rate is 200kHz；The ethernet mac, for realizing ethernet frame
Assembling.
The CPU processor, the sampled value for obtaining combining unit from the ethernet mac, from D/A conversions
The sampled value obtained in device, obtains the transmission of sampling value message from effective digit pulse of the on-site programmable gate array FPGA
At the moment, the phase error of combining unit is calculated, and be compared with the requirement of professional standard, realize analog input combining unit
The inspection of phase accuracy；
The FPGA provides sampling pulse for the A/D converter；
The Ethernet fiber optic receiver will be converted into electric signal with the ethernet frame of optical signal transmission, and export to described
Ethernet PHY；The ethernet PHY realizes the conversion and serial/parallel conversion of signal level, and the signal output after conversion is extremely
The ethernet mac and the FPGA；
The universal optical fibre receiver will be converted into electric signal with the IRIG-B of optical signal transmission yards of signal, and export to institute
State FPGA；
The D/A converter outputs voltage signal to the constant-temperature crystal oscillator, and the constant-temperature crystal oscillator exports clock signal to institute
State FPGA；
The verifying attachment and combining unit to be measured access light IRIG-B yards of signal of external clock unit output, in same
Step state；The verifying attachment and the combining unit to be measured access same analog quantity voltage or current signal.
The verifying attachment and the combining unit to be measured carry out sampling/changing using same principle to same signal.
The class of accuracy of the precision transformer that the verifying attachment is used is 0.05 grade, than the combining unit to be measured
The class of accuracy of transformer is high 2 grades, therefore, the phase error caused by transformer is relatively small.
The sample frequency (200kHz) that the verifying attachment is used than the combining unit to be measured sample frequency (4~
12.8kHz) an order of magnitude high, the cut-off frequency (20kHz) of corresponding low pass filter is also than the cut-off of combining unit to be measured
Frequency (being less than 2kHz) an order of magnitude high, therefore, the phase error caused by anti-aliasing filter is relatively small.
The verifying attachment accurately records SV messages using FPGA by the way of ethernet PHY exit hardware beats timestamp
The time of reception.
Signal is to verifying attachment, combining unit to be measured and exchanges during external clock unit output light of the present invention IRIG-B yards pair
Simulation signal generator, makes verifying attachment, combining unit synchronization to be measured, while ensureing that the frequency of AC analogue signal source is accurate.It is to be measured
Combining unit output is sampled, the SV messages after conversion and treatment to verifying attachment, when verifying attachment is to the reception of SV messages
Carve and its comprising sampled value recorded and analyzed.A same analog signalses of AC analogue signal source output are simultaneously
Verifying attachment, combining unit to be measured are accessed, equivalent to parallel connection for primary voltage, equivalent to series connection for primary current,
So as to realize that phase accuracy is checked.
Brief description of the drawings
Fig. 1 is the system wiring figure for checking combining unit phase accuracy；
Fig. 2 is the structured flowchart of verifying attachment of the present invention.
Specific embodiment
For technological means, creation characteristic, reached purpose and effect for making present invention realization are easy to understand, with reference to
Specific embodiment, is expanded on further the present invention.
Fig. 1 is the system wiring figure for checking combining unit phase accuracy.
Signal to verifying attachment, combining unit to be measured and AC analogue is believed during external clock unit output light IRIG-B yards pair
Number source, makes verifying attachment, combining unit synchronization to be measured, while ensureing that the frequency of AC analogue signal source is accurate.It is to be measured to merge single
Unit's output is sampled, the SV messages after conversion and treatment to verifying attachment, verifying attachment to time of reception of SV messages and its
Comprising sampled value recorded and analyzed.A same analog signalses of AC analogue signal source output access inspection simultaneously
Experiment device, combining unit to be measured, equivalent to parallel connection for primary voltage, equivalent to series connection for primary current.
Fig. 2 is the structured flowchart of verifying attachment.
The verifying attachment is main by CPU, on-site programmable gate array FPGA, ethernet mac, ethernet PHY, Ethernet
Fiber optic receiver, universal optical fibre receiver, D/A converter, constant-temperature crystal oscillator, low pass filter, A/D converter, precision transformer
And the part such as local bus constitutes.
The CPU, FPGA, A/D converter, D/A converter are interconnected by the local bus, and the CPU is by described
Local bus enter line access to the data of the FPGA, A/D converter, D/A converter.The ethernet mac, for realize with
The too assembling of net frame.
Precision transformer, realizes primary voltage, electric current to the conversion of secondary voltage, and it is described to even stating to export secondary voltage
Low pass filter；
The precision transformer is used to receive the analog quantity voltage or electric current same with the combining unit access to be measured
Signal, realizes primary voltage, electric current to the conversion of secondary voltage, and exports secondary voltage to even stating the low pass filter；Institute
State low pass filter and realize anti-aliasing filter, and export it is filtered after secondary voltage to the A/D converter, LPF
Device uses second order Butterworth filter, and cut-off frequency is 20kHz；The A/D converter completes analog quantity turning to digital quantity
Change, sample rate is 200kHz.
The FPGA provides sampling pulse for the A/D converter.
The Ethernet fiber optic receiver is used to receive combining unit to be measured with the ethernet frame of optical signal transmission, and will be with
The ethernet frame of optical signal transmission is converted into electric signal, and exports to the ethernet PHY；The ethernet PHY realizes signal
The conversion of level and serial/parallel are changed, the signal output after conversion to the ethernet mac and the FPGA.
The universal optical fibre receiver, for receiving external clock unit with IRIG-B yards of optical signal transmission, and will be with
IRIG-B yards of signal of optical signal transmission is converted into electric signal, and exports to the FPGA.The output of the external clock unit
End is also connected with combining unit to be measured, and the combining unit to be measured receives external clock unit with IRIG-B yards of optical signal transmission,
Ensure synchronous with the holding of universal optical fibre receiver.
The D/A converter outputs voltage signal to the constant-temperature crystal oscillator, and the constant-temperature crystal oscillator exports clock signal to institute
State FPGA.
The verifying attachment can realize being technically characterized in that for phase accuracy inspection：
The verifying attachment and combining unit to be measured access light IRIG-B yards of signal of external clock unit output, in same
Step state；The verifying attachment and the combining unit to be measured access same analog quantity voltage or current signal.
The verifying attachment and the combining unit to be measured carry out sampling/changing using same principle to same signal.
The class of accuracy of the precision transformer that the verifying attachment is used is than the transformer of the combining unit to be measured
Class of accuracy is high 2 grades, therefore, the phase error caused by transformer is relatively small.
The sample frequency (200kHz) that the verifying attachment is used than the combining unit to be measured sample frequency (4~
12.8kHz) an order of magnitude high, the cut-off frequency (20kHz) of corresponding low pass filter is also than the cut-off of combining unit to be measured
Frequency (being less than 2kHz) an order of magnitude high, therefore, the phase error caused by anti-aliasing filter is relatively small.
The verifying attachment accurately records SV messages using FPGA by the way of ethernet PHY exit hardware beats timestamp
The time of reception.
Signal is to verifying attachment, combining unit to be measured and exchanges during external clock unit output light of the present invention IRIG-B yards pair
Simulation signal generator, makes verifying attachment, combining unit synchronization to be measured, while ensureing that the frequency of AC analogue signal source is accurate.It is to be measured
Combining unit output is sampled, the SV messages after conversion and treatment to verifying attachment, when verifying attachment is to the reception of SV messages
Carve and its comprising sampled value recorded and analyzed.A same analog signalses of AC analogue signal source output are simultaneously
Verifying attachment, combining unit to be measured are accessed, equivalent to parallel connection for primary voltage, equivalent to series connection for primary current,
So as to realize that phase accuracy is checked.
General principle of the invention and principal character and advantages of the present invention has been shown and described above.The technology of the industry
Personnel it should be appreciated that the present invention is not limited to the above embodiments, simply explanation described in above-described embodiment and specification this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes
Change and improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention by appending claims and its
Equivalent thereof.
Claims (5)
1. a kind of verifying attachment of analog input combining unit phase accuracy, it is characterised in that including：Constant-temperature crystal oscillator；
D/A converter, for completing digital quantity to the conversion of analog quantity；
A/D converter, for completing analog quantity to the conversion of digital quantity；
On-site programmable gate array FPGA, for the A/D converter provides sampling pulse；
Low pass filter, for realizing anti-aliasing filter, and export it is filtered after secondary voltage to the A/D converter,
Ethernet mac, the assembling for realizing ethernet frame；
Ethernet PHY, conversion and serial/parallel conversion for realizing signal level, signal output after conversion is to described
Ethernet mac and the on-site programmable gate array FPGA；
Ethernet fiber optic receiver, for receiving combining unit to be measured with the ethernet frame of optical signal transmission, and will be with optical signal
The ethernet frame of transmission is converted into electric signal, and exports to the ethernet PHY；
Universal optical fibre receiver, for receiving external clock unit with IRIG-B yards of optical signal transmission, and will be passed with optical signal
IRIG-B yards of defeated signal is converted into electric signal, and exports to the on-site programmable gate array FPGA；The external clock list
The output end of unit is also connected with combining unit to be measured, and the combining unit to be measured receives external clock unit with optical signal transmission
IRIG-B yards, it is ensured that synchronous with the holding of universal optical fibre receiver；
Precision transformer, for receiving analog quantity voltage or current signal, the analog quantity voltage or current signal are treated with described
It is same to survey the analog quantity voltage or current signal of combining unit access, realizes primary voltage, electric current turning to secondary voltage
Change, and export secondary voltage to the low pass filter；
CPU processor, the sampled value for obtaining combining unit from the ethernet mac, obtains from the D/A converter
Sampled value, obtains the delivery time of sampling value message from effective digit pulse of the on-site programmable gate array FPGA, calculates
The phase error of combining unit, and be compared with the requirement of professional standard, realize that analog input combining unit phase is accurate
The inspection of degree；
The CPU processor, on-site programmable gate array FPGA, A/D converter, D/A converter are interconnected by local bus, institute
State CPU processor and line access is entered to the data of the FPGA, A/D converter, D/A converter by local bus, the D/A turns
Parallel operation outputs voltage signal to the constant-temperature crystal oscillator, and the constant-temperature crystal oscillator exports clock signal to the field programmable gate array
FPGA。
2. the verifying attachment of the analog input combining unit phase accuracy according to right wants 1, it is characterised in that above-mentioned
Low pass filter uses second-order low-pass filter, and the second-order low-pass filter cut-off frequency is 20kHz.
3. the verifying attachment of the analog input combining unit phase accuracy according to right wants 1, it is characterised in that described
A/D converter complete analog quantity to the sample rate that digital quantity is changed be 200kHz.
4. the verifying attachment of the analog input combining unit phase accuracy according to right wants 1, it is characterised in that above-mentioned
On-site programmable gate array FPGA accurately records the reception of SV messages by way of ethernet PHY exit hardware beats timestamp
Moment.
5. the verifying attachment of the analog input combining unit phase accuracy according to right wants 1, it is characterised in that described
The class of accuracy of precision transformer is 0.05 grade, and 2 higher than combining unit to be measured of the degree of accuracy of the precision transformer is accurate
Degree grade.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410758809.0A CN104375047B (en) | 2014-12-11 | 2014-12-11 | A kind of verifying attachment of analog input combining unit phase accuracy |
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| CN201410758809.0A CN104375047B (en) | 2014-12-11 | 2014-12-11 | A kind of verifying attachment of analog input combining unit phase accuracy |
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| CN104375047B true CN104375047B (en) | 2017-06-20 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104793077A (en) * | 2015-04-11 | 2015-07-22 | 国家电网公司 | Phase error detecting method of analog input combining unit |
| CN104931826A (en) * | 2015-06-12 | 2015-09-23 | 国家电网公司 | Phase error test device and method of analog input type merging unit |
| CN110596485B (en) * | 2019-08-22 | 2022-11-04 | 国网安徽省电力有限公司 | Digital-analog integrated tester and digital-analog synchronous output method thereof |
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| KR101363045B1 (en) * | 2007-04-20 | 2014-02-17 | 현대중공업 주식회사 | Testing device for Merging unit |
| CN103487695B (en) * | 2013-09-26 | 2016-05-25 | 国家电网公司 | Based on the checkout gear of analog input merge cells |
| CN103605023B (en) * | 2013-11-20 | 2016-09-21 | 国家电网公司 | A kind of combining unit time response measuring method and measurement apparatus |
| CN103616591B (en) * | 2013-11-27 | 2016-09-21 | 国家电网公司 | The simulator of a kind of Intelligent substation merging unit characteristic and emulation mode thereof |
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| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: JIANGSU ELECTRIC POWER COMPANY YANGZHOU POWER SUPP Free format text: FORMER OWNER: JIANGSU ELECTRIC POWER COMPANY YANGZHOU POWER SUPPLY CO., JIANGSU PROV ELECTRIC POWER CO., LTD. WUHAN KEMOV ELECTRIC CO., LTD. Effective date: 20150206 |
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Inventor after: Qin Jian Inventor after: Zhang Zhengyang Inventor after: Wang Zhan Inventor after: Shi Hui Inventor after: Ji Hui Inventor after: Chen Yan Inventor after: Lu Wei Inventor after: Zhang Peng Inventor before: Qin Jian Inventor before: Zhang Zhengyang Inventor before: Wang Zhan Inventor before: Shi Hui Inventor before: Ji Hui Inventor before: Chen Yan Inventor before: Yang Jingchao |
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Free format text: CORRECT: INVENTOR; FROM: QIN JIAN ZHANG ZHENGYANG WANG ZHAN SHI HUI JI HUI CHEN YAN YANG JINGCHAO TO: QIN JIAN ZHANG ZHENGYANG WANG ZHAN SHI HUI JI HUI CHEN YAN LU WEI ZHANG PENG |
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Effective date of registration: 20150206 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant after: State Grid Corporation of China Applicant after: Jiangsu Electric Power Company Applicant after: Yangzhou Power Supply Company of Jiangsu Electric Power Company Applicant after: Wuhan Zhongyuan Huadian Science & Technology Co., Ltd. Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant before: State Grid Corporation of China Applicant before: Jiangsu Electric Power Company Applicant before: Yangzhou Power Supply Company of Jiangsu Electric Power Company Applicant before: Wuhan Kemov Electric Co., Ltd. |
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Effective date of registration: 20170407 Address after: 225009 Weiyang Road, Jiangsu, China, No. 179, No. Applicant after: YANGZHOU POWER SUPPLY COMPANY, STATE GRID JIANGSU ELECTRIC POWER COMPANY Applicant after: STATE GRID JIANGSU ELECTRIC POWER COMPANY Applicant after: Wuhan Zhongyuan Huadian Science & Technology Co., Ltd. Applicant after: State Grid Corporation of China Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant before: State Grid Corporation of China Applicant before: Jiangsu Electric Power Company Applicant before: Yangzhou Power Supply Company of Jiangsu Electric Power Company Applicant before: Wuhan Zhongyuan Huadian Science & Technology Co., Ltd. |
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