CN104348472A - Voltage level converting circuit - Google Patents

Abstract

A voltage level conversion circuit including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor . By configuring the sixth transistor and the seventh transistor to provide equivalent high resistance, the latch-up capability of the third transistor and the fourth transistor can be weakened, so that when the input voltage difference is at a lower level, the circuit can still Smooth transition, and the fifth transistor and the eighth transistor are provided to provide a conduction path, which can shorten the rise or fall time of the output signal. Under the same transition time requirement, the voltage of the present invention is higher than that of the prior art. The level conversion circuit can reduce the layout area and reduce dynamic current consumption.

Description

Voltage level conversion circuit

technical field

The invention relates to a conversion circuit, in particular to a voltage level conversion circuit.

Background technique

A voltage level conversion circuit is a conversion circuit widely used in current electronic circuits, and is used for converting signals between different voltage levels.

Referring to FIG. 1, an existing voltage level conversion circuit (FIG. 1 uses an N-Type voltage level conversion circuit as an illustration) includes a first transistor M1, a second transistor M2, a third transistor M3, and a first transistor M1. Four transistors M4.

The first transistor M1 has a first terminal outputting an inverted output signal OUTB, a second terminal electrically connected to a low level voltage VN, and a control terminal receiving an input signal IN.

The second transistor M2 has a first terminal outputting an output signal OUT, a second terminal electrically connected to the low level voltage VN, and a control terminal receiving an inverted input signal INB.

The third transistor M3 has a first terminal outputting the inverted output signal OUTB, a second terminal electrically connected to a high level voltage VP, and a control terminal electrically connected to the first terminal of the second transistor M2.

The fourth transistor M4 has a first terminal outputting the output signal OUT, a second terminal electrically connected to the high level voltage VP, and a control terminal electrically connected to the first terminal of the first transistor M1.

In general use, the voltage level conversion circuit is used to convert the input signal IN and the inverted input signal INB into the output signal OUT and the inverted output signal OUTB, wherein the input signal IN and the inverted input signal INB is a differential signal, and its voltage level difference is lower than the voltage level difference between the output signal OUT and the inverted output signal OUTB (the voltage level difference between the high level voltage VP and the low level voltage VN).

The first transistor M1 and the second transistor M2 are input differential pairs (differential input pair), and the third transistor M3 and the fourth transistor M4 form a positive feedback (positive feedback) mechanism, like a latch circuit (latch circuit), or As a cross-coupled pair, when the circuit is operating, the first transistor M1 and the second transistor M2 must be able to provide enough dynamic current to unlock the latch circuit, so that the input signal IN, invert The input signal INB is normally converted into the output signal OUT and the inverted output signal OUTB.

However, when the voltage levels of the input signal IN and the inverted input signal INB are close to the threshold voltage (threshold voltage) of the input-stage transistors (namely, the first transistor M1 and the second transistor M2), they will encounter difficulty in transition, and easily cause circuit damage. There is a direct current (DC) current in static state, which causes leakage current in the circuit.

Generally, in order to overcome this problem, the dynamic current of the input stage transistor will be increased by increasing the width of the input stage transistor, or the channel length (channel length) of the transistor of the latch circuit (that is, the third transistor M3 and the fourth transistor M4) will be increased. ) to reduce the ability of the latch circuit, but the former not only increases the power consumption but also increases the layout area and increases the circuit cost. The latter is an N-type Metal-Oxide-Semiconductor Field transistor for the input stage transistor. -Effect Transistor, abbreviated as N-MOSFET), it will increase the rising time (risingtime) of the output signal OUT and the inverted output signal OUTB, and the input stage transistor is a P-type metal oxide half field effect transistor (P-MOSFET). As shown in FIG. 2 , the falling time (falling time) of the output signal OUT and the inverted output signal OUTB will be increased, resulting in an increase in the transition time.

Contents of the invention

The object of the present invention is to provide a voltage level conversion circuit capable of reducing circuit area, cost and power consumption.

The voltage level conversion circuit of the present invention includes: a first output terminal, a second output terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor.

The first output terminal and the second output terminal are respectively used to output a first output voltage and a second output voltage complementary to the first output voltage.

The first transistor includes a first terminal electrically connected to the second output terminal, a second terminal electrically connected to a first level voltage, and a control terminal receiving a first input voltage.

The second transistor includes a first terminal electrically connected to the first output terminal, a second terminal electrically connected to the first level voltage, and a control terminal receiving a second input voltage, wherein the second input voltage complementary to the first input voltage.

The third transistor includes a first terminal electrically connected to the first terminal of the first transistor, a second terminal, and a control terminal electrically connected to the first output terminal.

The fourth transistor includes a first terminal electrically connected to the first terminal of the second transistor, a second terminal, and a control terminal electrically connected to the second output terminal.

The voltage level conversion circuit further includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor.

The fifth transistor includes a first terminal electrically connected to the second terminal of the third transistor, a second terminal electrically connected to a second level voltage, and a control terminal electrically connected to the second output terminal.

The sixth transistor is connected in series between the second level voltage and the second output terminal for providing equivalent high resistance.

The seventh transistor is connected in series between the second level voltage and the first output terminal for providing equivalent high resistance.

The eighth transistor includes a first terminal electrically connected to the second terminal of the fourth transistor, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to the first output terminal.

In the voltage level conversion circuit of the present invention, the sixth transistor includes: a first terminal electrically connected to the second terminal of the third transistor, a second terminal electrically connected to the second level voltage, and an electrical connection A control terminal for a bias input controlled to maintain operation in the saturation region.

The seventh transistor includes: a first terminal electrically connected to the second terminal of the fourth transistor, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to the bias input terminal, controlled to Maintain operation in the saturation region.

In the voltage level conversion circuit of the present invention, the first transistor and the second transistor are N-type metal oxide semiconductor field effect transistors; the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, The seventh transistor and the eighth transistor are P-type metal oxide semiconductor field effect transistors.

In the voltage level conversion circuit of the present invention, the first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors; the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, The seventh transistor and the eighth transistor are N-type metal oxide semiconductor field effect transistors.

In the voltage level conversion circuit of the present invention, the sixth transistor includes: a first terminal electrically connected to the second output terminal, a second terminal electrically connected to the second level voltage, and a bias voltage The control terminal of the input terminal is controlled to maintain operation in the saturation region;

The seventh transistor includes: a first terminal electrically connected to the first output terminal, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to the bias input terminal, controlled to maintain operation at saturation zone.

In the voltage level conversion circuit of the present invention, the sixth transistor includes: a first terminal electrically connected to the second terminal of the third transistor, a second terminal electrically connected to the second level voltage, and an electrical connection the first output terminal and a control terminal receiving the first output voltage;

The seventh transistor includes: a first terminal electrically connected to the second terminal of the fourth transistor, a second terminal electrically connected to the second level voltage, and a second output terminal electrically connected to receive the second output Voltage control terminal.

In the voltage level conversion circuit of the present invention, the first transistor and the second transistor are N-type metal oxide semiconductor field effect transistors; the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, The seventh transistor and the eighth transistor are P-type metal oxide semiconductor field effect transistors.

In the voltage level conversion circuit of the present invention, the first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors; the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, The seventh transistor and the eighth transistor are N-type metal oxide semiconductor field effect transistors.

In the voltage level conversion circuit of the present invention, the sixth transistor includes: a first terminal electrically connected to the second output terminal, a second terminal electrically connected to the second level voltage, and a first terminal electrically connected to the first output terminal. an output terminal and a control terminal receiving the first output voltage;

The seventh transistor includes: a first terminal electrically connected to the first output terminal, a second terminal electrically connected to the second level voltage, and a control device electrically connected to the second output terminal and receiving the second output voltage end.

The beneficial effects of the present invention are: the sixth transistor and the seventh transistor provide an equivalent high resistance, and when the voltage difference between the first input voltage and the second input voltage is at a lower level, the circuit can still turn normally. state, and the arrangement of the fifth transistor and the eighth transistor can shorten the rising and falling time of the first output voltage and the second output voltage, and has the effects of reducing circuit area, saving cost and power consumption.

Description of drawings

FIG. 1 is a circuit diagram of an existing voltage level conversion circuit;

FIG. 2 is a circuit diagram of another form of the existing voltage level conversion circuit;

Fig. 3 is a circuit diagram of a first preferred embodiment of the voltage level conversion circuit of the present invention;

Fig. 4 is another form of this first preferred embodiment;

Fig. 5 is the third form of the first preferred embodiment;

6 is a circuit diagram of a second preferred embodiment of the voltage level conversion circuit of the present invention;

Fig. 7 is another form of the second preferred embodiment; and

Fig. 8 is the third form of the second preferred embodiment.

Detailed ways

Below in conjunction with accompanying drawing and embodiment the present invention is described in detail:

Referring to FIG. 3, the first preferred embodiment of the voltage level conversion circuit of the present invention includes a first output terminal OUT and a second output terminal OUTB, a first transistor M1, a second transistor M2, and a third transistor M3 , a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a bias input terminal Vbias.

The first output terminal OUT and the second output terminal OUTB are respectively used to output a first output voltage and a second output voltage complementary to the first output voltage.

The first transistor M1 includes a first terminal electrically connected to the second output terminal OUTB, a second terminal electrically connected to a first level voltage V1, and a control terminal receiving a first input voltage VIN.

The second transistor M2 includes a first terminal electrically connected to the first output terminal OUT, a second terminal electrically connected to the first level voltage V1, and a control terminal receiving a second input voltage VINB, wherein, The second input voltage VINB is complementary to the first input voltage VIN, and its voltage level difference is lower than the voltage level difference between the first output voltage and the second output voltage.

The third transistor M3 includes a first terminal electrically connected to the first terminal of the first transistor M1 and the second output terminal OUTB, a second terminal, and a control terminal electrically connected to the first output terminal OUT.

The fourth transistor M4 includes a first terminal electrically connected to the first terminal of the second transistor M2 and the first output terminal OUT, a second terminal, and a control terminal electrically connected to the second output terminal OUTB.

The fifth transistor M5 includes a first terminal electrically connected to the second terminal of the third transistor M3, a second terminal electrically connected to a second level voltage V2, and a control terminal electrically connected to the second output terminal OUTB .

The sixth transistor M6 is connected in series between the second level voltage V2 and the second output terminal OUTB to provide an equivalent high resistance. The sixth transistor M6 includes: a second transistor electrically connected to the third transistor M3 The first terminal of the terminal, a second terminal electrically connected to the second level voltage V2, and a control terminal electrically connected to a bias input terminal Vbias are controlled to maintain the operation in the saturation region (Saturation region).

The seventh transistor M7 is connected in series between the second level voltage V2 and the first output terminal OUT to provide an equivalent high resistance. The seventh transistor M7 includes: a second transistor electrically connected to the fourth transistor M4 A first end of the terminals, a second end electrically connected to the second level voltage V2, and a control end electrically connected to the bias input end Vbias are controlled to maintain operation in a saturation region.

The eighth transistor M8 includes a first terminal electrically connected to the second terminal of the fourth transistor M4, a second terminal electrically connected to the second level voltage V2, and a control terminal electrically connected to the first output terminal OUT. .

In this embodiment, the first transistor M1 and the second transistor M2 are N type Metal-Oxide-Semiconductor Field-Effect Transistor (N-type Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as N-MOSFET), and the third transistor M3 , the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are P-type metal oxide semiconductor field effect transistors (P-MOSFET), and the second quasi The bit voltage V2 is higher than the first bit voltage V1, but not limited thereto.

In general use, the control terminals of the first transistor M1 and the second transistor M2 respectively receive the first input voltage VIN and the second input voltage VINB, and then output the voltage through the first output terminal OUT and the second output terminal OUTB. The first output voltage and the second output voltage with a higher voltage level difference, since the voltage level conversion operation mode of the voltage level conversion circuit is familiar in the industry, details will not be described here.

Wherein, the first transistor M1 and the second transistor M2 are input differential pairs (differential input pair), the third transistor M3 and the fourth transistor M4 form a positive feedback mechanism, which can be regarded as a latch Lock circuit (latchcircuit), or cross-coupled pair (cross-coupled pair).

During the transition period of the circuit (that is, when the first input voltage VIN and the second input voltage VINB change from a relatively low level voltage to a high level voltage, or from a relatively high level voltage to a low level voltage), through the bias Voltage input terminal Vbias provides a bias voltage to make the sixth transistor M6 and the seventh transistor M7 operate in the saturation region. At this time, the sixth transistor M6 and the seventh transistor M7 are respectively equivalent to a transistor connected in series with the second quasi-transistor. The equivalent high resistance between the bit voltage V2 and the third transistor M3 and the fourth transistor M4 (that is, the small-signal equivalent output resistance ro), can weaken the latch-up capability of the third transistor M3 and the fourth transistor M4 in this way, The first output voltage and the second output voltage can change state more easily.

When the equivalent resistance of the sixth transistor M6 and the seventh transistor M7 is higher, the latch-up capability of the third transistor M3 and the fourth transistor M4 is weakened, so the first transistor M1 and the first transistor M1 The second transistor M2 can easily turn the first output voltage and the second output voltage without providing a large dynamic current.

However, the weaker the latch-up ability of the third transistor M3 and the fourth transistor M4 will cause the rise time (rising time) of the first output voltage and the second output voltage to increase, so the fifth transistor M5 and the fifth transistor M5 are set. The eighth transistor M8 shortens the rising time of the first output voltage and the second output voltage.

During the transition period of the circuit, when the first input voltage VIN changes from a relatively low level voltage to a high level voltage (at this time, the second input voltage VINB changes from a relatively high level voltage to a low level voltage), at the first When the transistor M1 is in the conduction state, the path through the eighth transistor M8 can accelerate the rising time of the first output voltage; when the first input voltage VIN changes from a relatively high level voltage to a low level voltage (the first The second input voltage VINB changes from a relatively low level voltage to a high level voltage), when the second transistor M2 is turned on, the path passing through the fifth transistor M5 can accelerate the rising time of the second output voltage.

Through the above description, the advantages of this embodiment can be summarized as follows:

By setting the sixth transistor M6 and the seventh transistor M7 as an equivalent high resistance connected in series between the second level voltage V2 and the third transistor M3 and the fourth transistor M4, the third transistor M3 can be weakened and the latch-up capability of the fourth transistor M4, so that the first output voltage and the second output voltage can be easily transitioned, and then the fifth transistor M5 and the eighth transistor M8 are arranged in conjunction to provide a conduction path, which can Shorten the rising time of the first output voltage and the second output voltage, so even if the voltage levels of the first input voltage VIN and the second input voltage VINB are close to the thresholds of the first transistor M1 and the second transistor M2 voltage (threshold voltage), the first output voltage and the second output voltage can still transition smoothly.

When the voltage difference (│VIN-VINB│) between the first input voltage VIN and the second input voltage VINB is at a lower level, compared with the existing voltage level conversion circuit, this embodiment performs Under the demand of the state time, the layout (layout) area can be reduced without consuming more dynamic current, so it is suitable for application in the driving circuit of the liquid crystal display (Liquid Crystal Display, abbreviated as LCD), which can greatly reduce the chip area and save the cost and power consumption.

Referring to Fig. 4, it is another form of the first preferred embodiment, the difference between this form and the first preferred embodiment is:

The first transistor M1 and the second transistor M2 are P-type metal oxide semiconductor field effect transistors, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 . The eighth transistor M8 is an N-type MOSFET, and the first level voltage V1 is higher than the second level voltage V2.

Wherein, the first transistor M1 and the second transistor M2 are an input differential pair, and the third transistor M3 and the fourth transistor M4 form a positive feedback mechanism, which can be regarded as a latch circuit.

During the circuit transition period, the bias voltage provided by the bias input terminal Vbias will make the sixth transistor M6 and the seventh transistor M7 operate in the saturation region, so as to weaken the latch of the third transistor M3 and the fourth transistor M4 lock capability, so that the first output voltage and the second output voltage can be easily transitioned, and then cooperate with the fifth transistor M5 and the eighth transistor M8 to provide a conduction path, which can shorten the first output voltage and the second The falling time of the output voltage, since the circuit principle is similar to the above, will not be repeated here.

In this way, this form can also achieve the same purpose and effect as the above-mentioned first preferred embodiment.

Referring to Fig. 5, it is the third form of the first preferred embodiment, the difference between this form and the first preferred embodiment is:

The sixth transistor M6 includes: a first terminal electrically connected to the second output terminal OUTB, a second terminal electrically connected to the second level voltage V2, and a control terminal electrically connected to a bias input terminal Vbias, Controlled to maintain operation in the saturation region.

The seventh transistor M7 includes: a first terminal electrically connected to the first output terminal OUT, a second terminal electrically connected to the second level voltage V2, and a control terminal electrically connected to the bias input terminal Vbias, Controlled to maintain operation in the saturation region.

This form can also achieve the same purpose and effect as the above-mentioned first preferred embodiment, since the circuit principle is similar to the above, so it will not be repeated here.

Referring to Fig. 6, it is a second preferred embodiment of the voltage level conversion circuit of the present invention, the second preferred embodiment is similar to the first preferred embodiment, the second preferred embodiment is the same as the first The differences of the preferred embodiment are:

The sixth transistor M6 includes: a first terminal electrically connected to the second terminal of the third transistor M3, a second terminal electrically connected to the second level voltage V2, and a first output terminal OUT electrically connected to receive The control terminal of the first output voltage.

The seventh transistor M7 includes: a first terminal electrically connected to the second terminal of the fourth transistor M4, a second terminal electrically connected to the second level voltage V2, and a second output terminal OUTB electrically connected to receive The control terminal of the second output voltage.

In this embodiment, the first transistor M1 and the second transistor M2 are N-type metal oxide semiconductor field effect transistors, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 , the seventh transistor M7 and the eighth transistor M8 are P-type MOSFETs, and the second level voltage V2 is higher than the first level voltage V1 , but not limited thereto.

The first transistor M1 and the second transistor M2 are an input differential pair, and the third transistor M3 and the fourth transistor M4 form a positive feedback mechanism, which can be regarded as a latch circuit.

During the transition period of the circuit, the first output voltage and the second output voltage will make the sixth transistor M6 and the seventh transistor M7 operate in the triode region (triode region), at this time the sixth transistor M6 and the first transistor M6 The seven transistors M7 are respectively equivalent to a linear resistor connected in series between the second level voltage V2 and the third transistor M3 and the fourth transistor M4 (that is, the linear resistor Ron between the drain terminal and the source terminal of the transistor, but three The resistance performance of the stage tube region will be slightly inferior to the resistance performance of the saturation region), so that the latch-up capability of the third transistor M3 and the fourth transistor M4 can be weakened, so that the first output voltage and the second output voltage can be easily transition, and can reduce the dynamic current required to be provided by the first transistor M1 and the second transistor M2.

The fifth transistor M5 and the eighth transistor M8 are set together to provide a conduction path, which can shorten the rise time of the first output voltage and the second output voltage. Since the circuit principle is similar to the above, so it will not be repeated here. .

In this way, the second preferred embodiment can also achieve the same purpose and effect as the above-mentioned first preferred embodiment.

Referring to Fig. 7, it is another form of the second preferred embodiment, the difference between this form and the second preferred embodiment is:

The first transistor M1 and the second transistor M2 are P-type metal oxide semiconductor field effect transistors, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 . The eighth transistor M8 is an N-type MOSFET, and the first level voltage V1 is higher than the second level voltage V2 , but not limited thereto.

Wherein, the first transistor M1 and the second transistor M2 are an input differential pair, and the third transistor M3 and the fourth transistor M4 form a positive feedback mechanism, which can be regarded as a latch circuit.

During the transition period of the circuit, the first output voltage and the second output voltage will cause the sixth transistor M6 and the seventh transistor M7 to operate in the triode region as equivalent to a voltage connected in series with the second level The linear resistance between V2 and the third transistor M3 and the fourth transistor M4 can weaken the latch-up capability of the third transistor M3 and the fourth transistor M4, so that the first output voltage and the second output voltage can be compared It is easy to turn the state, and the fifth transistor M5 and the eighth transistor M8 are combined to provide a conduction path, which can shorten the falling time of the first output voltage and the second output voltage. Since the circuit principle is similar to the above, it will not be discussed here. Say no more.

In this way, this form can also achieve the same purpose and effect as the above-mentioned first preferred embodiment.

Referring to Fig. 8, it is the third form of the second preferred embodiment, the difference between this form and the second preferred embodiment is:

The sixth transistor M6 includes: a first terminal electrically connected to the second output terminal OUTB, a second terminal electrically connected to the second level voltage V2, and a second terminal electrically connected to the first output terminal OUT and receiving the first output terminal OUT A control terminal for an output voltage.

The seventh transistor M7 includes: a first terminal electrically connected to the first output terminal OUT, a second terminal electrically connected to the second level voltage V2, and a second terminal electrically connected to the second output terminal OUTB and receiving the first Two output voltage control terminals.

This form can also achieve the same purpose and effect as the above-mentioned second preferred embodiment, since the circuit principle is similar to the above, no more details are given here.

To sum up, the present invention can reduce the circuit area, save cost and power consumption, so the purpose of the present invention can indeed be achieved.

The above is only an explanation of the specific structural embodiments of the present invention. Without violating the structure and spirit of the present invention, all those skilled in the art can still make various changes and modifications. In order to be covered in the scope of the following patent applications in this case.

Claims (9)

1. A voltage level conversion circuit, comprising: a first output terminal, a second output terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor; The first output terminal and the second output terminal are respectively used to output a first output voltage and a second output voltage complementary to the first output voltage; The first transistor includes a first terminal electrically connected to the second output terminal, a second terminal electrically connected to a first level voltage, and a control terminal receiving a first input voltage; The second transistor includes a first terminal electrically connected to the first output terminal, a second terminal electrically connected to the first level voltage, and a control terminal receiving a second input voltage, wherein the second input voltage complementary to the first input voltage; The third transistor includes a first terminal electrically connected to the first terminal of the first transistor, a second terminal, and a control terminal electrically connected to the first output terminal; The fourth transistor includes a first terminal electrically connected to the first terminal of the second transistor, a second terminal, and a control terminal electrically connected to the second output terminal; It is characterized by: The voltage level conversion circuit also includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The fifth transistor includes a first terminal electrically connected to the second terminal of the third transistor, a second terminal electrically connected to a second level voltage, and a control terminal electrically connected to the second output terminal; The sixth transistor is connected in series between the second level voltage and the second output terminal for providing equivalent high resistance; The seventh transistor is connected in series between the second level voltage and the first output terminal for providing equivalent high resistance; The eighth transistor includes a first terminal electrically connected to the second terminal of the fourth transistor, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to the first output terminal. 2. The voltage level conversion circuit as claimed in claim 1, characterized in that: The sixth transistor includes: a first terminal electrically connected to the second terminal of the third transistor, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to a bias input terminal, controlled to maintain operation in the saturation zone; The seventh transistor includes: a first terminal electrically connected to the second terminal of the fourth transistor, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to the bias input terminal, controlled to Maintain operation in the saturation region. 3. The voltage level conversion circuit as claimed in claim 2, characterized in that: The first transistor and the second transistor are N-type metal-oxide-semiconductor field-effect transistors; The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type metal oxide semiconductor field effect transistors. 4. The voltage level conversion circuit as claimed in claim 2, characterized in that: The first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors; The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are N-type metal oxide semiconductor field effect transistors. 5. The voltage level conversion circuit as claimed in claim 1, characterized in that: The sixth transistor includes: a first terminal electrically connected to the second output terminal, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to a bias input terminal, controlled to maintain operation at saturation zone; The seventh transistor includes: a first terminal electrically connected to the first output terminal, a second terminal electrically connected to the second level voltage, and a control terminal electrically connected to the bias input terminal, controlled to maintain operation at saturation zone. 6. The voltage level conversion circuit as claimed in claim 1, characterized in that: The sixth transistor includes: a first terminal electrically connected to the second terminal of the third transistor, a second terminal electrically connected to the second level voltage, and a first output terminal electrically connected to receive the first output Voltage control terminal; The seventh transistor includes: a first terminal electrically connected to the second terminal of the fourth transistor, a second terminal electrically connected to the second level voltage, and a second output terminal electrically connected to receive the second output Voltage control terminal. 7. The voltage level conversion circuit as claimed in claim 6, characterized in that: The first transistor and the second transistor are N-type metal-oxide-semiconductor field-effect transistors; The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type metal oxide semiconductor field effect transistors. 8. The voltage level conversion circuit as claimed in claim 6, characterized in that: The first transistor and the second transistor are P-type metal oxide semiconductor field effect transistors; The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are N-type metal oxide semiconductor field effect transistors. 9. The voltage level conversion circuit as claimed in claim 1, characterized in that: The sixth transistor includes: a first terminal electrically connected to the second output terminal, a second terminal electrically connected to the second level voltage, and a control device electrically connected to the first output terminal and receiving the first output voltage end; The seventh transistor includes: a first terminal electrically connected to the first output terminal, a second terminal electrically connected to the second level voltage, and a control device electrically connected to the second output terminal and receiving the second output voltage end.