CN104347596A - Sealing ring structure of chip - Google Patents
Sealing ring structure of chip Download PDFInfo
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- CN104347596A CN104347596A CN201310345408.8A CN201310345408A CN104347596A CN 104347596 A CN104347596 A CN 104347596A CN 201310345408 A CN201310345408 A CN 201310345408A CN 104347596 A CN104347596 A CN 104347596A
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Abstract
The invention provides a sealing ring structure of a chip. The sealing ring structure comprises an inner sealing ring and an outer sealing ring, wherein the inner sealing ring is arranged surrounding an integrated circuit area and is provided with an aluminum weld pad; the outer sealing ring is arranged surrounding the inner sealing ring; the inner sealing ring comprises one or more first sub sealing rings, one or more second sub sealing rings and first dielectric isolation rings, wherein the one or more first sub sealing rings are coupled to the aluminum weld pad and are arranged close to the outer sealing ring, and each first sub sealing ring comprises a group of sealing strips, which are arranged along the circumferential direction and are independent of one another, and dielectric isolation strips which are used for isolating adjacent sealing strips; the one or more second sub sealing rings are arranged close to the integrated circuit area; the first dielectric isolation rings are arranged between the first sub sealing rings and the second sub sealing rings, so as to isolate the second sub sealing rings from the aluminum weld pad and the first sub sealing rings. According to the sealing ring structure of the chip, the second sub sealing rings are isolated from the aluminum weld pad and the first sub sealing rings by using the first dielectric isolation rings, and the first sub sealing rings are isolated into the mutually-independent sealing strips by using the dielectric isolation strips, so that the defect that the integrated circuit area is failed due to short circuit is avoided.
Description
Technical field
The application relates to field of semiconductor manufacture, in particular to a kind of seal ring structure of chip.
Background technology
In semiconductor fabrication process, can be formed on a semiconductor substrate by techniques such as photoetching, etching and depositions and comprise semiconductor active device and be arranged on the semiconductor chip of the interconnection structure on device.Usually, multiple chip can be formed on a wafer, finally again these chips be cut down from wafer, carry out packaging technology, form integrated circuit district.In the process of diced chip, the stress that cutter produce can cause damage to the edge of chip, even can cause chip generation avalanche.Existing in order to prevent chip from sustaining damage when cutting, in the active device area periphery of chip, sealing ring is set, sealing ring can stop that the stress that cutter produce causes the undesired stress fracture of active device area, and chip sealing ring can stop water vapor permeable such as containing acid substance, the chemical damage that causes containing the diffusion of alkaloid substance or pollutant sources.
In semiconductor technology now, increasing dual chip sealing ring solves more serious splintering problem, has the semiconductor chip structure schematic diagram of sealing ring in prior art as shown in Figure 1 to Figure 3.Sealing ring comprises inner seal ring 21 ' (edge seal district) and outer seal ring 22 ' (crack stop district), inner seal ring 21 ' and outer seal ring 22 ' include the stepped construction of more metal layers, wherein, every one deck of stepped construction as shown in Figure 2 comprises interlayer dielectric layer 4 ' and is positioned at interlayer dielectric layer 4 ' and the discrete metal wiring layer 211 ' flushed with interlayer dielectric layer 4 ' surface, be connected by conductive plunger 5 ' between neighbouring metal wiring layer 211 ', the stepped construction of inner seal ring 21 ' is formed with protective layer 23 ', there is in protective layer 23 ' opening exposing metal wiring layer 211 ', at protective layer 23 ' upper formation aluminum pad 206 ', and aluminum pad 206 ' fills above-mentioned opening, aluminum pad 206 ' and protective layer 23 ' are formed with sealant 24 '.In addition, application number to be Chinese patent application, the application number of 2004800215224 be 2021100495316 Chinese patent application, application number be 202210262670 Chinese patent application all disclose concrete seal ring structure.
Above-mentioned seal ring structure all can protect active device area from the cutting damage of stress and the pollution of pollutant well, but, encapsulate and metal aluminum steel used easy connection with the aluminum pad of inner seal ring cause the short circuit of integrated circuit district, lost efficacy in integrated circuit district.
Summary of the invention
Easily being connected with the aluminum pad of inner seal ring the problem causing the short circuit of integrated circuit district to solve metal aluminum steel, this application provides a kind of seal ring structure of chip.
Above-mentioned seal ring structure comprises: inner seal ring, arranges, have aluminum pad around integrated circuit district; And outer seal ring, arrange around inner seal ring; Above-mentioned inner seal ring comprises: one or more first sub-sealing ring, coupling with aluminum pad, arranges near outer seal ring, and each first sub-sealing ring comprises the dielectric isolation bar of the separate sealing strip of a group of circumferentially the arranging sealing strip adjacent with isolation; One or more second sub-sealing ring, is arranged near integrated circuit district; First dielectric isolation ring, is arranged between the first sub-sealing ring and the second sub-sealing ring, the second sub-sealing ring and aluminum pad and the first sub-sealing ring is kept apart.
Further, above-mentioned first sub-sealing ring is multiple, and inner seal ring also comprises the second dielectric isolation ring, and the second dielectric isolation ring is arranged between the first adjacent sub-sealing ring.
Further, above-mentioned second sub-sealing ring is multiple, and inner seal ring also comprises the 3rd dielectric isolation ring, and the 3rd dielectric isolation ring is arranged between the second adjacent sub-sealing ring.
Further, above-mentioned inner seal ring also comprises the first floating boom, and the first floating boom is arranged between the first sub-sealing ring and the substrate of chip.
Further, the sealing strip of above-mentioned outer seal ring, the first sub-sealing ring and the second sub-sealing ring comprises respectively: n layer intermetallic dielectric layer, and stacked along the direction perpendicular to substrate, n is positive integer; N+1 layer metal wiring layer, is crisscross arranged with intermetallic dielectric layer; N via hole, runs through each intermetallic dielectric layer and arranges.
Further, each above-mentioned via hole along the direction perpendicular to substrate just to setting.
Further, above-mentioned first floating boom comprises: multiple first sub-floating boom, arranges accordingly with the via hole being positioned at the first sub-sealing ring bottom; Media protection portion, is arranged between multiple first sub-floating boom.
Further, said chip also comprises: interlayer dielectric layer, is arranged between substrate and seal ring structure; Connector, runs through interlayer dielectric layer and arranges, and corresponding with the via hole being positioned at seal ring structure bottom.
Further, above-mentioned inner seal ring also comprises the second floating boom, and the second floating boom is arranged between the second sub-sealing ring and substrate.
Further, above-mentioned inner seal ring also comprises the first shallow trench isolation part, is arranged on the substrate corresponding with inner seal ring, and the first floating boom and the second floating boom are arranged on the first shallow trench isolation part.
Further, above-mentioned outer seal ring also comprises the 3rd floating boom, and the 3rd floating boom is arranged on the substrate corresponding with outer seal ring.
Further, above-mentioned outer seal ring also comprises logic circuit area, and logic circuit area is arranged on substrate, and the 3rd floating boom is arranged in logic circuit area.
Further, above-mentioned outer seal ring also comprises the second shallow trench isolation part, and the second shallow trench isolation part is arranged on the substrate corresponding with outer seal ring, and the 3rd floating boom is arranged on the second shallow trench isolation part.
Further, above-mentioned seal ring structure also comprises: protective layer, be arranged on being positioned on the metal wiring layer of top layer in n+1 layer metal wiring layer, and have opening in the region of inner seal ring, aluminum pad to be arranged on the protective layer in inner seal ring region and to fill opening; Sealant, is arranged on aluminum pad.
Further, the material of above-mentioned protective layer is silicon nitride or silica.
Further, the material of above-mentioned sealant is silica or silicon nitride.
Further, the material of above-mentioned metal wiring layer is copper or aluminium.
Further, the number of plies of above-mentioned metal wiring layer is 6 ~ 8 layers.
Further, the material in above-mentioned first dielectric isolation ring, the second dielectric isolation ring, the 3rd dielectric isolation ring, dielectric isolation article and media protection portion is the silica of SiOCH, silica, silicon nitride, fluorine silex glass or doping carbon.
Inner seal ring is set to the first separate sub-sealing ring and the second sub-sealing ring by the application, and utilize circumferentially around and extended along the vertical direction the first dielectric isolation ring by the second sub-sealing ring and aluminum pad, first sub-sealing ring and the second sub-sealing ring are kept apart, what make can be electrically connected with aluminum pad only has the first sealing ring, then circumferentially spread configuration and the first sub-sealing ring is isolated into separate sealing strip by the dielectric isolation bar extended along the vertical direction is utilized further, thus interrupted the loop that in prior art, aluminum pad and sealing ring are formed, avoid the defect lost efficacy because of short circuit in integrated circuit district, sealing strip, the second sub-sealing ring and outer seal ring still keep good sealing property simultaneously, and therefore, the seal ring structure of the application can meet the seal protection effect to integrated circuit district, and integrated circuit district can not be caused again to lose efficacy because of short circuit.And, the manufacturing process in the manufacturing process with the seal ring structure of said structure and integrated circuit district is synchronously carried out, particular location according to sealing strip, dielectric isolation bar and dielectric isolation ring designs corresponding mask plate, then adopt the method such as etching, deposition of this area routine to make each several part of sealing ring, manufacture method is simple.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the exemplary embodiment of the application and explanation thereof, for explaining the application, do not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the cross-sectional view being parallel to substrate direction of a kind of seal ring structure in prior art;
The part A that Fig. 2 shows the seal ring structure shown in Fig. 1 is radially and perpendicular to the cross-sectional view of substrate;
Fig. 3 shows along B-B face in Fig. 2 and perpendicular to the cross-sectional view of substrate;
Fig. 4 shows the cross-sectional view being parallel to substrate direction of a kind of preferred embodiment middle seal ring structure of the application;
The part A that Fig. 5 shows the seal ring structure shown in Fig. 4 is radially and perpendicular to the cross-sectional view of substrate;
Fig. 6 shows along B-B face in Fig. 5 and perpendicular to the cross-sectional view of substrate;
Fig. 7 shows the cross-sectional view being parallel to substrate direction of seal ring structure in another preferred embodiment of the application;
The part A that Fig. 8 shows the seal ring structure shown in a kind of preferred Fig. 7 is radially and perpendicular to the cross-sectional view of substrate;
The part A that Fig. 9 shows another kind of preferred seal ring structure shown in Fig. 7 is radially and perpendicular to the cross-sectional view of substrate; And
The part A that Figure 10 shows another seal ring structure shown in preferred Fig. 7 is radially and perpendicular to the cross-sectional view of substrate.
Embodiment
It is noted that following detailed description is all exemplary, be intended to provide further instruction to the application.Unless otherwise, all technology used herein and scientific terminology have the identical meanings usually understood with the application person of an ordinary skill in the technical field.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and make respective explanations to used space relative descriptors here.
Now, the illustrative embodiments according to the application is described with reference to the accompanying drawings in more detail.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
The metal aluminum steel that in prior art, the encapsulation of existence pointed by background technology part is used easy connection with the aluminum pad 206 of inner seal ring 21 causes integrated circuit district 3 short circuit, make the problem lost efficacy in integrated circuit district 3, the application, in order to solve the problem, proposes a kind of seal ring structure of chip.
Fig. 4 to 10 shows the seal ring structure of preferred embodiment the provided a kind of chip of the application.Sealing ring structure comprises inner seal ring 21 and outer seal ring 22, and inner seal ring 21 is arranged around integrated circuit district 3, has aluminum pad 206; Outer seal ring 22 is arranged around inner seal ring 21; Inner seal ring 21 comprises one or more first sub-sealing ring 201, one or more second sub-sealing ring 202 and the first dielectric isolation ring 203, first sub-sealing ring 201 is coupling with aluminum pad 206, arrange near outer seal ring 22, and each first sub-sealing ring 201 comprises the dielectric isolation bar 12 of the separate sealing strip 11 of a group of circumferentially the arranging sealing strip 11 adjacent with isolation; Second sub-sealing ring 202 is arranged near integrated circuit district 3; First dielectric isolation ring 203 is arranged between the first sub-sealing ring 201 and the second sub-sealing ring 202, the first sub-sealing ring 201 and aluminum pad 206 and the second sub-sealing ring 202 is kept apart.
Inner seal ring 21 is set to the first separate sub-sealing ring 201 and the second sub-sealing ring 202 by the application, and utilize circumferentially around and extended along the vertical direction the first dielectric isolation ring 203 by the second sub-sealing ring 202 and aluminum pad 206, first sub-sealing ring 201 and the second sub-sealing ring 202 are kept apart (as Fig. 4, shown in Fig. 5 and Fig. 8 to Figure 10), what make can be electrically connected with aluminum pad 206 only has the first sub-sealing ring 201, then circumferentially spread configuration and the first sub-sealing ring 201 is isolated into separate sealing strip 11(as Fig. 4 by the dielectric isolation bar 12 extended along the vertical direction is utilized further, shown in Fig. 6 and Fig. 7), thus interrupted the loop that in prior art, aluminum pad 206 and sealing ring are formed, avoid the defect lost efficacy because of short circuit in integrated circuit district 3, the sub-sealing ring 202 of sealing strip 11, second and outer seal ring 22 still keep good sealing property simultaneously, and therefore, the seal ring structure of the application can meet the seal protection effect to integrated circuit district 3, and integrated circuit district 3 can not be caused again to lose efficacy because of short circuit.And, the manufacturing process in the manufacturing process with the seal ring structure of said structure and integrated circuit district 3 is synchronously carried out, particular location according to sealing strip 11, dielectric isolation bar 12 and the first dielectric isolation ring 203 designs corresponding mask plate, then adopt the method such as etching, deposition of this area routine to make each several part of sealing ring, manufacture method is simple.
The first sub-sealing ring 201 of the application can be one also can be multiple, and the first sub-sealing ring 201 that in seal ring structure as shown in Figure 4, circumference is arranged is one, in seal ring structure as shown in Figure 7, the structure of the first sub-sealing ring 201 that circumference is arranged is two, each first sub-sealing ring 201 all has sealing strip 11 and isolating bar 12, and the second dielectric isolation ring 204 can be adopted to isolate between the adjacent first sub-sealing ring 201, Fig. 4 and Fig. 7 is only the seal ring structure that the application is schematically described, first sub-sealing ring 201 can be one or more just as previously mentioned, be not limited to two in Fig. 4 and Fig. 7, first sub-sealing ring 201 can be set to three according to the seal ring structure feature of reality by those skilled in the art, four even more.In first sub-sealing ring 201, circumferentially the quantity of the sealing strip 11 of spread configuration is also not limited to the quantity shown in Fig. 4 and Fig. 7, and those skilled in the art rationally can arrange the quantity of sealing strip 11 equally according to the complex structure degree of set chip.
Equally, the second sub-sealing ring 202 of the application can be one also can be multiple, seal ring structure shown in Fig. 4 and Fig. 7 all has a second sub-sealing ring 202, when the second sub-sealing ring 202 is multiple, 3rd dielectric isolation ring (attached not shown) is set between the adjacent second sub-sealing ring 202, those skilled in the art can according to the seal ring structure feature of reality the second sub-sealing ring 202 is set to two, three, four even more.
The material that can be used for making first dielectric isolation ring 203, the second dielectric isolation ring 204 of the application, the 3rd dielectric isolation ring and dielectric isolation articles 12 is the material that dielectric constant is greater than 3.6, preferred dielectric constant 3.6 ~ 7.0 material, the further preferably silica of SiOCH, silica, silicon nitride, fluorine silex glass or doping carbon.
In the application's another preferred embodiment, as shown in Fig. 5, Fig. 8, Fig. 9 or Figure 10, the sealing strip 11 of the sub-sealing ring 201 of above-mentioned outer seal ring 22, first and the second sub-sealing ring 202 comprises respectively: n layer intermetallic dielectric layer 212, n+1 layer metal wiring layer 211 and n via hole 213, n is positive integer, and intermetallic dielectric layer 212 is stacked along the direction perpendicular to substrate 1; Metal wiring layer 211 and intermetallic dielectric layer 212 are crisscross arranged; Via hole 213 runs through each intermetallic dielectric layer 212 and arranges.Metal wiring layer 211 and the mutual overlapping setting of intermetallic dielectric layer 212; and it is metal laminated to adopt via hole 213 that metal wiring layer 211 is carried out interconnected formation, this metal laminated can Protective IC district 3 avoids being subject to stress damage in cutting process, block contaminant pollutes integrated circuit district 3.
When above-mentioned intermetallic dielectric layer 212 and metal wiring layer 211 are multilayer, be preferably 6 ~ 8 layers.The material forming above-mentioned metal wiring layer 211 is copper or aluminium, and the material forming above-mentioned via hole 213 is copper or aluminium; The material of intermetallic dielectric layer 212 is the material that dielectric constant is greater than 3.6, preferred dielectric constant 3.6 ~ 7.0 material, the further preferably silica of SiOCH, silica, silicon nitride, fluorine silex glass or doping carbon.
Wherein the manufacture method of intermetallic dielectric layer 212 and metal wiring layer 211 and via hole 213 adopts the conventional method of this area to make, below to make dielectric layer 212 and layer of metal wiring layer 211 between layer of metal to make the seal ring structure of the application manufacture method for illustrative.Utilize the method such as chemical vapour deposition (CVD), plasma reinforced chemical vapour deposition to form metal level, the preferred aluminium lamination of this metal level or layers of copper, be then coated with photoresist on the metal layer, and utilize the photoetching processes such as exposure, development to carry out graphical treatment to photoresist; With patterned photoresist for mask, using plasma etching technics or reactive ion etching process etching sheet metal form metal wiring layer 211, etching gas adopts chloride, bromine, helium mist, the flow of etching gas is 50 ~ 150sccm, preferably 80 ~ 100sccm, 100 ~ 120sccm, the power output of plasma source is 2000 ~ 5000W, preferably 3000 ~ 4000W; Cineration technics or wet clean process is adopted to remove photoresist, metal wiring layer 211 adopts chemical vapour deposition technique, Low Pressure Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method or physical vaporous deposition deposit and form intermetallic dielectric layer 212, the material preferred nitrogen SiClx of intermetallic dielectric layer 212, silicon oxide carbide, silicon dioxide or silicon oxynitride; Then on this intermetallic dielectric layer 212, be coated with photoresist, and utilize the photoetching processes such as exposure, development to carry out graphical treatment formation opening figure to photoresist; With patterned photoresist for mask, using plasma etching technics or reactive ion etching process etching intermetallic dielectric layer 212 form through hole; Remove photoresist, in through hole, fill metal form via hole 213.In order to simplify the manufacture craft of the mask plate used in manufacturing process and ensure the sealing of seal ring structure, preferred each via hole 213 along the direction perpendicular to substrate 1 just to setting.
In metal wiring layer 211, metal spreads to intermetallic dielectric layer 212, preferably at employing physical vapour deposition (PVD) or sputtering technology, diffusion impervious layer is set on metal wiring layer 211, forms the preferred tantalum of material of diffusion impervious layer or tantalum nitride or both compounds.
In addition; similar to the common process of this area; need to arrange one or more layers interlayer dielectric layer 4 on semiconductor substrate 1 in the semiconductor device process making integrated circuit district 3; so the application preferably arranges one or more layers interlayer dielectric layer 4 in seal ring structure, and arrange in interlayer dielectric layer 4 with via hole 213 one to one connector 5 and the via hole 213 in intermetallic dielectric layer 212 together as metal laminated a part of Protective IC district 3.
Cause in order to avoid in use voltage is excessive sealing strip 11 in first sub-sealing ring 201 by substrate 1 mutual conduction or with integrated circuit district 3 conducting, preferably the first floating boom 214 is set between the first sub-sealing ring 201 and the substrate 1 of chip, and the first sub-floating boom 41 of the first floating boom 214 is preferably set in the position corresponding with via hole 213, and utilize media protection portion 42 to be isolated by first sub-floating boom 41, as shown in Figure 8, utilize the dielectric property of the first floating boom 214 shown in Fig. 8 that the first sub-sealing ring 201 is insulated with substrate 1, avoid producing above-mentioned conducting, and then ensure that the sensitivity of chip operation.
Equally, in order to avoid substrate 1 and the second sub-sealing ring 202 produce beyond thought adverse effect with the conducting of substrate 1 and the work of conducting to chip of outer seal ring 22 pairs of substrates 1, preferably the second floating boom 215 is set between the second sub-sealing ring and substrate 1, 3rd floating boom 216 is set between outer seal ring 22 and substrate 1, second floating boom 215 can be arranged to the structure identical with the first floating boom 214 with the 3rd floating boom 216, namely then arrange sub-floating boom in the position corresponding with via hole 213 utilize media protection portion to be kept apart by sub-floating boom, thus saved the cost of manufacture of floating boom.
The material of above-mentioned first floating boom 214, second floating boom 215 and the 3rd floating boom 216 neutron floating boom is can be metal, metal alloy, metal nitride or metal silicide; polysilicon; and other materials be applicable to, the dielectric material in media protection portion is selected from the silica of SiOCH, silica, silicon nitride, fluorine silex glass or doping carbon.The method forming above-mentioned floating boom comprises ald, chemical vapour deposition (CVD); the conventional methods such as the combination of physical vapour deposition (PVD) or said method; said method is conventionally known to one of skill in the art, and it is conventional or be out of shape all in the scope of the application's protection, does not repeat them here.
Fig. 9 shows the cross-sectional view of another preferred embodiment provided seal ring structure of the application.Inner seal ring 21 in Fig. 9 has the first shallow trench isolation part 217 arranged in semiconductor substrate 1, and the metal laminated and Semiconductor substrate 1 be located thereon is insulated.First shallow trench isolation part 217 and the first floating boom 214 arrange to avoid simultaneously and form metal-oxide-semiconductor on the substrates 1 of chip, simultaneously can bear larger operating voltage, ensure that the fail safe of chip operation and extend useful life of chip.
Fig. 9 also show and arrange logic circuit area 219 in the Semiconductor substrate 1 of outer seal ring 22 correspondence of seal ring structure, this logic circuit area 219 is connected with bottom metal wire layer 211 by connector 5, the metal laminated hermetically-sealed construction of the outer seal ring 22 also formed; Sealing ring structure is playing on the basis to the device available protecting in integrated circuit district 3, avoid better due to when aluminum pad 206 is connected with wire to the adverse effect that the device in integrated circuit district 3 causes.
Figure 10 shows the cross-sectional view of another preferred embodiment provided seal ring structure of the application.Inner seal ring 21 in Figure 10 has the first shallow trench isolation part 217 arranged in semiconductor substrate 1, and outer seal ring 22 has the second shallow trench isolation part 218 arranged in semiconductor substrate 1, and the metal laminated of top is thoroughly insulated with Semiconductor substrate 1.
Above-mentioned first shallow trench isolation part 217 and the second shallow trench isolation part 218 adopt the conventional manufacture method of this area to make: etching forms shallow trench, then fill in shallow trench megohmite insulant formed shallow trench isolation part, and use chemico-mechanical polishing CMP by semiconductor device surface planarization and high annealing firm; The megohmite insulant preferential oxidation silicon of filling in shallow trench, in order to improve the tack between Semiconductor substrate 1 and silica when filling, can also chemical vapor deposition be adopted at the inner surface of shallow trench or adopt high-temperature thermal oxidation method to form silicon oxide liner bed course at the inner surface of groove.Said method is conventionally known to one of skill in the art, and it is conventional or be out of shape all in the scope of the application's protection, does not repeat them here.
The inner seal ring 21 of the seal ring structure of the application is while adopting the structure shown in Fig. 4 to Figure 10; outer seal ring 22 can adopt the structure being similar to the first sub-sealing ring 201; as long as the metallic member of inner seal ring 21 and outer seal ring 22 is combined to form hermetically-sealed construction; ensure that the due seal protection effect of seal ring structure, also serve and avoid metal wiring layer 211, via hole 213, aluminum pad 206 aluminum conductor used with encapsulation and form the defect that loop causes integrated circuit district 3 short circuit.
The seal ring structure with said structure also comprises protective layer 23 and sealant 24, protective layer 23 is arranged on top-level metallic wiring layer 211, and in the region of inner seal ring 21, there is opening, aluminum pad 206 to be arranged on the protective layer 23 in inner seal ring 21 region and to fill opening; Sealant 24 is arranged on aluminum pad 206.Wherein top-level metallic wiring layer 211 protected by protective layer 23, avoids it in later stage encapsulation process or use procedure, be subject to the destruction of external environment condition; The protective layer 23 of aluminum pad 206 and outer seal ring 22 is carried out sealing and plays further protective effect by sealant 24.Can be used for material preferred nitrogen SiClx or the silica of the protective layer 23 of the application, the material preferential oxidation silicon of sealant 24 or silicon nitride.
The method forming above-mentioned protective layer 23 can make chemical vapour deposition technique, Low Pressure Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method or physical vaporous deposition; Further, opening is formed in protective layer 23 in inner seal ring 21, and then expose Portions of top layer metal wiring layer 211, concrete forming process is as follows: on protective layer 23, cover photoresist layer, defining opening figure through exposure imaging process, is then mask with photoresist layer, carries out etching form opening along opening figure to protective layer 23, expose top-level metallic wiring layer 211, remove photoresist layer; Follow-up employing chemical vapour deposition technique, Low Pressure Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method or physical vaporous deposition form aluminum pad 206.
As can be seen from foregoing description, the seal ring structure of the application has following advantage:
1) utilize circumferentially around and the first extended along the vertical direction dielectric isolation ring the second sub-sealing ring and aluminum pad, the first sub-sealing ring and the second sub-sealing ring are kept apart, what make can be electrically connected with aluminum pad only has the first sealing ring, then circumferentially spread configuration and the first sub-sealing ring is isolated into separate sealing strip by the dielectric isolation bar extended along the vertical direction is utilized further, thus interrupted the loop that in prior art, aluminum pad and sealing ring are formed, avoid the defect lost efficacy because of short circuit in integrated circuit district;
2) sealing strip, the second sub-sealing ring and outer seal ring still keep good sealing property, and therefore, the seal ring structure of the application can meet the seal protection effect to integrated circuit district, and integrated circuit district can not be caused again to lose efficacy because of short circuit;
3) manufacturing process in the manufacturing process with the seal ring structure of said structure and integrated circuit district is synchronously carried out, particular location according to sealing strip, dielectric isolation bar and dielectric isolation ring designs corresponding mask plate, then adopt the method such as etching, deposition of this area routine to make intermetallic dielectric layer and metal wiring layer, manufacture method is simple.
These are only the preferred implementation of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (20)
1. a seal ring structure for chip, comprising:
Inner seal ring, arranges around integrated circuit district, has aluminum pad; And
Outer seal ring, is arranged around described inner seal ring;
It is characterized in that, described inner seal ring comprises:
One or more first sub-sealing ring, coupling with described aluminum pad, arrange near described outer seal ring, and each described first sub-sealing ring comprises the dielectric isolation bar of the separate sealing strip of a group of circumferentially the arranging described sealing strip adjacent with isolation;
One or more second sub-sealing ring, is arranged near described integrated circuit district;
First dielectric isolation ring, is arranged between described first sub-sealing ring and the second sub-sealing ring, described second sub-sealing ring and described aluminum pad and described first sub-sealing ring is kept apart.
2. seal ring structure according to claim 1, is characterized in that, described first sub-sealing ring is multiple, and described inner seal ring also comprises the second dielectric isolation ring, and described second dielectric isolation ring is arranged between adjacent described first sub-sealing ring.
3. seal ring structure according to claim 2, is characterized in that, described second sub-sealing ring is multiple, and described inner seal ring also comprises the 3rd dielectric isolation ring, and described 3rd dielectric isolation ring is arranged between adjacent described second sub-sealing ring.
4. seal ring structure according to any one of claim 1 to 3, is characterized in that, described inner seal ring also comprises the first floating boom, and described first floating boom is arranged between described first sub-sealing ring and the substrate of described chip.
5. seal ring structure according to claim 4, is characterized in that, the sealing strip of described outer seal ring, described first sub-sealing ring and described second sub-sealing ring comprises respectively:
N layer intermetallic dielectric layer, stacked along the direction perpendicular to described substrate, n is positive integer;
N+1 layer metal wiring layer, is crisscross arranged with described intermetallic dielectric layer;
N via hole, runs through each described intermetallic dielectric layer and arranges.
6. seal ring structure according to claim 5, is characterized in that, each described via hole along the direction perpendicular to described substrate just to setting.
7. seal ring structure according to claim 6, is characterized in that, described first floating boom comprises:
Multiple first sub-floating boom, is arranged accordingly with the described via hole being positioned at described first sub-sealing ring bottom;
Media protection portion, is arranged between described multiple first sub-floating boom.
8. seal ring structure according to claim 5, is characterized in that, described chip also comprises:
Interlayer dielectric layer, is arranged between described substrate and described seal ring structure;
Connector, runs through described interlayer dielectric layer and arranges, and corresponding with the described via hole being positioned at described seal ring structure bottom.
9. seal ring structure according to claim 5, is characterized in that, described inner seal ring also comprises the second floating boom, and described second floating boom is arranged between described second sub-sealing ring and described substrate.
10. seal ring structure according to claim 9, it is characterized in that, described inner seal ring also comprises the first shallow trench isolation part, is arranged on the described substrate corresponding with described inner seal ring, and described first floating boom and described second floating boom are arranged on described first shallow trench isolation part.
11. seal ring structures according to claim 5, is characterized in that, described outer seal ring also comprises the 3rd floating boom, and described 3rd floating boom is arranged on the described substrate corresponding with described outer seal ring.
12. seal ring structures according to claim 11, is characterized in that, described outer seal ring also comprises logic circuit area, and described logic circuit area is arranged over the substrate, and described 3rd floating boom is arranged in described logic circuit area.
13. seal ring structures according to claim 11, it is characterized in that, described outer seal ring also comprises the second shallow trench isolation part, and described second shallow trench isolation part is arranged on the described substrate corresponding with described outer seal ring, and described 3rd floating boom is arranged on described second shallow trench isolation part.
14. seal ring structures according to claim 5, is characterized in that, described seal ring structure also comprises:
Protective layer, be arranged on and be positioned on the described metal wiring layer of top layer in described n+1 layer metal wiring layer, and in the region of described inner seal ring, there is opening, described aluminum pad to be arranged on the described protective layer in described inner seal ring region and to fill described opening;
Sealant, is arranged on described aluminum pad.
15. seal ring structures according to claim 14, is characterized in that, the material of described protective layer is silicon nitride or silica.
16. seal ring structures according to claim 14, is characterized in that, the material of described sealant is silica or silicon nitride.
17. seal ring structures according to claim 5, is characterized in that, the material of described metal wiring layer is copper or aluminium.
18. seal ring structures according to claim 5, is characterized in that, the number of plies of described metal wiring layer is 6 ~ 8 layers.
19. seal ring structures according to claim 3, it is characterized in that, the material of described first dielectric isolation ring, described second dielectric isolation ring, described 3rd dielectric isolation ring and described dielectric isolation article is the silica of SiOCH, silica, silicon nitride, fluorine silex glass or doping carbon.
20. seal ring structures according to claim 7, is characterized in that, the material in described media protection portion is the silica of SiOCH, silica, silicon nitride, fluorine silex glass or doping carbon.
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