CN104347575B - Semiconductor package assembly and a manufacturing method thereof - Google Patents
Semiconductor package assembly and a manufacturing method thereof Download PDFInfo
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- CN104347575B CN104347575B CN201310342762.5A CN201310342762A CN104347575B CN 104347575 B CN104347575 B CN 104347575B CN 201310342762 A CN201310342762 A CN 201310342762A CN 104347575 B CN104347575 B CN 104347575B
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- China
- Prior art keywords
- lateral surface
- packaging body
- infrabasal plate
- cabling
- electrical components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
A kind of semiconductor package assembly and a manufacturing method thereof.Semiconductor package part includes upper substrate, infrabasal plate, packaging body, cabling and protective layer.Upper substrate has lateral surface.Infrabasal plate has upper surface and lateral surface, and the upper surface of infrabasal plate is relative with upper substrate and lateral surface of infrabasal plate protrudes past the lateral surface of upper substrate.Packaging body is formed between upper substrate and infrabasal plate, and has lateral surface, and the lateral surface of packaging body is to tilt with extending out from upper substrate toward the direction of infrabasal plate.Cabling is formed at the lateral surface of packaging body and is electrically connected with upper substrate and infrabasal plate.Protective layer covers lateral surface and the cabling of packaging body.
Description
Technical field
The invention relates to a kind of semiconductor package assembly and a manufacturing method thereof, and in particular to one kind, there is side
The semiconductor package assembly and a manufacturing method thereof of cabling.
Background technology
Traditional stacking type semiconductor structure is generally using soldered ball as the electrical connection element being directly connected to upper and lower substrate.So
And, the size of soldered ball is generally larger, when the spacing of adjacent two soldered balls reduces, is particularly easy to because the deformation of upper and lower substrate is led
Cause adjacent two soldered balls bridge joint (bridge) and electrical short.For fear of the size limitation of soldered ball, so instead result in adjacent two soldered balls
Spacing be difficult to meet thin space（fine pitch）Specification.
Content of the invention
The invention relates to a kind of semiconductor package assembly and a manufacturing method thereof, semiconductor package part meets thin space rule
Lattice.
According to the present invention it is proposed that a kind of semiconductor package part.Semiconductor package part include a upper substrate, an infrabasal plate, one
First packaging body, one first cabling and a protective layer.Upper substrate has a lateral surface.Infrabasal plate has outside a upper surface and one
Face, the upper surface of infrabasal plate is relative with upper substrate and lateral surface of infrabasal plate protrudes past the lateral surface of upper substrate.First encapsulation
Body is formed between upper substrate and infrabasal plate, and has a lateral surface, and the lateral surface of the first packaging body is from upper substrate toward infrabasal plate
Direction tilt with extending out.First cabling is formed at the lateral surface of the first packaging body and is electrically connected with upper substrate and infrabasal plate.Protect
Sheath covers lateral surface and first cabling of the first packaging body.
According to the present invention it is proposed that a kind of manufacture method of semiconductor package part.Manufacture method comprises the following steps.There is provided one
Upper substrate；One infrabasal plate is provided；Form a packaging body between upper substrate and infrabasal plate；Form one first Cutting Road through upper base
Plate, the first packaging body and infrabasal plate, make packaging body formed a lateral surface, wherein the lateral surface of packaging body from upper substrate toward infrabasal plate
Direction tilt with extending out；Form a cabling on the lateral surface of packaging body, wherein cabling is electrically connected with upper substrate and infrabasal plate；
Form the lateral surface that a protective layer covers cabling and packaging body；Form one second Cutting Road at least through protective layer.
It is that the above of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, make in detail
It is described as follows：
Brief description
Figure 1A illustrates the outside drawing of the semiconductor package part according to one embodiment of the invention.
Figure 1B illustrates the sectional view in Figure 1A along direction 1B-1B '.
Fig. 1 C illustrates the top view of Figure 1B.
Fig. 2, it illustrates the sectional view of the semiconductor package part according to one embodiment of the invention.
Fig. 3 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 6 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 7, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 8 A to 8F illustrates the process drawing of the semiconductor package part of Figure 1B.
Fig. 9 A to 9C illustrates the process drawing of the semiconductor package part of Fig. 2.
Figure 10 A to 10E illustrates the process drawing of the semiconductor package part 40 of Fig. 4.
Figure 11 illustrates the process drawing of the semiconductor package part of Fig. 5.
Figure 12 A to 12C illustrates the process drawing of the semiconductor package part of Fig. 6.
Figure 13 A to 13D illustrates the process drawing of the semiconductor package part of Fig. 7.
Main element symbol description：
100、200、300、400、500、600、700：Semiconductor package part
110：Upper substrate
111：Upper electrical components
1111、1211：Line layer
1113、1213：Conductive pad
1112、1212：Electrically projection
110b：Lower surface
110s、1111s、1112s、1113s、120s、1211s、1212s、1213s、130s、140s、150s、630s、
730s：Lateral surface
110s2：Second lateral surface
120：Infrabasal plate
120r：Groove
120u、1212u：Upper surface
121：Lower electrical components
125：Chip
1251：Electrical contact
126：Bonding coat
130、630：First packaging body
130s1：Laterally face
130s2：Directly to face
140、640：First cabling
150：Protective layer
630r：First groove
730：Second packaging body
730r：Second groove
740：Second cabling
D1：Directly to feed
D2：Cross feed
P1：First Cutting Road
P2：Second Cutting Road
P3：3rd Cutting Road
P4：4th Cutting Road
Specific embodiment
Refer to Figure 1A, it illustrates the outside drawing of the semiconductor package part according to one embodiment of the invention.The present embodiment
Semiconductor package part 100 has side cabling, and side cabling has the feature of fine rule width and thin space, therefore can reduce semiconductor package
The size of piece installing 100, or the configuration elasticity of semiconductor package part 100 can be lifted.Additionally, the side of semiconductor package part 100
Face provides a big configuration area, can increase quantity and the configuration elasticity of lateral cabling, and can solve to utilize solder
Or stannum ball as upper and lower base plate electrical connection element when, produced bridge joint problem.
Semiconductor package part 100 includes upper substrate 110, infrabasal plate 120, chip 125（Figure 1B）, bonding coat 126（Figure 1B）、
First packaging body 130, several first cablings 140 and protective layer 150（For becoming apparent from representing the first cabling 140, protective layer 150 with
Dotted lines）.
Refer to Figure 1B, it illustrates the sectional view in Figure 1A along direction 1B-1B '.
Upper substrate 110 is, for example, single layer substrate or multilager base plate.In this example, upper substrate 110 as non-active element,
That is, upper substrate 110 does not comprise any active member（As active chip or active lines）, such as one printed circuit board (PCB) (Printed
Circuit Board).In another example, upper substrate 110 can comprise active lines or active chip and become active member.Upper base
Plate 110 has lower surface 110b and lateral surface 110s.
Upper substrate 110 includes electrical components 111 at least, wherein goes up electrical components 111 and includes at least one line layer
1111 and at least one electrical projection 1112.Upper electrical components 111 are electrically connected at infrabasal plate 120 through the first cabling 140.This
Outward, line layer 1111 and electrical projection 1112 are respectively provided with lateral surface 1111s and 1112s, due to lateral surface 1111s and 1112s
It is to be formed in same cutting technique, therefore lateral surface 1111s is generally alignd with 1112s, such as flushes.Electrically projection 1112 can wrap
Include conductive pole, solder or other conductive projections.In this example, electrical projection is formed for after solder cutting, via electrical projection
1112 design can increase upper substrate 110 and the contact area of the first cabling 140, can lift the reliability on electrically or signal passes
Defeated speed.
Infrabasal plate 120 is, for example, single layer substrate or multilager base plate.In this example, infrabasal plate 120 as non-active element,
That is, infrabasal plate 120 does not comprise any active member（As active chip or active lines）, such as one printed circuit board (PCB) (Printed
Circuit Board).In another example, infrabasal plate 120 can comprise active lines or active chip and become active member.
Infrabasal plate 120 includes at least once electrical components 121, wherein descends electrical components 121 to include at least one line layer
1211 and at least one electrical projection 1212.Lower electrical components 121 are electrically connected at the upper of upper substrate 110 through the first cabling 140
Electrical components 111.Additionally, electrical projection 1212 has upper surface 1212u, the upper surface 1212u of the present embodiment is plane.First
Cabling 140 covers the upper surface 1212u of electrical projection 1212, to be electrically connected with electrical projection 1212.Electrically projection 1212 can wrap
Include conductive pole, solder or other conductive projections.In this example, electrical projection 1212 is formed for after solder cutting, electrical projection
1212 can switch to the surface of electrical projection 1212 or the inside being switched to electrical projection 1212, because electrical projection 1212 has when being formed
There is a thickness, therefore can increase tolerance during cutting, improve the yield that infrabasal plate makes.
Infrabasal plate 120 has upper surface 120u and lateral surface 120s.The upper surface 120u of infrabasal plate 120 and upper substrate 110
Lower surface 110b relatively.The lateral surface 120s of infrabasal plate 120 protrudes past the lateral surface 110s of upper substrate 110.In this example, under
The whole lateral surface 120s of substrate 120 protrudes past the whole lateral surface 110s of upper substrate 110, makes the horizontal face of infrabasal plate 120
The long-pending horizontal area more than upper substrate 110s.In another embodiment, wherein one lateral surface 120s of infrabasal plate 120 protrudes past
The corresponding lateral surface 110s of substrate 110, and another lateral surface 120s can not protrude past the corresponding lateral surface of upper substrate 110
110s.
Chip 125 is between upper substrate 110 and infrabasal plate 120.In the present embodiment, chip 125 is located at infrabasal plate 120
On.Chip 125 is e.g. on infrabasal plate 120 and electrical through at least one electrical contact 1251 with its active faced downwards position
It is connected to infrabasal plate 120.In another embodiment, chip 125 can be on upper substrate 110.
Bonding coat 126 bonding upper substrate 110 and chip 125, with firm relative position between upper substrate 110 and chip 125
Put.In another embodiment, chip 125 is on upper substrate 110, and bonding coat 126 bonding infrabasal plate 120 and chip 125, with steady
Gu the relative position between infrabasal plate 120 and chip 125.In another embodiment, also can omit bonding coat 126, under here design,
First packaging body 130 can be filled in the space between chip 115 and upper substrate 110.
First packaging body 130 may include phenolic group resin（Novolac-based resin）, epoxy（epoxy-
based resin）, silicone（silicone-based resin）Or other suitable coverings.First packaging body 130 is also
May include suitable filler, the e.g. silicon dioxide of powdery.The first packaging body 130 can be formed using several encapsulation technologies,
E.g. compression forming（compression molding）, liquid encapsulation type（liquid encapsulation）, injection moulding
（injection molding）Or tuberculosiss molding（transfer molding）.
First packaging body 130 is formed between upper substrate 110 and infrabasal plate 120, and coating chip 125.First packaging body
130 have one from upper substrate 110 toward the direction of infrabasal plate 120 be the lateral surface 130s tilting with extending out.Lateral surface 130s be by
Cutter or cut are formed.In the present embodiment, lateral surface 130s is a ladder lateral surface, and it includes several horizontal face 130s1
And directly to face 130s2, the horizontal face 130s1 connecting constitutes an accommodation space with straight to face 130s2, can accept and accommodate first and walk
The material of line 140.
First cabling 140 e.g. conducting resinl is formed at the lateral surface 130s of the first packaging body 130 with coating technique.?
During one cabling 140 coats the lateral surface 130s of the first packaging body 130, horizontal face 130s1 can accept conducting resinl, makes to lead
Electric glue avoids the direction flowing toward infrabasal plate 120 too quickly via the buffering of horizontal face 130s1.So, first can be avoided to walk
Line 140 breaks.In another embodiment, if conducting resinl no disconnection problem（For example, it is suitably designed the outside of the first packaging body 130
The gradient of face 130s or the generation type changing the first cabling 130, for example, form the first cabling 130 with plating mode）, then
The lateral surface 130s of one packaging body 130 may be designed to curved surface or plane.
First cabling 140 is electrically connected with upper substrate 110 and infrabasal plate 120 along the lateral surface 130s of the first packaging body 130.Phase
Electrical connection element compared with other species（As conductive pole and solder ball）, the present embodiment is special via having fine rule width and thin space
The first cabling 140 levied comes electrical connection upper substrate 110 and infrabasal plate 120, thus can reduce semiconductor package part 100 size,
The configuration of lifting semiconductor package part 100 is elastic and makes semiconductor package part 100 meet thin space specification, additionally, can
Remove alignment issues when engaging for the upper and lower electrical connection element from.In one embodiment, it is micro- that the width of the first cabling 140 can be as small as 25
Rice or even more little, the spacing of adjacent 2 first cablings 140 can be as small as 50 microns or even more little.
Protective layer 150 covers lateral surface 130s and first cabling 140 of the first packaging body 130, to avoid the first packaging body
130 lateral surface 130s and the first cabling 140 are subject to the excessive damage of environment.Additionally, protective layer 150, the first cabling 140, line
Road floor 1211 and electrical projection 1212 are respectively provided with lateral surface 150s, 140s, 1211s and 1212s.Due to lateral surface 150s,
140s, 1211s and 1212s are to be formed in same cutting technique, therefore lateral surface 150s, 140s, 1211s and 1212s are generally
Alignment, such as flushes.
Protective layer 150 can be identical material or different materials with the first packaging body 130.Protective layer 150 and the first packaging body
130 can comprise filler (filler), and in an embodiment, (filler comprises several the mean diameter of the filler of protective layer 150
Particle filled composite) less than the first packaging body 130 implant mean diameter, therefore protective layer 150 can insert the first packaging body 130
Lateral surface 130s and the first cabling 140 between space and horizontal face 130s1 and straight to the corner between the 130s2 of face,
Equably to cover lateral surface 130s and first cabling 140 of the first packaging body 130, the product of bubble in encapsulating structure can be reduced
Raw.
Refer to Fig. 1 C, it illustrates the top view of Figure 1B.As seen from the figure, 1112 points of the several electrical projection of upper substrate 110
It is distributed in the marginal area of upper substrate 110, and is not located at the zone line of upper substrate 110, so this is not used to limit present invention enforcement
Example.Similarly, the several electrical projection 1212 of infrabasal plate 120 is distributed in the marginal area of infrabasal plate 120, and is not located at infrabasal plate
120 zone line, so this is not used to limit the embodiment of the present invention.
Refer to Fig. 2, it illustrates the sectional view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part
200 include upper substrate 110, infrabasal plate 120, chip 125, bonding coat 126, the first packaging body 130, several first cablings 140 and
Protective layer 150.From unlike Figure 1A, the protective layer 150 of the present embodiment covers the whole lateral surface of infrabasal plate 120.Concrete and
Speech, protective layer 150 covers lateral surface 140s, the lateral surface 1211s of line layer 1211 of the first cabling 140 and electrical projection 1212
Lateral surface 1212s, wherein lateral surface 140s, 1211s is generally alignd with 1212s, such as flushes.Due to the first cabling 140
The lateral surface 1212s of lateral surface 140s, the lateral surface 1211s of line layer and electrical projection is protected layer 150 and is covered, not
Expose and contact with the external world, more preferably product reliability therefore can be provided.
Refer to Fig. 3, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 300 includes upper substrate 110, infrabasal plate 120, chip 125, bonding coat 126, the first packaging body 130, several first cablings 140
And protective layer 150.In the present embodiment, the lateral surface 140s of the first cabling 140, the lateral surface 1211s of line layer 1211 with electrically
The lateral surface 1212s of projection 1212 generally aligns, and such as flushes.The lateral surface 1211s of line layer 1211 and electrical projection 1212
Lateral surface 1212s constitute infrabasal plate 120 the first lateral surface 120s1.Infrabasal plate 120 separately has one second lateral surface 120s2,
Generally align with the lateral surface 150s of protective layer 150, due to the first lateral surface 120s1 from the second lateral surface 120s2 in different
Formed in two cutting techniques, therefore it is horizontal to have one between the first lateral surface 120s1 of infrabasal plate 120 and the second lateral surface 120s2
Segment difference, for example, the first lateral surface 120s1 of infrabasal plate 120 inside contracts relative to the second lateral surface 120s2.Due to the first cabling 140
The lateral surface 1212s of lateral surface 140s, the lateral surface 1211s of line layer and electrical projection is protected layer 150 and is covered, not
Expose and contact with the external world, more preferably product reliability therefore can be provided.
Refer to Fig. 4, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 400 includes upper substrate 110, infrabasal plate 120, chip 125, bonding coat 126, the first packaging body 130, several first cablings 140
And protective layer 150.From the upper surface 1212u and surface that unlike Figure 1A, the electrical projection 1212 of infrabasal plate 120 exposes
1212s receives the covering of the first cabling 140, and does not expose from the lateral surface 150s of protective layer 150, due to the first cabling 140
With the upper surface 1212u of the electrical projection 1212 that the contact area of the electrical projection 1212 of infrabasal plate 120 comprises infrabasal plate 120 and
Side 1212s, therefore contact area increase, and can lift the reliability on electrically or signal transmission speed.
Refer to Fig. 5, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 500 includes upper substrate 110, infrabasal plate 120, chip 125, bonding coat 126, the first packaging body 130, several first cablings 140
And protective layer 150.From unlike Figure 1A, the upper electrical components 111 of upper substrate 110 include at least one conductive pad 1113.Circuit
Layer 1111 and conductive pad 1113 are respectively provided with lateral surface 1111s and 1113s, because lateral surface 1111s and 1113s is in all
Cut in technique and formed, therefore lateral surface 1111s is generally alignd with 1113s, such as flushes.
The lower electrical components 121 of infrabasal plate 120 include at least one conductive pad 1213.Line layer 1211, conductive pad 1113, walk
Line 140 and protective layer 150 are respectively provided with lateral surface 1211s, 1213s, 140s and 150s, due to lateral surface 1211s, 1213s,
140s and 150s is to be formed in same cutting technique, therefore lateral surface 1211s, 1213s, 140s are generally alignd with 150s, such as
Flush.Additionally, in order to expose conductive pad 1213, the lateral surface 130s of the first packaging body 130 extends to inside infrabasal plate 120, and
Form a groove 120r exposing conductive pad 1213 in substrate 110, such first cabling 140 can pass through groove 120r and extends to and connects
Pad 1213.Because the area of conductive pad 1213 may be typically less than the area of electrical projection, therefore easily realize height and walk line density
Design.
In another embodiment, the semiconductor package of Fig. 5 is built 500 and also can be omitted conductive pad 1113 and/or 1213.When omission is led
During electrical pad 1213, the first cabling 140 is formed directly on line layer 1211, and under here design, line layer 1211 can be formed with table
Face process layer（surface finishing）.
Refer to Fig. 6, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 600 includes upper substrate 110, infrabasal plate 120, chip 125, bonding coat 126, the first packaging body 630, several first cablings 640
And protective layer 150.
In the present embodiment, the first packaging body 630 has lateral surface 630s, and wherein lateral surface 630s is, for example, plane or song
Face.First packaging body 630 is by laser activation dielectric material（laser-activated dielectric material）Make,
It forms at least one first groove 630r via laser.The cell wall that laser can activate first groove 630r goes to form a Seed Layer
（Do not illustrate）, make first groove 630r conductive.Because first groove 630r can be conductive, therefore first can be formed using plating mode
Cabling 640 is in first groove 630r；That is, the first cabling 640 is plating line.Electrical connection compared to other species
Element（As conductive pole and solder ball）, first cabling 640 of the present embodiment has the feature that live width is thin and spacing is thin, therefore can reduce
The size of semiconductor package part 600, the configuration elasticity of lifting semiconductor package part 600, and so that semiconductor package part 600 is accorded with
Close the specification of thin space, additionally, alignment issues when engaging for the upper and lower electrical connection element can be removed from.
Refer to Fig. 7, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 700 include upper substrate 110, infrabasal plate 120, chip 125, bonding coat 126, the first packaging body 630, several first cablings 640,
Protective layer 150, the second packaging body 730, several second cablings 740.From unlike the semiconductor package part 700 of Fig. 6, quasiconductor
Packaging part 700 includes multilamellar routing layer, can increase the cabling quantity of semiconductor package part 700, and lifting configuration elasticity.
Second packaging body 730 covers the lateral surface 630s of the first cabling 640 and the first packaging body 630.Second packaging body 730
It is made up of laser activation dielectric material, it forms at least one second groove 730r via laser, and laser activation second groove
The cell wall of 730r forms a Seed Layer（Do not illustrate）, make second groove 730r conductive.Because second groove 730rr can be conductive,
Therefore electrodepositable the second cabling 740 is in second groove 730r；That is, the second cabling 740 is plating line.Plant compared to other
The electrical connection element of class（As conductive pole and solder ball）, second cabling 740 of the present embodiment has that live width is thin and spacing is thin
Feature, therefore the configuration elasticity of the size of semiconductor package part 700, lifting semiconductor package part 700 can be reduced, and make partly to lead
Body packaging part 700 meets the specification of thin space, additionally, alignment issues when engaging for the upper and lower electrical connection element can be removed from.
Additionally, protective layer 150 covers lateral surface 730s and second cabling 740 of the second packaging body 730.
Refer to Fig. 8 A to 8F, it illustrates the process drawing of the semiconductor package part 100 of Figure 1B.
As shown in Figure 8 A, upper substrate 110 is provided.Upper substrate 110 includes electrical components 1111 at least, upper electrical components
111 include a plurality of line layer 1111 and multiple electrical projection 1112.In the present embodiment, upper substrate 810 is strip substrate, its definition
Multiple encapsulation unit areas, single package cellular zone corresponds to final semiconductor package part 100.This large-area upper substrate 810 can be same
When with multiple chips 125 complete packaging technology.
As shown in Figure 8 A, infrabasal plate 120 is provided.Infrabasal plate 120 includes at least once electrical components 1211, lower electrical components
1211 include a plurality of line layer 1211 and multiple electrical projection 1212.In the present embodiment, infrabasal plate 820 is strip substrate, and it is fixed
The multiple encapsulation unit area of justice, single package cellular zone corresponds to final semiconductor package part 100., this large-area infrabasal plate 820 can
Complete packaging technology with multiple chips 125 simultaneously.
As shown in Figure 8 A, setting at least one chip 125 is on infrabasal plate 820.Chip 125 passes through bonding coat 126 and upper base
Plate 810 binds.
As shown in Figure 8 B, can adopt e.g. compression forming, liquid encapsulation type, injection moulding or tuberculosiss molding, form the
One packaging body 130 between upper substrate 810 and infrabasal plate 820, the wherein first packaging body 130 coating chip 125, upper substrate 810
Electrical projection 1112 and infrabasal plate 820 electrical projection 1212.
As shown in Figure 8 C, cutter or laser can be adopted, form at least one first Cutting Road P1 through upper substrate 810, first
Packaging body 130 and infrabasal plate 120, make upper substrate 810 form the upper substrate 110 of multiple unification, and make the first packaging body 130 shape
Become lateral surface 130s, wherein lateral surface 130s is to tilt with extending out from upper substrate 110 toward the direction of infrabasal plate 120.
The direction of feed of cutting tool in cutting process, can be changed, form the lateral surface 130s with hierarchic structure.Example
As available same cutter, in the way of directly crossing feed D2 to feed D1 collocation, forms ladder lateral surface 130s.Lateral surface
130s includes several horizontal face 130s1 and directly to face 130s2, and the horizontal face 130s1 connecting is housed to face 130s2 composition one with straight
Space, can accept and accommodate the material of follow-up first cabling 140.
After cutting, line layer 1111 and electrical projection 1112 form lateral surface 1111s and 1112s, wherein lateral surface respectively
1111s is generally alignd with 1112s, such as flushes.Additionally, the first Cutting Road P1 terminates in the electrical projection 1212 of infrabasal plate 120, and
Form upper surface 1212u in electrical projection 1212, wherein upper surface 1212u is, for example, plane.However, regarding the profile of cutting tool
Depending on, upper surface 1212u can also be corresponding curved surface or inclined-plane.
As in fig. 8d, at least one first cabling 140 can be formed in the first packaging body 130 using e.g. coating technique
Lateral surface 130s on, the wherein first cabling 140 is electrically connected with upper substrate 110 along the lateral surface 130s of first packaging body 130
The electrically electrical projection 1212 of projection 1112 and infrabasal plate 120.In the present embodiment, the first cabling 140 is conducting resinl.Additionally, two
First cabling 140 can share same electrical projection 1212, and in follow-up cutting technique, this same electrical projection 1212 can be cut
Become two isolated parts.
As illustrated in fig. 8e, protective layer 150 can be formed and covers the first cabling using e.g. coating technique or filler technology
140 and first packaging body 130 lateral surface 130s.
As shown in Figure 8 F, at least one second Cutting Road P2 can be formed at least through protection using e.g. cutter or laser
Layer 150, infrabasal plate 820, including line layer 1211 and the electrical projection 1212 of infrabasal plate 820 of infrabasal plate 820, make infrabasal plate
The infrabasal plate 120 of the 820 multiple unification of formation, to form at least one semiconductor package part 100 as shown in Figure 1B.After cutting,
Protective layer 150, the line layer 1211 of infrabasal plate 120 and the electrical projection 1212 of infrabasal plate 120 formed respectively lateral surface 150s,
1211s and 1212s, wherein lateral surface 150s, 1211s is generally alignd with 1212s, such as coplanar.
Refer to Fig. 9 A to 9C, it illustrates the process drawing of the semiconductor package part 200 of Fig. 2.
As shown in Figure 9 A, at least one second Cutting Road P2 can be formed through the first cabling using e.g. cutter or laser
140 with the whole thickness of infrabasal plate 120, to cut off infrabasal plate 820.After cutting, the first cabling 140, infrabasal plate 120 electrically convex
The line layer 1211 of block 1212 and infrabasal plate 120 forms lateral surface 140s, 1212s and 1211s respectively, wherein lateral surface 140s,
1212s is generally alignd with 1211s, such as flushes.
As shown in Figure 9 B, protective layer 150 can be formed and covers the first cabling using e.g. coating technique or filler technology
140 lateral surface 140s, the lateral surface 130s of the first packaging body 130, the lateral surface of the electrical projection 1212 of infrabasal plate 120
The lateral surface 1211s of the line layer 1211 of 1212s and infrabasal plate 120.
As shown in Figure 9 C, one the 3rd Cutting Road P3 can be formed whole through protective layer 150 using e.g. cutter or laser
Individual thickness, to form at least one semiconductor package part 200 as shown in Figure 2.
The manufacture method of the semiconductor package part 300 of Fig. 3 is similar in appearance to semiconductor package part 200, different places, second
Cutting Road P2 is through the segment thickness of infrabasal plate 120；Then, after protective layer 150 formation, form at least one the 3rd Cutting Road P3
Through remaining thickness of protective layer 150 and infrabasal plate 120, to form at least one semiconductor package part 300 as shown in Figure 3.
Refer to Figure 10 A to 10E, it illustrates the process drawing of the semiconductor package part 400 of Fig. 4.
As shown in Figure 10 A, form the first packaging body 130 between upper substrate 810 and infrabasal plate 820, the wherein first encapsulation
Body 130 coating chip 125.In the present embodiment, in infrabasal plate 820, the region between two chips 125 is configured with two or two rows electricity
Property projection 1212, makes two chips 115 respectively be configured to single or single electrical projection 1212.
As shown in Figure 10 B, cutter or laser can be adopted, form at least one first Cutting Road P1 through upper substrate 810, first
Packaging body 130 and infrabasal plate 820, make large-area upper substrate 810 form single upper substrate 110, and the first packaging body 130 shape
Become lateral surface 130s, wherein lateral surface 130s is to tilt with extending out from upper substrate 110 toward the direction of infrabasal plate 820.
As illustrated in figure 10 c, at least one first cabling 140 can be formed in the first packaging body 130 using e.g. coating technique
Lateral surface 130s on, the wherein first cabling 140 is electrically connected with upper substrate 110 along the lateral surface 130s of first packaging body 130
The electrically electrical projection 1212 of projection 1112 and infrabasal plate 120.In the present embodiment, 2 first cablings 140 are respectively from different two
Electrically projection 1212 is electrically connected with, and in follow-up cutting technique, can form the completely isolated two electrical projections of at least one Cutting Road
1212.
As shown in Figure 10 D, protective layer 150 can be formed and covers the first cabling using e.g. coating technique or filler technology
140 and first packaging body 130 lateral surface 130s.
As shown in figure 10e, one second Cutting Road P2 can be formed at least through protective layer using e.g. cutter or laser
150th, the first cabling 141 and the line layer 1211 of infrabasal plate 820, make infrabasal plate 820 form the infrabasal plate 120 of multiple unification,
To form at least one semiconductor package part 400 as shown in Figure 4.After cutting, protective layer 150, the first cabling 140 and infrabasal plate
120 line layer 1211 forms lateral surface 150s, 140s and 1211s, wherein lateral surface 150s, 140s and 1211s substantially respectively
Upper alignment, such as flushes.
In the present embodiment, the first Cutting Road P1 can not be through the electrical projection 1212 of infrabasal plate 120.In another embodiment,
First Cutting Road P1 can make the lateral surface of electrical projection 1212 expose, to form phase through the electrical projection 1212 of infrabasal plate 120
It is similar to the structure of the semiconductor package part 100 of Figure 1B.
Refer to Figure 11, it illustrates the process drawing of the semiconductor package part 500 of Fig. 5.Can using e.g. cutter or
Laser, forms at least one first Cutting Road P1 through upper substrate 810, the first packaging body 130 and infrabasal plate 820, makes upper substrate 810
Form the upper substrate 110 of multiple unification, the first packaging body 130 forms lateral surface 130s, and wherein lateral surface 130s is from upper substrate
110 is to tilt with extending out toward the direction of infrabasal plate 820.
In the present embodiment, the upper electrical components 111 of upper substrate 110 include in be embedded in upper substrate 110 line layer 1111
And conductive pad 1113.First Cutting Road P1 is through the whole thickness of upper substrate 110.Additionally, the lower electrical components of infrabasal plate 820
121 include in be embedded in infrabasal plate 820 line layer 1211 and conductive pad 1213.First Cutting Road P1 is through infrabasal plate 820
Segment thickness, and form a groove 120r.Groove 120r expose in the conductive pad 1213 that buries, make the first follow-up cabling 140 can
It is electrically connected at conductive pad 1213 via groove 120r.In another embodiment, also can omit conductive pad 1213, make the first cabling
140 via groove 120r directly contact line layer 1111.
Remaining step of the manufacture method of semiconductor package part 500 of Fig. 5 is similar in appearance to the manufacturer of semiconductor package part 100
The corresponding step of method, holds this and repeats no more.
Refer to Figure 12 A to 12C, it illustrates the process drawing of the semiconductor package part 600 of Fig. 6.
As illustrated in fig. 12, cutter or laser can be adopted, form at least one first Cutting Road P1 through upper substrate 810, first
Packaging body 130 and infrabasal plate 820, make the first packaging body 630 form lateral surface 130s, and wherein lateral surface 630s is plane, its from
Upper substrate 110 tilts toward the direction of infrabasal plate 120 with extending out.In another embodiment, lateral surface 630s can be curved surface.This enforcement
In example, the first packaging body 630 is laser activation dielectric material, and it can go out the Seed Layer of a conduction with laser activation.
As shown in Figure 12 B, at least one first groove 630r is formed with laser, wherein first groove 630r is from lateral surface 630s
Inside toward the first packaging body 630 extends, and connects the upper electrical components 111 of upper substrate 110 and the lower electrical unit of infrabasal plate 120
Part 121.The cell wall of first groove 630r forms Seed Layer under laser activation.
As indicated in fig. 12 c, at least one first cabling, via conductive Seed Layer, can be formed using e.g. plating mode
640 in first groove 630r.Because upper electrical components 111 and lower electrical components 121 can be conductive, therefore the first cabling 640 also shape
In the upper electrical components of Cheng Yu 111 and lower electrical components 121, to be electrically connected with upper electrical components 111 and lower electrical components 121.
Remaining step of the manufacture method of semiconductor package part 600 of Fig. 6 is similar in appearance to the manufacturer of semiconductor package part 100
The corresponding step of method, holds this and repeats no more.
Refer to Figure 13 A to 13D, it illustrates the process drawing of the semiconductor package part 700 of Fig. 7.
As shown in FIG. 13A, the second packaging body 730 can be formed and covers the first cabling 640 and the using e.g. coating technique
The lateral surface 630s of one packaging body 630.Second packaging body 730 is e.g. made up of laser activation dielectric material.
As shown in Figure 13 B, cutter can be adopted, form another circuit through upper substrate 810 at least one the 4th Cutting Road P4
Layer 1111 ' and the second packaging body 730, until exposing another electrical projection 1212 '.After cutting, upper substrate 810 forms multiple single
The upper substrate 110 changed, line layer 1111 ' forms a lateral surface 1111s exposing, and the electrical projection 1212 ' shape of infrabasal plate 820
Become a upper surface 1212u.
As shown in fig. 13 c, at least one second groove 730r is formed with laser, wherein second groove 730r is from lateral surface 730s
Inside toward the second packaging body 730 extends, and connects the line layer 1111 ' of upper substrate 110 and the electrical projection of infrabasal plate 820
1212’.The cell wall of second groove 730r forms Seed Layer under laser activation.
As illustrated in figure 13d, at least one second cabling, via conductive Seed Layer, can be formed using e.g. plating mode
740 in second groove 730r.Because the line layer 1111 ' of upper substrate 110 and the electrical projection 1212 ' of infrabasal plate 820 can be led
Electricity, therefore the second cabling 740 is also formed on line layer 1111 ' and electrical projection 1212 ', be electrically connected with line layer 1111 ' and
Electrically projection 1212 '.
In sum although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.This
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when can make various changes
With retouching.Therefore, protection scope of the present invention is worked as and is defined depending on those as defined in claim.
Claims (25)
1. a kind of semiconductor package part, including：
One upper substrate, has a lateral surface；
One infrabasal plate, has a upper surface and a lateral surface, and this upper surface of this infrabasal plate is relative with this upper substrate and this lower base
This lateral surface of plate protrudes past this lateral surface of this upper substrate；
One first packaging body, is formed between this upper substrate and this infrabasal plate, and has a lateral surface, this first packaging body should
Lateral surface tilts from this upper substrate toward the direction of this infrabasal plate with extending out；
One first cabling, is formed at this lateral surface of this first packaging body and is electrically connected with this upper substrate and this infrabasal plate；And
One protective layer, covers this lateral surface and this first cabling of this first packaging body.
2. semiconductor package part as claimed in claim 1 is it is characterised in that this lateral surface of this first packaging body is a ladder
Lateral surface.
3. semiconductor package part as claimed in claim 2 is it is characterised in that this first cabling is conducting resinl.
4., it is characterised in that this cascaded surface includes several horizontal faces, those are horizontal for semiconductor package part as claimed in claim 3
Carry this first cabling to face.
5. semiconductor package part as claimed in claim 1 it is characterised in that this lateral surface of this first packaging body be curved surface or
Plane.
6. semiconductor package part as claimed in claim 1 is it is characterised in that this first packaging body is by laser activation dielectric material
Material is made.
7. semiconductor package part as claimed in claim 6 is it is characterised in that this first cabling is plating line.
8. semiconductor package part as claimed in claim 6 is it is characterised in that this first packaging body includes：
One first groove, extends toward this first encapsulation in vivo from this lateral surface of this first packaging body；
Wherein, this first cabling is inserted in this first groove.
9. semiconductor package part as claimed in claim 8 is it is characterised in that further include：
One second packaging body, covers this first cabling and has a second groove, and this second groove is from this second packaging body
Side extends toward the inside of this second packaging body, and wherein this second packaging body is made up of laser activation dielectric material；And
One second cabling, is formed in this second groove of this second packaging body；
Wherein, this protective layer more covers this second packaging body and this second cabling.
10. semiconductor package part as claimed in claim 1 is it is characterised in that this upper substrate includes electrical components on, on this
Electrical components have a lateral surface, and on this, this lateral surface of electrical components exposes from this lateral surface of this first packaging body, and this
One cabling along this first packaging body this lateral surface via expose this on electrical components extend to this infrabasal plate.
11. semiconductor package parts as claimed in claim 1 are it is characterised in that this infrabasal plate includes electrical components, under this
Electrical components have plane on, and this first cabling extends to covering from this upper substrate along this lateral surface of this first packaging body should
Plane on this of lower electrical components.
12. semiconductor package parts as claimed in claim 1 are it is characterised in that this infrabasal plate includes electrical components, under this
Electrical components have a lateral surface, and this first cabling covers this lateral surface of this lower electrical components.
13. semiconductor package parts as claimed in claim 1 are it is characterised in that this infrabasal plate includes electrical components, under this
It is embedded in this infrabasal plate, this infrabasal plate has a groove, this groove exposes this lower electrical components, this first cabling prolongs in electrical components
Extend and cover this lower electrical components exposed.
14. semiconductor package parts as claimed in claim 1 are it is characterised in that this infrabasal plate and this protective layer respectively have outside one
Side, this lateral surface of this infrabasal plate is alignd with this lateral surface of this protective layer.
15. semiconductor package parts as claimed in claim 1 are it is characterised in that this infrabasal plate has one first lateral surface and one
Second lateral surface, this protective layer has a lateral surface, and this first lateral surface of this infrabasal plate inside contracts relative to this second lateral surface, should
This lateral surface alignment of this this protective layer of the second lateral surface of infrabasal plate.
16. semiconductor package parts as claimed in claim 1 it is characterised in that this infrabasal plate has a lateral surface, this protective layer
Cover this lateral surface whole of this infrabasal plate.
A kind of 17. manufacture methods of semiconductor package part, including：
One upper substrate is provided；
One infrabasal plate is provided；
Form a packaging body between this upper substrate and this infrabasal plate；
Form one first Cutting Road and pass through this upper substrate, this packaging body and this infrabasal plate, make this packaging body form a lateral surface, its
In this lateral surface of this packaging body tilt with extending out from this upper substrate toward the direction of this infrabasal plate；
Form a cabling on this lateral surface of this packaging body, wherein this cabling is electrically connected with this upper substrate and this infrabasal plate；
Form this lateral surface that a protective layer covers this cabling and this packaging body；
Form one second Cutting Road at least through this protective layer.
18. manufacture methods as claimed in claim 17 are passed through this upper substrate, are somebody's turn to do it is characterised in that forming this first Cutting Road
Packaging body is included with the step of this infrabasal plate：
By cross feed and straight to cutting this packaging body in the way of feed, make this packaging body form a ladder lateral surface.
19. manufacture methods as claimed in claim 17 are it is characterised in that this packaging body is by laser activation dielectric material system
Become.
20. manufacture methods as claimed in claim 19 are it is characterised in that further include：
One groove is formed in this packaging body with laser, this groove extends toward this encapsulation in vivo from this lateral surface of this packaging body；With
And
Include in the step forming this lateral surface in this packaging body for this cabling：
Electroplate this cabling to insert in this groove.
21. manufacture methods as claimed in claim 17 are it is characterised in that this cabling is to be formed with applying conductive glue.
22. manufacture methods as claimed in claim 17 are it is characterised in that this upper substrate includes electrical components on；
In the step forming this first Cutting Road, this first Cutting Road passes through electrical components on this, makes electrical components shape on this
Become a lateral surface, and on this, this lateral surface of electrical components exposes from this lateral surface of this packaging body；
In the step forming this cabling, this cabling electrical components on this exposing extend to along this lateral surface of this packaging body
This infrabasal plate.
23. manufacture methods as claimed in claim 17 are it is characterised in that this infrabasal plate includes electrical components；
In the step forming this first Cutting Road, this first Cutting Road passes through this lower electrical components, makes this lower electrical components shape
Become plane on；
In the step forming this cabling, this cabling extends to this lower electricity of covering from this upper substrate along this lateral surface of this packaging body
Plane on this of property element.
24. manufacture methods as claimed in claim 17 are it is characterised in that this infrabasal plate includes electrical components；
In the step forming this first Cutting Road, this first Cutting Road passes through this lower electrical components, makes this lower electrical components shape
Become a lateral surface；
In the step forming this cabling, this cabling covers this lateral surface of this lower electrical components.
25. manufacture methods as claimed in claim 17 are it is characterised in that pass through this protective layer in forming this second Cutting Road
In step, this second Cutting Road passes through this protective layer and this infrabasal plate, makes this infrabasal plate and this protective layer each formation one lateral surface,
Wherein this lateral surface of this infrabasal plate is alignd with this lateral surface of this protective layer.
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| CN201310342762.5A CN104347575B (en) | 2013-08-07 | 2013-08-07 | Semiconductor package assembly and a manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310342762.5A CN104347575B (en) | 2013-08-07 | 2013-08-07 | Semiconductor package assembly and a manufacturing method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04130756A (en) * | 1990-09-21 | 1992-05-01 | Mitsubishi Electric Corp | Semiconductor device |
| CN101930929A (en) * | 2009-06-26 | 2010-12-29 | 日月光半导体（上海）股份有限公司 | Manufacturing method of packaging base plate provided with side surface lines |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006086149A (en) * | 2004-09-14 | 2006-03-30 | Toshiba Corp | Semiconductor device |
| US8552546B2 (en) * | 2009-10-06 | 2013-10-08 | Samsung Electronics Co., Ltd. | Semiconductor package, semiconductor package structure including the semiconductor package, and mobile phone including the semiconductor package structure |
| JP5214753B2 (en) * | 2011-02-23 | 2013-06-19 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
-
2013
- 2013-08-07 CN CN201310342762.5A patent/CN104347575B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04130756A (en) * | 1990-09-21 | 1992-05-01 | Mitsubishi Electric Corp | Semiconductor device |
| CN101930929A (en) * | 2009-06-26 | 2010-12-29 | 日月光半导体（上海）股份有限公司 | Manufacturing method of packaging base plate provided with side surface lines |
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