CN104347522A - Implementation method based on III-V gallium nitride intelligent power integrated circuit - Google Patents

Implementation method based on III-V gallium nitride intelligent power integrated circuit Download PDF

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Publication number
CN104347522A
CN104347522A CN201310326457.7A CN201310326457A CN104347522A CN 104347522 A CN104347522 A CN 104347522A CN 201310326457 A CN201310326457 A CN 201310326457A CN 104347522 A CN104347522 A CN 104347522A
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CN
China
Prior art keywords
substrate
crystal orientation
semiconductor device
iii
implementation method
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Pending
Application number
CN201310326457.7A
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Chinese (zh)
Inventor
谢刚
陈琛
盛况
崔京京
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Suzhou Industrial Technology Research Institute of ZJU
Industrial Technology Research Institute of ZJU
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Industrial Technology Research Institute of ZJU
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Priority to CN201310326457.7A priority Critical patent/CN104347522A/en
Publication of CN104347522A publication Critical patent/CN104347522A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256

Abstract

The invention discloses an implementation method based on an III-V gallium nitride intelligent power integrated circuit. A semiconductor device of the implementation method is a high electron mobility device made of III-V semiconductor materials, and a certain method and an SOI (Signal Operation Instruction) technique are utilized to realize the purpose of monolithic power integration of a high-voltage resistant GaN semiconductor device based on a <111> crystalline silicon substrate and a low-voltage device based on a <100> crystalline silicon material. The method is applied to mixed type intelligent power integrated circuits based on different materials.

Description

A kind of implementation method based on iii-v gallium nitride smart-power IC
Technical field
The present invention relates to a kind of implementation method based on iii-v gallium nitride smart-power IC, semiconductor device package of the present invention is mainly used in power integrated circuit.
Background technology
Gallium nitride (GaN) semiconductor device of iii-v nitride type device is the novel semiconductor material device developed rapidly in recent years.Device based on GaN semi-conducting material can carry large electric current and support high pressure, and such devices can also provide low-down conduction resistance and very short switching time simultaneously.
Based on the smart-power IC of GaN, namely by high voltage gan device and low pressure Si base device on the one wafer integrated, be a study hotspot of current integrated circuit.
But it is good in GaN semiconductor semiconductor material devices in order to prepare, consider the problems such as the lattice constant match of storeroom, device needs growth prepared by silica-based GaN semi-conducting material is on the substrate in <111> crystal orientation.Equally, consider performance and the cost of controlling and driving circuits, usually silicon-based electronic circuits and device are prepared in the silicon-based substrate based on <100> crystal orientation.
Therefore how by GaN semiconductor device withstand voltage for the height based on <111> crystal orientation silicon materials substrate with to carry out monolithic power based on the low-voltage device of <100> crystal orientation silicon materials integrated, be a current difficult problem.
SOI (Silicon-On-Insulator, the silicon in dielectric substrate) technology be at the bottom of top layer silicon and backing between introduce one deck and bury oxide layer.Utilize SOI technology can reach the integrated gallium nitride power semiconductor device based on <111> crystal orientation silicon substrate and the object based on <100> crystal orientation silicon-based electronic circuits and device by certain method.
Summary of the invention
The present invention proposes a kind of implementation method based on iii-v gallium nitride smart-power IC, is applicable to being applied to the mixed type smart-power IC based on different materials.
The present invention proposes the method for integrated high voltage and low-voltage device, its feature described comprises: reach integrated object by SOI technology.The method of the integrated high voltage that the present invention proposes and low-voltage device, wherein GaN semiconductor material devices contains the structure of 2DEG, achieves the reduction of conducting resistance and conduction loss.And this integrated method comprises following one or more features: the substrate in the <100> crystal orientation 1) introduces one deck and buries oxide layer.2) substrate in the <111> crystal orientation described in introduces one deck and buries oxide layer.3) substrate described in is integrated by burying oxide layer bonding.
Accompanying drawing explanation
Fig. 1 is the cross-section illustration intention that the substrate in <100> crystal orientation introduces that one deck buries oxide layer.
Fig. 2 is the cross-section illustration intention that the substrate in <111> crystal orientation introduces that one deck buries oxide layer.
Fig. 3 is after the substrate adopting a kind of method introducing to be buried the <100> crystal orientation of oxide layer buries the substrate bonding in the <111> crystal orientation of oxide layer with introducing and is intended in the cross-section illustration of the Grown GaN semiconductor material devices epitaxial loayer in <111> crystal orientation.
Fig. 4 makes GaN HEMT semiconductor device and make the generalized section that silicon device reaches integrated object on the substrate in <100> crystal orientation through over etching for the epitaxial loayer after bonding shown in Fig. 3.
Embodiment
Fig. 1 is the cross-section illustration intention that the substrate in <100> crystal orientation introduces that one deck buries oxide layer, describes in detail below in conjunction with Fig. 1.
A kind of substrate of <100> crystal orientation introduces the cross-section illustration intention that one deck buries oxide layer, comprises, the substrate 100 in <100> crystal orientation.Bury oxide layer 101.
Fig. 2 is the cross-section illustration intention that the substrate in <111> crystal orientation introduces that one deck buries oxide layer, describes in detail below in conjunction with Fig. 2.
A kind of substrate of <111> crystal orientation introduces the cross-section illustration intention that one deck buries oxide layer, comprises, the substrate 200 in <111> crystal orientation.Bury oxide layer 201.
Fig. 3 is after the substrate adopting a kind of method introducing to be buried the <100> crystal orientation of oxide layer buries the substrate bonding in the <111> crystal orientation of oxide layer with introducing and is intended in the cross-section illustration of the Grown GaN semiconductor material devices epitaxial loayer in <111> crystal orientation.Describe in detail below in conjunction with Fig. 3.
The cross-section illustration introducing the substrate that buries the <100> crystal orientation of oxide layer integrated with introducing the substrate that buries the <111> crystal orientation of oxide layer is intended to by a kind of method, comprise, the substrate 300 in <100> crystal orientation.The substrate 302 in <111> crystal orientation.Bury oxide layer 301.GaN semiconductor material devices epitaxial loayer 303.
Fig. 4 makes GaN HEMT semiconductor device and make the generalized section that silicon device reaches integrated object on the substrate in <100> crystal orientation through over etching for the epitaxial loayer after bonding shown in Fig. 3.Describe in detail below in conjunction with Fig. 4.
III-V semiconductor material devices and Si device growth are reached on the integrated substrate shown in Fig. 3 the generalized section of integrated object.Comprise, the substrate 400 in <100> crystal orientation.The substrate 402 in <111> crystal orientation.Bury oxide layer 401.GaN semiconductor material devices epitaxial loayer 403.Si material devices 404 and GaN semiconductor material devices 405.
Set forth the present invention by above-mentioned example, other example also can be adopted to realize the present invention, the present invention is not limited to above-mentioned instantiation, and therefore the present invention is limited by claims scope simultaneously.

Claims (4)

1., based on an implementation method for iii-v gallium nitride smart-power IC, it is characterized in that:
Semiconductor device prepared by GaN semi-conducting material is semiconductor material with wide forbidden band device, bears high voltage, can be applicable to high voltage electronics field;
Semiconductor device prepared by Si material, it is lower to bear voltage capability, is mainly used in the Digital Logical Circuits that drives and low-voltage simulation circuit;
Semiconductor device prepared by described GaN semi-conducting material makes based on the substrate epitaxial of <111> crystal orientation;
Semiconductor device prepared by described Si semi-conducting material makes based on the substrate of <100> crystal orientation;
The described material based on <111> crystal orientation substrate and the described material based on <100> crystal orientation substrate integrated by certain method bonding.
2. the semiconductor device structure prepared of GaN semi-conducting material as claimed in claim 1, described semiconductor device substrate comprises the Si base substrate that crystal orientation is any doping of <111>.
3. the semiconductor device structure prepared of Si base semiconductor material as claimed in claim 1, described semiconductor device substrate is the silicon materials in the <100> crystal orientation of doping arbitrarily.
4. the substrate in <111> crystal orientation as claimed in claim 1 and the substrate in described <100> crystal orientation utilize SOI technology to reach the integrated object of bonding by certain method.
CN201310326457.7A 2013-07-31 2013-07-31 Implementation method based on III-V gallium nitride intelligent power integrated circuit Pending CN104347522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310326457.7A CN104347522A (en) 2013-07-31 2013-07-31 Implementation method based on III-V gallium nitride intelligent power integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310326457.7A CN104347522A (en) 2013-07-31 2013-07-31 Implementation method based on III-V gallium nitride intelligent power integrated circuit

Publications (1)

Publication Number Publication Date
CN104347522A true CN104347522A (en) 2015-02-11

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Country Status (1)

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CN (1) CN104347522A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1971943A (en) * 2006-12-07 2007-05-30 西安电子科技大学 Self-supporting SiC based GaN apparatus and its manufacturing method
US20080296617A1 (en) * 2007-05-01 2008-12-04 The Regents Of The University Of California METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS
CN102751296A (en) * 2012-07-24 2012-10-24 矽光光电科技（上海）有限公司 Single-substrate device integrating integrated circuits, luminescent elements and sensing elements
CN103022139A (en) * 2012-12-28 2013-04-03 上海集成电路研发中心有限公司 Semiconductor structure with insulating buried layer and manufacturing method thereof
WO2013088226A1 (en) * 2011-12-13 2013-06-20 Soitec Process for stabilizing a bonding interface, located within a structure which comprises an oxide layer and structure obtained

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1971943A (en) * 2006-12-07 2007-05-30 西安电子科技大学 Self-supporting SiC based GaN apparatus and its manufacturing method
US20080296617A1 (en) * 2007-05-01 2008-12-04 The Regents Of The University Of California METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS
WO2013088226A1 (en) * 2011-12-13 2013-06-20 Soitec Process for stabilizing a bonding interface, located within a structure which comprises an oxide layer and structure obtained
CN102751296A (en) * 2012-07-24 2012-10-24 矽光光电科技（上海）有限公司 Single-substrate device integrating integrated circuits, luminescent elements and sensing elements
CN103022139A (en) * 2012-12-28 2013-04-03 上海集成电路研发中心有限公司 Semiconductor structure with insulating buried layer and manufacturing method thereof

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