CN104347484A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
CN104347484A
CN104347484A CN201310335597.0A CN201310335597A CN104347484A CN 104347484 A CN104347484 A CN 104347484A CN 201310335597 A CN201310335597 A CN 201310335597A CN 104347484 A CN104347484 A CN 104347484A
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contact hole
semiconductor substrate
ion implantation
layer
implanted region
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CN104347484B (en
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陈金明
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a method for manufacturing a semiconductor device. The method includes the following steps: providing a semiconductor substrate; forming an inter-layer dielectric layer on the semiconductor substrate; patterning the inter-layer dielectric layer so as to expose contact holes of the semiconductor substrate; executing an ion implantation process so as to form ion implantation areas at the bottoms of the contact holes; and forming metal silicide layers on the surfaces of the ion implantation areas exposed at the bottoms of the contact holes. The invention proposes a novel manufacturing method of contact holes and between the step of forming the contact holes and the step of forming the silicide layers, the step of forming the ion implantation areas at the bottoms of the contact holes is added, equivalently, the ion implantation areas are formed in the formed contact holes and next, the silicide layers are formed on the ion implantation surfaces at the bottoms of the contact holes after the ion implantation areas are formed so as to prevent a breakdown voltage of the silicide layers and reduce the specific resistance of a device; and the whole technology process is completely compatible with the prior art so that the process is simpler and the process cost is reduced.

Description

A kind of method of semiconductor device and making semiconductor device
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method making semiconductor device.
Background technology
At present, in the manufacturing process of semiconductor device, the passage that connecting hole interconnects as multiple layer metal interlayer and is connected between device active region with external circuitry, has important effect in device architecture composition.Connecting hole is divided into contact hole (contact) and through hole.Metal silicide layer on contact hole and active area of semiconductor device is electrically connected.
Along with the development of semiconductor technology, the critical size of semiconductor device constantly reduces, and the problem such as how to obtain the less contact hole of size, how to make contact hole and active area accurately aim at becomes the problem that people are concerned about gradually.In the fabrication of semiconductor device of prior art, often occur the out-of-alignment phenomenon of contact hole and active area, this phenomenon will increase the resistance of contact hole.Lithography operations has reached its limit controlled for misalignment.The misalignment issues of photoetching is especially crucial for the contact hole on active area.Often there is the skew on position between the contact hole of the method formation of prior art and active area, be difficult to real aligning.
In order to solve the skew between contact hole and active area on position, current employing silicide can solve the misalignment issues between contact hole and active area in rear (silicide last) technique.Figure 1A is the schematic top plan view of the semiconductor device with contact hole, and semiconductor device 100 includes source region 101, grid 102 and contact hole 103.Silicide is adopted to solve the out-of-alignment problem of contact hole 103 in rear technique.
Silicide is adopted to solve the misalignment issues between contact hole and active area in rear technique, concrete processing step is, in step 201, Semiconductor substrate has active area and source-drain area, source-drain area can be made up of semi-conducting material, source-drain area is arranged in described gate stack structure both sides and embeds Semiconductor substrate, and described gate stack structure comprises the gate dielectric layer be formed in Semiconductor substrate, form grid on gate dielectric layer and the side wall around gate dielectric layer and grid.In step 202., form interlayer dielectric layer on a semiconductor substrate, interlayer dielectric layer is formed the figuratum photoresist layer of tool, for the size of the position and contact hole that define contact hole.In step 203, according to the photoresist layer etching interlayer dielectric layer of patterning, to form the contact hole be connected on source-drain area in interlayer dielectric layer.In step 204, after formation contact hole, form silicide layer in the bottom of contact hole, make contact hole be connected to source-drain area via silicide layer.In step 205, form silicide layer in the contact hole that etching is formed after, perform rapid thermal annealing (RTA) technique, remove unreacted material.In step 206, fill contact hole, concrete, depositing metal layers in the contact hole formed, adopt cmp to remove unnecessary metal level, to expose interlayer dielectric layer, and the metal level in contact hole flushes with the top of interlayer dielectric layer.
In order to reduce the resistance in contact hole, can adopt silicide in the contact hole formed, form the technical scheme of silicide layer in rear technique.But, along with the reduction gradually of semiconductor device critical dimension, the critical dimension of contact hole also reduces gradually, create new technological problems, this technological problems is the problem declined in joint face (silicide layer) puncture voltage adopting silicide to cause when rear technique is formed in the process of contact hole, do sectional view along tangent line in Figure 1A (arrow) to make an explanation to brought problem, as shown in Figure 1B, Figure 1B is the schematic cross-section of the semiconductor device corresponding with Figure 1A in cross section.As described in Figure 1B, Semiconductor substrate 100 has fleet plough groove isolation structure, forms oxide skin(coating) 101 in fleet plough groove isolation structure, the contact hole 102 formed in interlayer dielectric layer on a semiconductor substrate, the silicide layer 103 formed in the bottom of contact hole 102.As shown in the figure, the silicide layer 103 of formation has the part of outstanding point, and this part causes the puncture voltage of silicide layer to decline.
Therefore, need a kind of method of making semiconductor device newly, the problem declined with the puncture voltage solving the silicide layer formed caused by contact hole.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method making semiconductor device, comprising the following steps, Semiconductor substrate is provided; Form interlayer dielectric layer on the semiconductor substrate; Interlayer dielectric layer described in patterning exposes the contact hole of described Semiconductor substrate to be formed; Perform ion implantation technology, with the formation ion implanted region, bottom at described contact hole; The surface of the described ion implanted region of exposing in the bottom of described contact hole forms metal silicide layer.
Preferably, the step of rapid thermal anneal process is performed after being also included in the described metal silicide layer of formation.
Preferably, in described contact hole, the step that metal level forms metal plug is filled after being also included in execution rapid thermal anneal process.
Preferably, adopt the unnecessary metal outside chemical mechanical milling tech removing contact hole, flush with the top of described interlayer dielectric layer to make metal level.
Preferably, the degree of depth that described ion implantation technology is injected is greater than the degree of depth intending the described metal silicide layer formed.
Preferably, described Semiconductor substrate is formed with the grid structure of transistor, described contact hole exposes the source-drain area of described transistor.
Preferably, described ion implanted region is arranged in described source-drain area.
Preferably, described transistor is NFET, performs N-type ion implantation technology.
Preferably, described transistor is PFET, performs P type ion implantation technology.
The invention allows for a kind of semiconductor device, comprising: Semiconductor substrate; Be positioned at the interlayer dielectric layer in described Semiconductor substrate; Be arranged in the contact hole of described interlayer dielectric layer; Be positioned at the ion implanted region bottom described contact hole; Be positioned at the metal silicide layer on the surface, described ion implanted region, bottom of described contact hole.
Preferably, described Semiconductor substrate is formed with the grid structure of transistor, described in described Semiconductor substrate, the both sides of grid structure are formed with the source-drain area of transistor.
Preferably, described contact hole exposes the source-drain area of described transistor.
Preferably, described ion implanted region is arranged in described source-drain area.
Preferably, the degree of depth of described ion implanted region is greater than the degree of depth of the described metal silicide layer of formation.
Preferably, metal level is formed with in described contact hole.
To sum up, the present invention proposes a kind of manufacture method of new contact hole, forming the step adding the formation ion implanted region, bottom at contact hole between the step of contact hole and the step forming silicide layer, be equivalent to form ion implanted region in the contact hole formed, then, silicide layer is formed on the surface of the bottom ion implantation of contact hole after formation ion implanted region, to avoid the puncture voltage reducing silicide layer, reduce the resistivity of device, and whole technical process and existing technique completely compatible, therefore process is simpler, reduce process costs.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A makes the schematic top plan view with the semiconductor device of contact hole according to prior art;
Figure 1B makes the schematic cross-section with the semiconductor device of contact hole according to prior art;
Fig. 2 makes the process chart with the semiconductor device of contact hole according to prior art;
The cutaway view of device of Fig. 3 A-3F for making the correlation step with the semiconductor device of contact hole according to one embodiment of the present invention and obtaining;
Fig. 4 makes the process chart with the semiconductor device of contact hole according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by in following description, detailed step is proposed, the manufacture method that the present invention proposes a kind of new contact hole to be described, forming contact hole and forming the step increasing between silicide layer step and form ion implanted region, to avoid the puncture voltage reducing silicide layer.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
The present invention, in order to overcome problems of the prior art, proposes a kind of method making semiconductor device.Below in conjunction with accompanying drawing 3A-3F, the specific embodiment of the present invention is described in detail.With reference to Fig. 3 A to Fig. 3 F, the cutaway view of the correlation step of the embodiment according to one aspect of the invention is shown.
As shown in Figure 3A, provide Semiconductor substrate 300, in the substrate 300 of described semiconductor, be formed with trap;
Semiconductor substrate 300 can comprise any semi-conducting material, and this semi-conducting material can include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.
Semiconductor substrate 300 comprises various isolation structure, such as shallow trench isolation.Semiconductor substrate 300 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In addition, Semiconductor substrate can be defined active area.
Trap is formed in described Semiconductor substrate 300, described in an embodiment of the present invention, substrate selects N-type substrate, particularly, the N-type substrate that those skilled in the art select this area conventional, then in described N-type substrate, form P trap, in an embodiment of the present invention, first in described N-type substrate, form P trap window, in described P trap window, carry out ion implantation, then perform annealing steps and advance to form P trap.
As preferably, described Semiconductor substrate 300 is the thickness of Si material layer is 10-100nm, is preferably 30-50nm.
Described Semiconductor substrate 300 is divided into NFET(N type field-effect transistor) region and PFET(P type field-effect transistor) region, described Semiconductor substrate is formed with the grid structure of transistor, this NFET region has the first grid 301N be formed on the channel region of Uniform Doped, and PFET region has the second grid 301P be formed on the channel region of Uniform Doped.First grid 301N comprises gate dielectric and is positioned at the grid 302A on gate dielectric.Second grid 301P comprises gate dielectric and is positioned at the grid 302B on gate dielectric.
In of the present invention one particularly execution mode, described first grid 301N and second grid 301P is polysilicon gate, first the formation method of described polysilicon gate construction for form gate dielectric in Semiconductor substrate 300, as preferably, the material of described gate dielectric is silicon dioxide, and the mode of thermal oxidation can be adopted to be formed.
Be preferably formed polysilicon gate in the present invention, the formation method of polysilicon layer can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH4), and the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
Then patterning is carried out, to form polysilicon gate on a semiconductor substrate, described patterning method is the photoresist layer first forming patterning, with described photoresist layer for polysilicon layer described in mask etch and gate dielectric, described photoresist layer is removed in last ashing, but the patterning method of described polysilicon gate is not limited to above-mentioned example.
The grid gap wall 303A, the 303B that are formed in the both sides of first grid 301N and second grid 301P.The material of grid gap wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine formation, concrete technology is: form the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer on a semiconductor substrate, then adopts engraving method to form clearance wall.As an optimal enforcement mode of the present embodiment, described clearance wall is silica, silicon nitride forms jointly.It should be noted that, clearance wall structure is optional and nonessential, its be mainly used in follow-up carry out etching or ion implantation time grill-protected electrode structure sidewall injury-free.
Then, form interlayer dielectric layer 304 on a semiconductor substrate, interlayer dielectric layer 304 can use such as silica, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can be used in the film etc. fluorocarbon (CF) defining SiCN film.Thermal chemical vapor deposition method, plasma process can be adopted.Then, adopt cmp (CMP) remove unnecessary interlayer dielectric layer, with make grid 302A, 302B, grid gap wall 303A, 303B, interlayer dielectric layer 304 top flush.
As shown in Figure 3 B, interlayer dielectric layer 304 forms bottom antireflective coating and photoresist layer 305, adopt photoetching process after the steps such as exposure imaging, form the photoresist layer 305 of patterning.Photoresist layer 305 is for the opening size of the position and contact hole that define contact hole.
Other substrate materials can comprise the Other substrate materials be selected from the group comprising positive-tone photo glue material, negative photo glue material and mixing Other substrate materials.Usually, mask layer comprises and has thickness from about 2000 to the positive-tone photo glue material of about 5000 dusts or negative photo glue material.
Bottom antireflective coating is coated in the bottom of photoresist to reduce the reflection of bottom light.There are two kinds of coating materials: organic antireflective coating (Organic), in silicon chip surface spin coating, rely on organic layer directly to receive incident ray; Inorganic anti-reflective coating (Inorganic), utilizes plasma reinforced chemical vapour deposition (PECVD) to be formed at silicon chip surface.General material is: TiN or SiN.Worked by specific wavelength phase cancellation, most important parameter has: Refractive Index of Material, film thickness etc.The use of bottom antireflective coating is more extensive.
Etch interlayer dielectric layer 304 to form contact hole 306A, 306B according to the photoresist layer 305 of patterning, contact hole 306A, 306B expose the source-drain area in Semiconductor substrate.Cineration technics is adopted to remove the photoresist layer 305 of bottom antireflective coating and patterning.Described contact hole exposes the source-drain area of described transistor.
In an embodiment of the present invention, with described graphical photoresist layer for mask, passing into CF 4and CHF 3etching condition under, described interlayer dielectric layer 304 is etched, in this step described etching pressure: 50-150mTorr; Power: 300-800W; Time: 5-15s; Wherein gas flow: CF 4, 10-30sccm; CHF 3, 10-30sccm, it should be noted that above-mentioned engraving method is only exemplary, does not limit to and the method, and those skilled in the art can also select other conventional methods.
Then, as shown in Figure 3 C, Semiconductor substrate 300 forms photoresist layer 307 in PFET region, photoresist layer 307 covers grid 302B, grid gap wall 303A in PFET region, contact hole 306B and interlayer dielectric layer 304.
After the described photoresist layer 307 of formation, also be included in the step of the formation ion implanted region, both sides of grid 301N in NFET region further, particularly, ion implanted region is formed in Semiconductor substrate bottom contact hole in NFET region, the ion doping that can carry out N-type by the method for ion implantation or diffusion forms described ion implanted region, the method of preferred employing ion implantation, wherein the degree of depth in the region of N-type ion doping is greater than and follow-uply will forms the degree of depth of silicide layer in this region surface.The semi-conducting material forming described ion implanted region comprises Si, Si 1-xc x, wherein C atomicity percentage can be that the content of 0-2%, C can need flexible according to technique.Cineration technics is adopted to remove photoresist layer 307.In addition, also visible product demand and functionally to consider, separately forms lightly doped drain (LDD) respectively between regions and source/drain and each grid.The degree of depth adopting described ion implantation technology to inject is greater than the degree of depth intending the described silicide layer formed.Described ion implanted region is arranged in described source-drain area.
As shown in Figure 3 D, Semiconductor substrate 300 forms photoresist layer 308 in NFET region, photoresist layer 307 covers grid 301B, grid gap wall 301A in PFET region, contact hole 306A and interlayer dielectric layer 304.
After the described photoresist layer 308 of formation, also be included in the step of the formation ion implanted region, both sides of grid 301P in PFET region further, particularly, ion implanted region is formed in Semiconductor substrate bottom contact hole in PFET region, the ion doping that can carry out N-type by the method for ion implantation or diffusion forms described ion implanted region, the method of preferred employing ion implantation, wherein the degree of depth in the region of P type ion doping is greater than and follow-uply will forms the degree of depth of silicide layer in this region surface.The semi-conducting material forming described ion implanted region comprises Si, Si 1-xge x, wherein Ge atomicity percentage can be that the content of 30%-50%, Ge can need flexible according to technique.Cineration technics is adopted to remove photoresist layer 308.In addition, also visible product demand and functionally to consider, separately forms lightly doped drain (LDD) respectively between regions and source/drain and each grid.The degree of depth adopting described ion implantation technology to inject is greater than the degree of depth intending the described silicide layer formed.Described ion implanted region is arranged in described source-drain area.
As shown in FIGURE 3 E, the surface of the described ion implanted region that the bottom of contact hole 306A, 306B in PFET region and NFET region is exposed forms metal silicide layer 309A, 309B.Concrete, the ion implanted region be equivalent in PFET region and NFET region forms metal silicide layer 309A, 309B on the surface, and the silicide layer energy ditch of formation reduces the resistivity in PFET region and NFET region.Wherein, the degree of depth of the N-type ion implantation performed respectively Semiconductor substrate in PFET region and NFET region and P type ion implantation is greater than the degree of depth of the silicide layer formed in the Semiconductor substrate of injection zone.
Employing silicification technics (silicidation) forms metal silicide layer 309A, 309B's, particularly, at semiconductor substrate surface sputtered metal layer, such as nickel metal layer, then RTA (RTA) technique is carried out, the partial reaction that metal level is contacted with grid and regions and source/drain becomes metal silicide layer, completes silicification technics (silicidation).
The formation of metal silication layer region, first depositing metal layers, it can comprise the material of nickel (nickel), cobalt (cobalt) and platinum (platinum) or its combination.Then heated substrate, cause metal level and the silicon layer generation silicification under it, thus metal silication layer region is formed.Then erodable metal level is used, but the etchant in unlikely attack metal disilicide layer region, so that unreacted metal level is removed.
Described annealing steps is generally under described substrate is placed in the protection of high vacuum or high-purity gas; be heated to certain temperature to heat-treat; nitrogen or inert gas is preferably at high-purity gas of the present invention; the temperature of described thermal anneal step is 800-1200 DEG C; be preferably 1050 DEG C, the described thermal anneal step time is 1-300s.As further preferred, rapid thermal annealing can be selected in the present invention, the one in following several mode can be selected: pulse laser short annealing, the short annealing of the Pulse Electric philosophical works, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light source (as halogen lamp, arc lamp, graphite heating) short annealing etc., but be not limited to examples cited.
As illustrated in Figure 3 F, the sidewall of contact hole 306A, 306B and bottom deposit one deck contact hole blocking layer on silicide layer 309A, 309B, and growing metal, cmp is carried out to formed contact hole blocking layer and metal, expose interlayer dielectric layer 304, metal object only filled in the contact hole and removes unnecessary metal, to make metal level 310A, 310B flush with the top of interlayer dielectric layer 304, finally forming metal plug.Metal layer material is formed by the deposition technique of low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and ald (ALD) or other advanced person.Preferably, metal layer material is tungsten material.In another embodiment, metal layer material can be cobalt (Co), molybdenum (Mo), titanium nitride (TiN) and the electric conducting material containing tungsten or its combination.
With reference to Fig. 4, show the process chart making contact hole according to one embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.Comprise the following steps particularly:
Step 401 provides Semiconductor substrate, and Semiconductor substrate has the first area separated by shallow trench and second area that are formed thereon.First area is N-shaped field-effect transistor region, second area is p-type field-effect transistor region, be formed with source region and trap in the semiconductor substrate, in NFET region and PFET region, be formed with grid, be formed with interlayer dielectric layer in the periphery of Semiconductor substrate and grid;
Step 402 forms the first photoresist layer on interlayer dielectric layer, adopts photoetching process to form the first photoresist layer of patterning;
Step 403 is according to the first photoresist layer etching interlayer dielectric layer of patterning to form contact hole, and contact hole exposes Semiconductor substrate, adopts cineration technics to remove the first photoresist layer;
Step 404 forms the second photoresist layer in PFET region, and the second photoresist layer covers PFET region, exposes NFET region;
Step 405 performs ion implantation in NFET region, in the base semiconductor substrate of contact hole, form ion implanted region, removes the second photoresist layer;
Step 406 forms the 3rd photoresist layer in NFET region, and the second photoresist layer covers NFET region, exposes PFET region;
Step 407 performs ion implantation in PFET region, in the base semiconductor substrate of contact hole, form ion implanted region, removes the 3rd photoresist layer;
Metal silicide layer is formed on the bottom of the contact hole of step 408 respectively in NFET region and PFET region;
Step 409 performs rapid thermal anneal process;
Metal level is filled, to form metal plug in the contact hole of step 410 respectively in NFET region and PFET region.
In addition, beyond the preparation method that the invention provides described semiconductor device, additionally provide a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the interlayer dielectric layer in described Semiconductor substrate;
Be arranged in the contact hole of described interlayer dielectric layer in described Semiconductor substrate;
Be positioned at the ion implanted region bottom described contact hole;
Be positioned at the metal silicide layer on the surface, described ion implanted region, bottom of described contact hole.
As further preferred, described device also comprises:
Described Semiconductor substrate is formed with the grid structure of transistor, described in described Semiconductor substrate, the both sides of grid structure are formed with the source-drain area of transistor.
Described contact hole exposes the source-drain area of described transistor.
Described ion implanted region is arranged in described source-drain area.
The degree of depth of described ion implanted region is greater than the degree of depth of the described metal silicide layer of formation.
Metal level is formed in described contact hole.
To sum up, the present invention proposes a kind of manufacture method of new contact hole, forming the step adding the formation ion implanted region, bottom at contact hole between the step of contact hole and the step forming silicide layer, be equivalent to form ion implanted region in the contact hole formed, then, metal silicide layer is formed on the surface of the bottom implanted region of contact hole after forming ion implantation, to avoid the puncture voltage reducing silicide layer, reduce the resistivity of device, and whole technical process and existing technique completely compatible, therefore process is simpler, reduce process costs.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.

Claims (15)

1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form interlayer dielectric layer on the semiconductor substrate;
Interlayer dielectric layer described in patterning exposes the contact hole of described Semiconductor substrate to be formed;
Perform ion implantation technology, with the formation ion implanted region, bottom at described contact hole;
The surface of the described ion implanted region of exposing in the bottom of described contact hole forms metal silicide layer.
2. the method for claim 1, is characterized in that, is also included in the step performing rapid thermal anneal process after forming described metal silicide layer.
3. method as claimed in claim 2, is characterized in that, is also included in after performing rapid thermal anneal process in described contact hole, fills the step that metal level forms metal plug.
4. method as claimed in claim 3, is characterized in that, adopts the unnecessary metal outside chemical mechanical milling tech removing contact hole, flushes to make metal level with the top of described interlayer dielectric layer.
5. the method for claim 1, is characterized in that, the degree of depth that described ion implantation technology is injected is greater than the degree of depth intending the described metal silicide layer formed.
6. the method for claim 1, is characterized in that, described Semiconductor substrate is formed with the grid structure of transistor, and described contact hole exposes the source-drain area of described transistor.
7. method as claimed in claim 6, it is characterized in that, described ion implanted region is arranged in described source-drain area.
8. method as claimed in claim 6, it is characterized in that, described transistor is NFET, performs N-type ion implantation technology.
9. method as claimed in claim 6, it is characterized in that, described transistor is PFET, performs P type ion implantation technology.
10. a semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the interlayer dielectric layer in described Semiconductor substrate;
Be arranged in the contact hole of described interlayer dielectric layer;
Be positioned at the ion implanted region bottom described contact hole;
Be positioned at the metal silicide layer on the surface, described ion implanted region, bottom of described contact hole.
11. devices as claimed in claim 10, it is characterized in that, described Semiconductor substrate is formed with the grid structure of transistor, described in described Semiconductor substrate, the both sides of grid structure are formed with the source-drain area of transistor.
12. devices as claimed in claim 11, it is characterized in that, described contact hole exposes the source-drain area of described transistor.
13. devices as claimed in claim 11, it is characterized in that, described ion implanted region is arranged in described source-drain area.
14. devices as claimed in claim 10, is characterized in that, the degree of depth of described ion implanted region is greater than the degree of depth of the described metal silicide layer of formation.
15. devices as claimed in claim 10, is characterized in that, be formed with metal level in described contact hole.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213277A (en) * 1986-03-14 1987-09-19 Nec Corp Manufacture of semiconductor device
US20040058548A1 (en) * 2002-09-24 2004-03-25 Yong-Sun Sohn Forming method of contact in semiconductor device and manufacturing method of PMOS device using the same
CN1681089A (en) * 2004-04-06 2005-10-12 尔必达存储器股份有限公司 Semiconductor device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213277A (en) * 1986-03-14 1987-09-19 Nec Corp Manufacture of semiconductor device
US20040058548A1 (en) * 2002-09-24 2004-03-25 Yong-Sun Sohn Forming method of contact in semiconductor device and manufacturing method of PMOS device using the same
CN1681089A (en) * 2004-04-06 2005-10-12 尔必达存储器股份有限公司 Semiconductor device and method of manufacturing the same

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