CN104320655B - Video decoding chip test device and method - Google Patents
Video decoding chip test device and method Download PDFInfo
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- CN104320655B CN104320655B CN201410630839.3A CN201410630839A CN104320655B CN 104320655 B CN104320655 B CN 104320655B CN 201410630839 A CN201410630839 A CN 201410630839A CN 104320655 B CN104320655 B CN 104320655B
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Abstract
The invention provides a kind of video decoding chip test device and method of testing.Described video decoding chip output multi-channel composite video signal.Described test device includes: apparatus for processing of video signals, for processing to obtain single channel video standard signal to multichannel composite video signal；And video signal analysis device, for single channel video standard signal is measured to obtain the parameter index of video signal.Described test device effectively reduces test complexity, improves testing efficiency.
Description
Technical field
The present invention relates to integrated circuit testing field, relate more specifically to video decoding chip test dress
Put and method.
Background technology
Along with semiconductor technology and the progress of production technology, the process performance of coding and decoding video chip exists
Gradually stepping up, image definition is more and more higher.The performance of video class chip is the most progressively by SD
Develop to high definition.
The test of coding and decoding video adhesive integrated circuit, no matter from signal processing complexity, or signal
From the point of view of processing speed, process data volume aspect, all have more than the test of other type integrated circuit
Big complexity.Under the background constantly pursuing transmission speed and channel utilization index, the overwhelming majority regards
Frequently decoding chip has a passage and can transmit the feature of multichannel composite video stream simultaneously.
For the test of video codec class chip, current common method of testing is to utilize dedicated video
Relevant parameter index tested by test instrunment.Main test instrunment has and regards for directly test component
Frequently the logic analyser of signal, and by decoded digital signal again through video coding chip
It is encoded to analogue component, utilizes video analyzer to measure each analogue component of video signal.Main
The test parameter wanted includes that video frequency output amplitude, audio video synchronization amplitude, video signal to noise ratio, differential increase
Benefit, luminance non-linearity etc..
But, multichannel is compound regards being applied to above-mentioned logic analyser or video analyzer to comprise
But difficulty is there is during the video decoding chip of passage of frequency stream.The signal of multichannel composite video stream is multiple
Miscellaneous degree height, data volume is big.If directly multichannel composite video stream being supplied to logic analyser or regarding
Frequency division analyzer, does not the most only result in the high bandwidth requirements of logic analyser or video analyzer, and leads
Cause signal processing complexity to increase.Such as, if logic analyser is pci bus, then may
Test data can not be properly received owing to bandwidth limits.Therefore, in the survey of multichannel composite video stream
Examination must use expensive special logic analyser or video analyzer.
The most effectively reduce the test complexity of single pass high-speed time-division multiplex video flowing, improve and survey
Examination efficiency is in the field tests of video codec class chip, it appears particularly critical.
Summary of the invention
In view of this, the present invention proposes a kind of video decoding chip test device and method.Described
Video decoding chip test device and method be capable of high-speed time-division multiplex composite video stream
Frequency reducing, fractionation, form conversion and test.
According to an aspect of the present invention, it is provided that a kind of video decoding chip test device, described video
Decoding chip output multi-channel composite video signal, described test device includes: video frequency signal processing fills
Put, for processing to obtain single channel video standard signal to multichannel composite video signal；And
Video signal analysis device, for measuring to obtain video signal to single channel video standard signal
Parameter index.
Preferably, described apparatus for processing of video signals includes: control module, for decoding from video
Chip obtains composite mode numbering and video channel interface index, and performs video frequency signal processing
System controls；Frequency reducing module, for generating system according to the multi-channel video signal composite mode recognized
System clock；And passage splits module, use system clock work and multichannel composite video is believed
Number split into single channel video standard signal；Wherein, composite mode numbering is provided to fall by control module
Frequency module, provides video channel interface index to passage fractionation module.
Preferably, described apparatus for processing of video signals also includes data format conversion module, and being used for will
Single channel video standard signal is converted into component video signal, and described control module is to described data form
Modular converter provides configuration control information.
Preferably, video signal analysis device includes selected from logic analyser and video analyzer
Kind.
Preferably, logic analyser includes the computer performing video data analytic function.
Preferably, video analyzer includes: D/A converter module, for being turned by component video signal
Change analog video signal into；And display terminal, for receiving described analog video signal defeated
Publish picture as display.
Preferably, control module includes: primary processor, and the system performing test device controls: dynamic
State memorizer, as the internal storage location of primary processor work；Nonvolatile memory, preservation system opens
Dynamic code and configuration information；And interface circuit, perform and chip controls interface to be measured, frequency reducing mould
Block, passage split Control on Communication and the relevant configuration function of module.
Preferably, frequency reducing module receives the compound of the time division multiplex composite video stream of control module transmission
Pattern class, and according to composite mode classification, determine the frequency dividing multiple of the internal clocking of device, raw
Become system clock.
According to a further aspect in the invention, it is provided that the method for testing of a kind of video decoding chip, described
Video decoding chip output multi-channel composite video signal, described method of testing includes: be combined multichannel
Video signal carries out processing to obtain single channel video standard signal；And to single channel video standard signal
Measure to obtain the parameter index of video signal.
Preferably, process to obtain single channel video standard signal to multichannel composite video signal
Step includes: obtain composite mode numbering and video channel interface index from video decoding chip；Root
System clock is generated according to composite mode numbering；To be many according to system clock and video channel interface index
Road composite video signal splits into single channel video standard signal.
Preferably, multichannel composite video signal is split into single channel video standard signal step it
After, also include single channel video standard signal is converted into component video signal.
Preferably, the step measured single channel video standard signal includes using and divides selected from logic
A kind of video signal analysis device of analyzer and video analyzer measures.
Preferably, use video analysis view to measure to include: component video signal is converted into mould
Intend video signal；And analog video signal described in receiving export image and show.
Preferably, include according to the step of composite mode numbering generation system clock: according to compound die
Formula classification, determines the frequency dividing multiple of the internal clocking of device；And according to frequency dividing multiple, from multichannel
Composite video signal generates system clock.
Preferably, composite mode classification is the one selected from following pattern: 27Mhz single channel pattern,
54Mhz two-way composite mode, 54Mhz tetra-road Half D1 composite mode, 108Mhz tetra-tunnel is combined
Pattern.
Preferably, system clock is 27MHz.
The video decoding chip test device and method that the present invention proposes is by video decoding chip to be measured
The time division multiplex composite video stream of the reference format of output carries out frequency reducing, splits generation single channel reticle
Formula video flowing, tests at video signal analysis device through form conversion, effectively reduces survey
Examination complexity, improves testing efficiency.
Accompanying drawing explanation
By description to the embodiment of the present invention referring to the drawings, the present invention above-mentioned and other
Objects, features and advantages will be apparent from, in the accompanying drawings:
Fig. 1 is the schematic block diagram of the video decoding chip test device according to embodiments of the invention；
Fig. 2 is the signal of the apparatus for processing of video signals used in video decoding chip test device
Property block diagram；
Fig. 3 is the schematic frame of the video analysis device used in video decoding chip test device
Figure；And
Fig. 4 is the flow chart according to embodiments of the invention video decoding chip method of testing.
Detailed description of the invention
Below based on embodiment, present invention is described, but the present invention is not restricted to these
Embodiment.In below the details of the present invention being described, detailed describe some specific detail portion
Point.The description not having these detail sections for a person skilled in the art can also understand this completely
Invention.In order to avoid obscuring the essence of the present invention, known method, process, flow process, element and
Circuit narration the most in detail.
Additionally, it should be understood by one skilled in the art that accompanying drawing is provided to provided herein
Bright purpose, and accompanying drawing is not necessarily drawn to scale.
Unless the context clearly requires otherwise, otherwise " the including " in entire disclosure and claims,
Implication rather than the exclusive or exhaustive implication that similar word should be construed to comprise such as " comprise "；
It is to say, be the implication of " including but not limited to ".
Fig. 1 is the schematic block diagram of the video decoding chip test device according to embodiments of the invention.
Video decoding chip test device includes apparatus for processing of video signals 100 and video signal analysis device
300。
Apparatus for processing of video signals 100 receives composite video stream from video decoding chip 200 to be measured
(such as 4 tunnel time division multiplex composite video stream), and composite video stream is resolved and is converted into component
Video signal.
Video signal analysis device 300 receives component video signal from apparatus for processing of video signals 100.
Video signal analysis device 300 can be the logic analyser of pci bus, such as, can perform test
Analyze the computer of software.
Alternatively, as it is shown on figure 3, video signal analysis device 300 can include digital-to-analogue conversion mould
Block 301 and display terminal 302.Component video signal is converted into simulation by D/A converter module 301
Signal, then shows image on display terminal 302, such that it is able to the resolution of test video signal
Rate and definition etc..
Fig. 2 is the signal of the apparatus for processing of video signals used in video decoding chip test device
Property block diagram.As in figure 2 it is shown, apparatus for processing of video signals 100 includes: control module 101, fall
Frequency module 103, passage split module 104, data format conversion module 105.
Control module 101 splits module 104, Data Format Transform with frequency reducing module 103, passage
Module 105 is connected, and the system performing apparatus for processing of video signals 100 controls.Control module 101
Including primary processor, nonvolatile memory, interface circuit and dynamic memory four part.Main place
Reason device completes the system of whole device and controls: include identifying chip composite video stream composite mode to be measured
And input channel number, control frequency reducing deconsolidation process device module and according to certain algorithm, data are dropped
The tasks such as fractionation frequently.Nonvolatile memory preserves system start-up code and configuration information, dynamically deposits
The internal storage location that reservoir works as primary processor.Interface circuit complete main controller module respectively with
Chip controls interface to be measured, frequency reducing module, passage split Control on Communication and the relevant configuration merit of module
Energy.
Control module 101 is monitored the signal of video decoding chip 200 to be measured and is controlled the mark that interface exports
The composite mode numbering of quasiconfiguaration time division multiplex composite video stream and video channel interface index.At this
In embodiment, composite mode numbering has four kinds: 00 to represent 27Mhz single channel pattern；01 represents 54Mhz
Two-way composite mode；10 represent 54Mhz tetra-road Half D1 composite mode；11 represent 108Mhz
Four road composite modes.Control module 101 judges to identify by internal hardware circuit and logical algorithm
The composite mode classification of described reference format time division multiplex composite video stream and input channel numbering.
Control module 101 controls frequency reducing module 103, data format conversion module according to composite mode classification
105 pairs of time division multiplex composite video streams carry out the operations such as frequency reducing, fractionation, form conversion.
Frequency reducing module 103 receives reference format time division multiplex from video decoding chip 200 to be measured and is combined
Video flowing.Frequency reducing module 103 receives the time division multiplex composite video stream of control module 101 transmission
Composite mode classification, and according to composite mode classification, determine the frequency dividing multiple of the internal clocking of device,
Generate system clock.Split system clock and reference format time division multiplex are combined by frequency reducing module 103
Video flowing provides to passage fractionation module 104.In the present embodiment, described system clock is 27MHz.
Passage splits module 104 and receives video channel interface index from control module 101, from frequency reducing
Module 103 receives split system clock and reference format time division multiplex composite video stream.According to accordingly
The video flowing belonging to different passage is carried out splitting into single channel reference format and regards by video channel interface index
Frequency stream, and described single channel reference format video flowing is exported data format conversion module 105.
The configuration that data format conversion module 105 sends according to control module 101 controls information, will
Each passage single channel reference format video flowing split is converted into component video signal.In this enforcement
In example, described component video signal is the format component data such as YUV or RGB.
Fig. 4 is the flow chart according to embodiments of the invention video decoding chip method of testing.Such as figure
The method of testing of video decoding chip shown in 4 includes:
In step S1, apparatus for processing of video signals 100 starts, and control module 101 is by interface electricity
The reference format time-division that road monitoring is controlled interface transmission by the signal of video decoding chip 200 to be measured is multiple
Number and video channel interface index with the composite mode of composite video stream；
In step S2, control module 101 being combined according to reference format time division multiplex composite video stream
MODE NUMBER and video channel interface index identification composite mode classification and input channel encode；
In step S3, control module 101 sends composite mode classification and defeated to frequency reducing module 103
Enter channel coding；
In step S4, frequency reducing module 103 receives the reticle of video decoding chip 200 to be measured output
Formula time division multiplex composite video stream also carries out frequency reducing to time division multiplex composite video stream；
In step S5, frequency reducing module 103 according to the composite mode classification of time division multiplex composite video stream,
Determine the frequency dividing multiple of the internal clocking of device, generate system clock, split module 104 for passage
Use；
In step S6, passage splits module 104 and resolves the video channel of time division multiplex composite video stream
Interface index, and according to video channel interface index, channel information is resolved, generate single channel reticle
Formula video flowing also sends it to data format conversion module 105；
In step S7, data format conversion module 105 carries out data to single channel reference format video flowing
Form is changed, and single channel reference format video flowing is converted into component video signal, and by component video
Signal is sent to video signal analysis device, and described video signal analysis device is selected from logical analysis
At least one in instrument and video analyzer；
In step S8, component video signal is analyzed by logic analyser；
In step S9, in video analyzer, component video signal is turned by D/A converter module 301
Change analog video signal into, and be sent to display terminal 302；
In step S10, in video analyzer, video analog signal is carried out at display terminal 302
Image exports.
The video decoding chip test device and method that the present invention proposes is by video decoding chip to be measured
The time division multiplex composite video stream of the reference format of output carries out frequency reducing, splits generation single channel reticle
Formula video flowing, tests at video signal analysis device through form conversion, effectively reduces survey
Examination complexity, improves testing efficiency.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for this
For skilled person, the present invention can have various change and change.All spirit in the present invention
Any modification, equivalent substitution and improvement etc. with being made within principle, should be included in the present invention's
Within protection domain.
Claims (13)
1. a video decoding chip test device, described video decoding chip output multi-channel is compound to be regarded
Frequently signal, described test device includes:
Apparatus for processing of video signals, for processing to obtain single channel to multichannel composite video signal
Video standard signal；And
Video signal analysis device, for measuring to obtain video to single channel video standard signal
The parameter index of signal,
Wherein, described apparatus for processing of video signals includes:
Control module, for obtaining composite mode numbering and video channel interface from video decoding chip
Numbering, and perform the system control of video frequency signal processing；
Frequency reducing module, for determining the interior of device according to the multi-channel video signal composite mode recognized
The frequency dividing multiple of portion's clock, generates system clock；And
Passage splits module, uses system clock work and multichannel composite video signal is split into
Single channel video standard signal；
Wherein, composite mode numbering is provided to frequency reducing module, by video channel interface by control module
Numbering provides to passage fractionation module.
Test device the most according to claim 1, wherein said apparatus for processing of video signals is also
Including data format conversion module, for single channel video standard signal is converted into component video signal,
Described control module provides configuration control information to described data format conversion module.
Test device the most according to claim 1, wherein video signal analysis device includes choosing
From logic analyser and the one of video analyzer.
Test device the most according to claim 3, wherein logic analyser includes performing video
The computer of data analysis function.
Test device the most according to claim 3, wherein video analyzer includes:
D/A converter module, for being converted into analog video signal by component video signal；And
Display terminal, is used for receiving described analog video signal and exporting image showing.
Test device the most according to claim 1, wherein control module includes:
Primary processor, the system performing test device controls:
Dynamic memory, as the internal storage location of primary processor work；
Nonvolatile memory, preserves system start-up code and configuration information；And
Interface circuit, performs to split module with chip controls interface to be measured, frequency reducing module, passage
Control on Communication and relevant configuration function.
Test device the most according to claim 1, wherein frequency reducing module receives control module and sends out
The composite mode classification of the time division multiplex composite video stream sent, and according to composite mode classification, determine
The frequency dividing multiple of the internal clocking of device, generates system clock.
8. a method of testing for video decoding chip, described video decoding chip output multi-channel is combined
Video signal, described method of testing includes:
Process to obtain single channel video standard signal to multichannel composite video signal；And
Single channel video standard signal is measured to obtain the parameter index of video signal,
Wherein, multichannel composite video signal processes to obtain the step of single channel video standard signal
Suddenly include:
Composite mode numbering and video channel interface index is obtained from video decoding chip；
System clock is generated according to composite mode numbering；
According to system clock and video channel interface index, multichannel composite video signal is split into single channel
Video standard signal,
Wherein, include according to the step of composite mode numbering generation system clock:
According to composite mode classification, determine the frequency dividing multiple of the internal clocking of device；And
According to frequency dividing multiple, generate system clock from multichannel composite video signal.
Method of testing the most according to claim 8, is splitting into multichannel composite video signal
After the step of single channel video standard signal, also include single channel video standard signal is converted into component
Video signal.
Method of testing the most according to claim 8, wherein enters single channel video standard signal
The step that row is measured includes using a kind of video signal selected from logic analyser and video analyzer to divide
Analysis apparatus measures.
11. method of testings according to claim 10, wherein use video analysis view to survey
Amount includes:
Component video signal is converted into analog video signal；And
Analog video signal described in reception also exports image and shows.
12. method of testings according to claim 8, wherein composite mode classification for selected from
The one of lower pattern: 27Mhz single channel pattern, 54Mhz two-way composite mode, 54Mhz tetra-road Half
D1 composite mode, 108Mhz tetra-road composite mode.
13. method of testings according to claim 12, wherein system clock is 27MHz.
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| CN105467295A (en) * | 2015-11-23 | 2016-04-06 | 硅谷数模半导体（北京）有限公司 | Test system of electronic chip, method and apparatus thereof |
| CN107592518B (en) * | 2016-07-06 | 2019-04-30 | 深圳市中兴微电子技术有限公司 | A kind of composite video signal quality index determines method and device |
| CN112399173A (en) * | 2020-10-28 | 2021-02-23 | 深圳市天视通技术有限公司 | Channel decoding test method, system and readable storage medium |
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| CN202059521U (en) * | 2011-05-31 | 2011-11-30 | 中国华录·松下电子信息有限公司 | Device for testing video decoding program |
| CN103686314B (en) * | 2012-09-04 | 2017-05-24 | 深圳中兴力维技术有限公司 | Demultiplex device and method adopting HD (high definition) video channel to transmit SD (standard definition) videos |
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