CN104320094B - Pulse signal standing-wave protecting circuit - Google Patents
Pulse signal standing-wave protecting circuit Download PDFInfo
- Publication number
- CN104320094B CN104320094B CN201410454532.2A CN201410454532A CN104320094B CN 104320094 B CN104320094 B CN 104320094B CN 201410454532 A CN201410454532 A CN 201410454532A CN 104320094 B CN104320094 B CN 104320094B
- Authority
- CN
- China
- Prior art keywords
- input
- signal
- comparator
- subtracter
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a kind of pulse signal standing-wave protecting circuit, including：Detection module, for carrying out peak detection respectively to obtain crest voltage to positive radiofrequency signal and reverse radio-frequency signal；Sampling module, for obtaining crest voltage；A/D modular converters, for crest voltage to be converted into numerical signal；And processor, for the rising edge and trailing edge of automatic identification numerical signal, and the virtual value in rising edge and trailing edge interval is processed to obtain vswr protection signal；Detection module, sampling module, A/D modular converters and processor are sequentially connected and connect.The present invention realizes forward and reverse voltage signal acquisition using peak detector and sample circuit, can adapt to any duty cycle pulse signal or narrow pulse signal, and energy quick detection goes out the crest voltage of pulse.Also, logical operation is carried out inside processor, it is to avoid the interference of radiofrequency signal, to ensure that detection is accurate, working stability.
Description
Technical field
The present invention relates to a kind of pulse signal standing-wave protecting circuit.
Background technology
Traditional standing-wave protecting circuit is mainly entered by " forward and reverse detection+voltage amplification with time delay+positive and negative voltage ratio compared with "
Moving standing wave is protected, and after the ratio of backward voltage and forward voltage exceedes certain value, starts vswr protection, the shortcomings of doing so
It is：1st, the delay circuit of traditional detection module can cause to be not suitable with the pulse signal of pulse signal or variable duty cycle；2nd, tradition inspection
The rise and fall of ripple module are not suitable with burst pulse along relatively slow；3rd, analog signal is easily disturbed by radiofrequency signal.
The content of the invention
It is an object of the invention to provide a kind of pulse signal standing-wave protecting circuit, any duty cycle pulse signal is can adapt to
Or narrow pulse signal, and energy quick detection goes out the crest voltage of pulse.Also, logical operation is carried out inside processor, it is to avoid
The interference of radiofrequency signal, to ensure that detection is accurate, working stability.
In order to solve the above technical problems, the present invention provides a kind of pulse signal standing-wave protecting circuit, including：
Detection module, for carrying out peak detection respectively to positive radiofrequency signal and reverse radio-frequency signal to obtain peak value electricity
Pressure；
Sampling module, for obtaining crest voltage；
A/D modular converters, for crest voltage to be converted into numerical signal；And
Processor, for the rising edge and trailing edge of numerical signal described in automatic identification, and will be in rising edge and trailing edge
Virtual value in interval is added up, the data feeding divider when again will be cumulative at the end of reverse impulse after and by divider
Output result is compared to obtain vswr protection signal with threshold value；
Wherein, A/D modular converters detection module, sampling module, A/D modular converters and processor are sequentially connected and connect.
Further, A/D modular converters detection module includes the first peak detector and the second peak detector；A/D turns
Mold changing block sampling module includes the first sample circuit and the second sample circuit；A/D modular converter A/D modular converters include an A/
D converters and the second A/D converter；
The peak detector of A/D modular converters first, the first sample circuit and the first A/D converter are connected to positive letter in turn
Number between source and A/D module processing devices；The peak detector of A/D modular converters second, the second sample circuit and the 2nd A/D turn
Parallel operation is sequentially connected to be stated between reverse signal source and A/D module processing devices；
Further, processor includes：A/D modular converters；It is connected to the first A/D converter and A/D modular converters in turn
Between the first data buffer and rising edge identifying unit, and the first data buffer is also connected with A/D modular converters；With
And it is connected to the second data buffer and trailing edge identifying unit between the second A/D converter and A/D modular converters in turn, and
And second data buffer be also connected with A/D modular converters.
Further, rising edge identifying unit and trailing edge identifying unit include respectively：First shift register, second
Shifting register, triple motion register, the first subtracter, the second subtracter, the 3rd subtracter, first comparator, second are compared
Device, the 3rd comparator and and gate circuit.
Positive input terminal of the input of triple motion register respectively with the 3rd subtracter is connected；Triple motion register
The positive input of output end input, the negative input end of the 3rd subtracter and the second subtracter respectively with second displacement register
End connection；The output end of second displacement register input, the negative input of the second subtracter respectively with the first shift register
The positive input terminal connection of end and the first subtracter；The output end of the first shift register respectively with the negative input of the first subtracter
End and the connection of vswr protection generation unit；The clock of the first shift register, second displacement register and triple motion register
Input receives synchronous clock pulse signal；The output end of the 3rd subtracter is connected to the positive input terminal of the 3rd comparator；The
The output end of two subtracters is connected with the positive input terminal of the second comparator；The output end of the first subtracter is with first comparator just
Input is connected；The output end of the output end of first comparator, the output end of the second comparator and the 3rd comparator is connected to
With the input of gate circuit；The negative input end of the 3rd comparator, the negative input end of the second comparator and first comparator it is negative defeated
Enter end and receive default step values.
Further, A/D modular converters include first selector, second selector, the first accumulator, the second accumulator,
Data switch, divider and the 4th comparator；The first input end of first selector and rising edge identifying unit and gate circuit
Connection, the second input of first selector is connected with the output end of the first data buffer, the 3rd input of first selector
End ground connection, the output end of first selector is connected with the first input end of the first accumulator；The output end difference of the first accumulator
First input end with its second input and data switch is connected；The first input end of second selector judges single with trailing edge
Unit is connected with gate circuit, and the second input of second selector is connected with the output end of the second data buffer, the second selection
3rd input end grounding of device, the output end of second selector is connected with the first input end of the second accumulator；Second accumulator
Second input of the output end respectively with its second input and data switch be connected；First accumulator and the second accumulator
Clock signal input terminal receives synchronous clock pulse signal；The of 3rd input of data switch and trailing edge identifying unit
The output end connection of one shift register；Two output ends of data switch are connected with two inputs of divider respectively；Remove
The output end of musical instruments used in a Buddhist or Taoist mass is connected with the negative input end of the 4th comparator, and the positive input terminal of the 4th comparator receives threshold value.
Further, the first A/D converter and the second A/D converter are high-speed a/d converter.
A kind of method of pulse signal vswr protection, comprises the following steps：
S1, coupled positive radiofrequency signal and reverse radio-frequency signal are carried out respectively detection, sampling with obtain peak value electricity
Pressure；
S2, above-mentioned peak signal is converted into numerical signal；
S3, rising edge and trailing edge are carried out to above-mentioned numerical signal judge interval to obtain the virtual value of pulse signal；And
Virtual value in rising edge and trailing edge interval is added up, data feeding after will be added up at the end of reverse impulse is removed
The output result of divider and threshold value simultaneously are compared to obtain vswr protection signal by musical instruments used in a Buddhist or Taoist mass.
Beneficial effects of the present invention are：The present invention realizes forward and reverse voltage signal acquisition using wave detector and sampling module,
Any duty cycle pulse signal or narrow pulse signal are can adapt to, and energy quick detection goes out the crest voltage of pulse.Also, at place
Logical operation is carried out inside reason device, it is to avoid the interference of radiofrequency signal, to ensure that detection is accurate, working stability.
Brief description of the drawings
Fig. 1 is the overall theory diagram of preferred embodiment；
Fig. 2 is the rising edge identifying unit of preferred embodiment and the circuit theory diagrams of trailing edge identifying unit；
Fig. 3 produces the circuit theory diagrams of circuit for the vswr protection of preferred embodiment.
Specific embodiment
Specific embodiment of the invention is described below, this hair is understood in order to those skilled in the art
It is bright, it should be apparent that the invention is not restricted to the scope of specific embodiment, for those skilled in the art,
As long as in appended claim restriction and the spirit and scope of the present invention for determining, these changes are aobvious and easy to various change
See, all are using the innovation and creation of present inventive concept in the row of protection.
Specific embodiment of the invention is described below, this hair is understood in order to those skilled in the art
It is bright, it should be apparent that the invention is not restricted to the scope of specific embodiment, for those skilled in the art,
As long as in appended claim restriction and the spirit and scope of the present invention for determining, these changes are aobvious and easy to various change
See, all are using the innovation and creation of present inventive concept in the row of protection.
A kind of pulse signal standing-wave protecting circuit as shown in Figure 1, including：Detection module, for positive radiofrequency signal
Peak detection is carried out respectively with reverse radio-frequency signal to obtain crest voltage；Sampling module, for obtaining crest voltage；A/D turns
Mold changing block, for crest voltage to be converted into numerical signal；And processor, for the rising of numerical signal described in automatic identification
Edge and trailing edge, and the virtual value in rising edge and trailing edge interval is added up, again will be tired at the end of reverse impulse
Plus after data feeding divider and the output result of divider and threshold value are compared to obtain vswr protection signal.Its
In, above-mentioned A/D modular converters detection module, sampling module, A/D modular converters and processor are sequentially connected and connect.
Additionally, A/D modular converters detection module includes the first peak detector and the second peak detector；A/D moduluss of conversion
Block sampling module includes the first sample circuit and the second sample circuit；A/D modular converter A/D modular converters turn including an A/D
Parallel operation and the second A/D converter；
The peak detector of A/D modular converters first, the first sample circuit and the first A/D converter are connected to positive letter in turn
Number between source and A/D module processing devices；The peak detector of A/D modular converters second, the second sample circuit and the 2nd A/D turn
Parallel operation is sequentially connected to be stated between reverse signal source and A/D module processing devices；
Processor includes：Vswr protection produces circuit；It is connected in turn between the first A/D converter and A/D modular converters
The first data buffer and rising edge identifying unit, and the first data buffer is also connected with A/D modular converters；And according to
Secondary the second data buffer and trailing edge identifying unit being connected between the second A/D converter and A/D modular converters, and the
Two data buffers are also connected with A/D modular converters.
Rising edge identifying unit and trailing edge identifying unit in processor is according to above-mentioned numerical signal automatic identification pulse
The rising edge and trailing edge of voltage, and output control signal.A/D modular converters unit enters to positive and reverse impulse valid data
Row is cumulative, is compared with threshold value by data feeding divider at the end of reverse impulse and by result, when the threshold more than setting
Vswr protection signal is exported during value and is kept.
Rising edge identifying unit and trailing edge identifying unit as shown in Figure 2 includes respectively：First shift register, second
Shift register, triple motion register, the first subtracter, the second subtracter, the 3rd subtracter, first comparator, the second ratio
Compared with device, the 3rd comparator and and gate circuit.
Positive input terminal of the input of triple motion register respectively with the 3rd subtracter is connected；Triple motion register
The positive input of output end input, the negative input end of the 3rd subtracter and the second subtracter respectively with second displacement register
End connection；The output end of second displacement register input, the negative input of the second subtracter respectively with the first shift register
The positive input terminal connection of end and the first subtracter；The output end of the first shift register respectively with the negative input of the first subtracter
End and the connection of vswr protection generation unit；The clock of the first shift register, second displacement register and triple motion register
Input receives synchronous clock pulse signal；The output end of the 3rd subtracter is connected to the positive input terminal of the 3rd comparator；The
The output end of two subtracters is connected with the positive input terminal of the second comparator；The output end of the first subtracter is with first comparator just
Input is connected；The output end of the output end of first comparator, the output end of the second comparator and the 3rd comparator is connected to
With the input of gate circuit；The negative input end of the 3rd comparator, the negative input end of the second comparator and first comparator it is negative defeated
Enter end and receive default step values.
Rising edge decision circuit and trailing edge decision circuit are synchronizing sequential circuit, the 3rd of rising edge identifying unit
Move register input be connected with the first data buffer, the input of the triple motion register of trailing edge identifying unit and
Second data buffer is connected.First shift register, second displacement register and triple motion register are used to keep nearest 3
The data at preceding once moment and later moment in time data, in synchronised clock rising edge, are carried out subtraction by the data at individual moment
And be compared with default step values, only when rising edge is detected, rising edge decision circuit output high level, when detecting
During flatness of wave, rising edge decision circuit output low level.Judge direct impulse effectively using high to Low change and draw just
To pulse useful signal.Similarly, trailing edge judges that electricity judges reverse impulse effectively and draws anti-also with high to Low change
To pulse useful signal.
Wherein, step values are preset by Index Pulse rising edge trailing edge time, the sensitivity and synchronization of peak detector
Clock cycle determines that formula is as follows：
Vswr protection generation circuit as shown in Figure 3 includes first selector, second selector, the first accumulator, second
Accumulator, data switch, divider and the 4th comparator；The first input end of first selector and rising edge identifying unit with
Gate circuit is connected, and the second input of first selector is connected with the output end of the first data buffer, and the of first selector
Three input end groundings, the output end of first selector is connected with the first input end of the first accumulator；The output of the first accumulator
The first input end respectively with its second input and data switch is held to be connected；The first input end and trailing edge of second selector
Identifying unit is connected with gate circuit, and the second input of second selector is connected with the output end of the second data buffer, and
3rd input end grounding of two selectors, the output end of second selector is connected with the first input end of the second accumulator；Second
Second input of the output end of accumulator respectively with its second input and data switch is connected；First accumulator and second tires out
Plus the clock signal input terminal of device receives synchronous clock pulse signal；3rd input of data switch judges single with trailing edge
The output end connection of the first shift register of unit；Two output ends of data switch connect with two inputs of divider respectively
Connect；The output end of divider is connected with the negative input end of the 4th comparator, and the positive input terminal of the 4th comparator receives threshold value.
The adder of A/D modular converters will be in direct impulse useful signal and reverse impulse useful signal valid value range
Positive numerical signal and reverse numerical signal added up respectively.At the end of reverse radio-frequency signal, by positive numerical signal
Accumulated value with reverse numerical signal is divided by, and finally enters and is compared compared with device than the 4th.When positive numerical signal and reverse number
When the result that the accumulated value of value signal is divided by is more than threshold value, then the 4th comparator will export vswr protection signal.
A kind of method of pulse signal vswr protection, comprises the following steps：
S1, coupled positive radiofrequency signal and reverse radio-frequency signal are carried out respectively detection, sampling with obtain peak value electricity
Pressure.
S2, the peak signal is converted into numerical signal.
S3, rising edge and trailing edge are carried out to the numerical signal judge interval to obtain the virtual value of pulse signal；And
Virtual value in rising edge and trailing edge interval is added up, data feeding after will be added up at the end of reverse impulse is removed
The output result of divider and threshold value simultaneously are compared to obtain vswr protection signal by musical instruments used in a Buddhist or Taoist mass.
The course of work of the invention is as follows：Coupled positive radiofrequency signal and reverse radio-frequency signal are examined by peak value respectively
, to obtain peak forward voltage and negative peak voltage, positive negative sense crest voltage is again via A/D converter for ripple device and sample circuit
Positive numerical signal and reverse numerical signal are converted into respectively；Positive numerical signal and reverse numerical signal respectively enter rising
Along identifying unit and trailing edge identifying unit obtaining direct impulse useful signal and reverse impulse useful signal, A/D moduluss of conversion
Block enters the positive numerical signal and reverse numerical signal in direct impulse useful signal and reverse impulse effective signal area
It is divided by after row is cumulative, and the result after being divided by is compared with threshold value.It is cumulative when positive numerical signal and reverse numerical signal
When the result that value is divided by is more than threshold value, then the 4th comparator is output vswr protection signal.
Claims (3)
1. a kind of pulse signal standing-wave protecting circuit, it is characterised in that including：
Detection module, for carrying out peak detection respectively to obtain crest voltage to positive radiofrequency signal and reverse radio-frequency signal；
Sampling module, for obtaining the crest voltage；
A/D modular converters, for the crest voltage to be converted into numerical signal；And
Processor, for the rising edge and trailing edge of numerical signal described in automatic identification, and will be interval in rising edge and trailing edge
Interior virtual value is added up, the data feeding divider when again will be cumulative at the end of reverse impulse after and by the divider
Output result is compared to obtain vswr protection signal with threshold value；
The detection module, sampling module, A/D modular converters and processor are sequentially connected and connect；
The detection module includes the first peak detector and the second peak detector；The sampling module includes the first sampling electricity
Road and the second sample circuit；The A/D modular converters include the first A/D converter and the second A/D converter；
First peak detector, the first sample circuit and the first A/D converter be connected in turn forward signal source with it is described
Between processor；Second peak detector, the second sample circuit and the second A/D converter are connected to reverse signal source in turn
Between the processor；
The processor includes：
Vswr protection produces circuit；
It is connected to first A/D converter and the vswr protection in turn and produces the first data buffer between circuit and upper
Rise along identifying unit, and first data buffer also produces circuit to be connected with the vswr protection；And
Be connected in turn second A/D converter and the vswr protection produce the second data buffer between circuit and under
Drop is along identifying unit, and second data buffer also produces circuit to be connected with the vswr protection；
The rising edge identifying unit and trailing edge identifying unit include respectively：First shift register, second displacement register,
Triple motion register, the first subtracter, the second subtracter, the 3rd subtracter, first comparator, the second comparator, the 3rd ratio
Compared with device and and gate circuit；
The input of the triple motion register is connected with the positive input terminal of the 3rd subtracter；The triple motion register
The positive input of output end input, the negative input end of the 3rd subtracter and the second subtracter respectively with second displacement register
End connection；The output end of second displacement register input respectively with the first shift register, the second subtracter it is negative
The positive input terminal connection of input and the first subtracter；The output end of first shift register respectively with the first subtracter
Negative input end and vswr protection generation unit connection；First shift register, second displacement register and triple motion
The input end of clock of register receives synchronous clock pulse signal；
The output end of the 3rd subtracter is connected to the positive input terminal of the 3rd comparator；The output of second subtracter
End is connected with the positive input terminal of the second comparator；The output end of first subtracter connects with the positive input terminal of first comparator
Connect；The output end of the output end of the first comparator, the output end of the second comparator and the 3rd comparator is connected to described
With the input of gate circuit；
The negative input end of the 3rd comparator, the negative input end of the second comparator and the negative input end of first comparator are received
Default step values.
2. standing-wave protecting circuit according to claim 1, it is characterised in that the vswr protection produces the circuit to include first
Selector, second selector, the first accumulator, the second accumulator, data switch, divider and the 4th comparator；
The first input end of the first selector is connected with the rising edge identifying unit with gate circuit, the first choice
Second input of device is connected with the output end of first data buffer, the 3rd input termination of the first selector
Ground, the output end of the first selector is connected with the first input end of first accumulator；First accumulator it is defeated
Go out first input end of the end respectively with its second input and the data switch to be connected；
The first input end of the second selector is connected with the trailing edge identifying unit with gate circuit, second selection
Second input of device is connected with the output end of second data buffer, the 3rd input termination of the second selector
Ground, the output end of the second selector is connected with the first input end of second accumulator；Second accumulator it is defeated
Go out second input of the end respectively with its second input and the data switch to be connected；First accumulator and second adds up
The clock signal input terminal of device receives synchronous clock pulse signal；
3rd input of the data switch is connected with the output end of the first shift register of the trailing edge identifying unit；
Two output ends of the data switch are connected with two inputs of the divider respectively；The output end of the divider with
The negative input end connection of the 4th comparator, the positive input terminal of the 4th comparator receives threshold value.
3. standing-wave protecting circuit according to claim 1, it is characterised in that first A/D converter and the 2nd A/D turn
Parallel operation is high-speed a/d converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410454532.2A CN104320094B (en) | 2014-09-09 | 2014-09-09 | Pulse signal standing-wave protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410454532.2A CN104320094B (en) | 2014-09-09 | 2014-09-09 | Pulse signal standing-wave protecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104320094A CN104320094A (en) | 2015-01-28 |
| CN104320094B true CN104320094B (en) | 2017-06-16 |
Family
ID=52375291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410454532.2A Active CN104320094B (en) | 2014-09-09 | 2014-09-09 | Pulse signal standing-wave protecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104320094B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108398590B (en) * | 2017-07-07 | 2024-10-15 | 佛山大学 | Digital output voltage peak value detection method |
| CN112084731B (en) * | 2020-08-04 | 2024-03-29 | 中电科思仪科技股份有限公司 | FPGA digital circuit and method for improving peak power measurement trigger dynamic range |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134670C (en) * | 2000-03-30 | 2004-01-14 | 华为技术有限公司 | Method and device for measuring standing-wave ratio |
| CN101614764A (en) * | 2008-06-27 | 2009-12-30 | 上海亿盟电气自动化技术有限公司 | Improve the method for sampling effective value precision in a kind of AC signal sampling |
| CN203747758U (en) * | 2014-03-21 | 2014-07-30 | 成都市金天之微波技术有限公司 | Power amplifier standing wave protection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011250088A (en) * | 2010-05-26 | 2011-12-08 | Yokogawa Electric Corp | Signal generator protection circuit |
-
2014
- 2014-09-09 CN CN201410454532.2A patent/CN104320094B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134670C (en) * | 2000-03-30 | 2004-01-14 | 华为技术有限公司 | Method and device for measuring standing-wave ratio |
| CN101614764A (en) * | 2008-06-27 | 2009-12-30 | 上海亿盟电气自动化技术有限公司 | Improve the method for sampling effective value precision in a kind of AC signal sampling |
| CN203747758U (en) * | 2014-03-21 | 2014-07-30 | 成都市金天之微波技术有限公司 | Power amplifier standing wave protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104320094A (en) | 2015-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104502684B (en) | A kind of totally digitilized peak value due in discrimination method | |
| CN105044420B (en) | A kind of waveform searching method of digital oscilloscope | |
| CN105486934B (en) | A kind of method and system of the impulse waveform leading edge detection based on straight line fitting | |
| CN106353788B (en) | Analog-digital hybrid formula pulse-height analyzer and its analysis method | |
| CN104320094B (en) | Pulse signal standing-wave protecting circuit | |
| CN106383338A (en) | Multichannel radar signal acquisition device based on digital channelization | |
| CN108761557A (en) | A kind of chiasma type light curtain detection device based on FPGA | |
| CN105245203A (en) | System and method for duty ratio detection employing high precision and low speed clock | |
| CN105116318A (en) | Method for realizing burr detection in logic analyzer | |
| CN105136317A (en) | Single-point sampling decision single-photon detector and sampling decision method thereof | |
| CN204360377U (en) | Veneer multi-channel wide band signal synchronous | |
| CN214756366U (en) | Time acquisition device for quantum communication system | |
| CN208013732U (en) | A kind of Acquisition Circuit of 220V alternating-current switch amount signal | |
| CN102175918B (en) | Universal digital geophone implementation method and device | |
| CN103631161A (en) | Filtering method based on state machine | |
| CN108647661A (en) | A kind of extracting method of complete cycle waveform | |
| CN104202097A (en) | High-speed scan method used for digital monitoring receiver | |
| CN203672782U (en) | Spectral data acquisition system based on singlechip control | |
| CN101561489A (en) | Chip design method adopting multi-path parallel code phase search of satellite signals | |
| CN206147079U (en) | Great dynamic range's magnetic field measurement system | |
| CN113406453B (en) | PRPD/PRPS map data processing method and detection device based on MCU | |
| CN103528695B (en) | Sampling single-photon detector and adaptive differential decision method thereof | |
| CN202033640U (en) | Multi-phase electric energy parameter synchronizing acquisition circuit | |
| CN104111083B (en) | The process circuit of Position-Sensitive Detector output signal and processing method | |
| CN103323032B (en) | Step signal detection method for filtering of double sliding windows with dead zone unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C53 | Correction of patent for invention or patent application | ||
| CB02 | Change of applicant information |
Address after: 3, No. 1, building 1, building 35, 610091 west slope Su Road, Chengdu, Sichuan Applicant after: CHENGDU SIWI POWER ELECTRONIC TECHNOLOGY CO., LTD. Address before: 3, No. 1, building 1, building 35, 610091 west slope Su Road, Chengdu, Sichuan Applicant before: Chengdu SIWI Aviatic Power Supply Co., Ltd. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: CHENGDU SIWI AVIATION POWER SUPPLY CO., LTD. TO: CHENGDU SIWI POWER ELECTRONICS TECHNOLOGY CO., LTD. |
|
| GR01 | Patent grant |