CN104319739A - DC surge voltage clamping circuit with reversal connection protection - Google Patents
DC surge voltage clamping circuit with reversal connection protection Download PDFInfo
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- CN104319739A CN104319739A CN201410517323.8A CN201410517323A CN104319739A CN 104319739 A CN104319739 A CN 104319739A CN 201410517323 A CN201410517323 A CN 201410517323A CN 104319739 A CN104319739 A CN 104319739A
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Abstract
The invention discloses a DC surge voltage clamping circuit with reversal connection protection, and a work method. The circuit comprises an input DC source VI, DC output VO, a first voltage stabling tube, a first MOS tube, a second MOS tube and a controller. The controller, through sampling voltage drop of resistors, detects input voltage, input loop current and output voltage and drives the first MOS tube through a fifth resistor and a second capacitor, then the second MOS tube is directly driven through the controller, an ideal diode formed by symmetrically connecting the first MOS tube and the second MOS tube in series is synchronously controlled by the controller to be conducted or cut off, and after filtering through a third capacitor, controlled DC output VO is generated, such that the reversal connection protection, surge voltage clamping, overcurrent protection and post-fault restarting are realized. According to the invention, the DC surge voltage clamping circuit can realize multiple protection functions, including accidental reversal connection protection, input overcurrent protection, input undervoltage protection and input overvoltage surge protection, and also has the functions of low voltage difference, low loss and recoverable faults during normal operation.
Description
Technical field
The present invention relates to a kind of DC power supply art, particularly a kind of direct current surge voltage clamp circuit with reverse connecting protection.
Background technology
The such as DC power supply system of Industry Control, the most equipment of automobile must process the high voltage surge of short time, keep the voltage-regulation in load, avoid sensitive circuit to incur danger the damage of transition simultaneously.
The iron core inductor that conventional protection scheme needs use one to connect and high level electrolysis by-pass capacitor, and be aided with a high power Transient Voltage Suppressor (TVS) and fuse.The method of this clumsiness needs to take a large amount of board area resources, and huge inductor and capacitor are usually assemblies the highest in system.
Even if having employed this type of protection scheme can not provide protective action for reverse input voltage or line under-voltage (these are all the situations likely met with in automotive environment).For avoiding suffering the damage of these situations and keeping the consideration of output voltage, designer has set up an isolating diode usually, but the increase that can cause power loss falls in extra voltage during this diode current flow.
Therefore, design this cover new-type circuit just for complete solution load protection, export the control kept, and there is compact, compact, the advantage of minimum power loss.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of direct current surge voltage clamp circuit with reverse connecting protection; when DC power system non-normal working; clamp is from the surge voltage of input, and protection rear end DC/DC transducer or load, improve the reliability of system.
In order to realize the object solved the problems of the technologies described above, present invention employs following technical scheme:
With a direct current surge voltage clamp circuit for reverse connecting protection, comprise input DC power VI, direct current exports VO, the first voltage-stabiliser tube (5), the first metal-oxide-semiconductor (8), the 5th resistor (9), the second metal-oxide-semiconductor (10), controller (16).
Input DC power VI anode connects one end of the first resistor (1), one end of 4th resistor (4), the drain electrode of the first metal-oxide-semiconductor (8), input DC power VI negative terminal connects output DC power supply VO negative terminal, one end of 3rd resistor (3), the anode of the first voltage-stabiliser tube (5), one end of first capacitor (6), one end of second capacitor (7), one end of 3rd capacitor (12), one end of 8th resistor (14), one end of 4th capacitor (15), 12 pin of controller (16) and 13 pin and 14 pin, the other end of the first resistor (1) connects one end of the second resistor (2), 2 pin of controller (16), the other end of the second resistor (2) connects the other end of the 3rd resistor (3), 1 pin of controller (16), the other end of the 4th resistor (4) connects the negative electrode of the first voltage-stabiliser tube (5), the other end of the first capacitor (6), 3 pin of controller (16) and 4 pin, the grid of the first metal-oxide-semiconductor (8) connects one end of the 5th resistor (9), and the other end of the 5th resistor (9) connects the other end of the second capacitor (7), 5 pin of controller (16), the source electrode of the first metal-oxide-semiconductor (8) connects the source electrode of the second metal-oxide-semiconductor (10), 6 pin of controller (16), 7 pin of the grid connection control device (16) of the second metal-oxide-semiconductor (10), 8 pin of the drain electrode connection control device (16) of the second metal-oxide-semiconductor (10), one end of 6th resistor (11), exports the other end that DC power supply VO anode connects the 6th resistor (11), one end of 7th resistor (13), the positive pole of the 4th capacitor (15), 9 pin of controller (16), 11 pin of the other end connection control device (16) of the 3rd capacitor (12), the other end of the 8th resistor (14) connects the other end of the 7th resistor (13), 10 pin of controller (16).
Concrete, the controller (16) of this patent, its pin definitions is: pin 1 is OV, pin 2 is UV, and pin 3 is SHDN, and pin 4 is VCC, pin 5 is HGATE, and pin 6 is SOURCE, and pin 7 is DGATE, pin 8 is SENSE, and pin 9 is OUT, and pin 10 is FB, pin 11 is TMR, pin 12 is GND, and pin 13 is GND, and pin 14 is GND.
Concrete, the input DC power voltage of this patent can be 12VDC or 28VDC.
Surge current suppression circuit of the present invention, its working method is: when the DC power supply of input starts,
The voltage-dividing detection circuit that controller (16) consists of the first resistor (1), the second resistor (2), the 3rd resistor (3), the 6th resistor (11), the 7th resistor (13), the 8th resistor (14) detects input voltage working condition; input voltage is controlled by protective circuit in normal range (NR), then exports to rear end DC/DC transducer or sensitive loads.
When input terminal voltage is normal, controller (16) controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) normally, and input voltage exports after first metal-oxide-semiconductor (8) of normally, the second metal-oxide-semiconductor (10) and the 6th resistor (11) again.
When input terminal voltage is under-voltage, controller (16) controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off, and constrained input disconnects, and exports and can not instead fill with to input.
When input overvoltage surge, controller (16) is by the dividing potential drop of collection the 7th resistor (13) and the 8th resistor (14), control the first metal-oxide-semiconductor (8) and carry out input voltage clamp, by unnecessary voltage drop on the first metal-oxide-semiconductor (8), convert heat energy to dissipate, and output will be clamped in normal range (NR).
When input circuit overcurrent, the pressure drop that controller (16) is arranged by sampling anode the 6th resistor (11), controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off in time, thus protection rear end DC/DC transducer and load.
When input overvoltage surge and overcurrent occur for a long time, controller (16) can be attempted starting under low-down initiation culture, both can ensure that the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) had enough cooling times and do not damage after being turned off because of fault, and ensure again to reset automatically.
When the reversal connection of input both positive and negative polarity, the negative voltage that controller (16) self can bear-40V does not damage, and controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off, and constrained input disconnects, and could recover normal work after must removing fault.
The effect of each device is as follows in circuit:
The effect of the first resistor (1), the second resistor (2), the 3rd resistor (3) is that dividing potential drop is to controller (16) in proportion by input voltage, and being used for sampling input terminal voltage and internal reference point compares and control; The effect of the 4th resistor (4), the first voltage-stabiliser tube (5), the first capacitor (6) is, allow input current produce stable voltage by the 4th resistor (4) at the first voltage-stabiliser tube (5) and the first capacitor (6) two ends voltage stabilizing, and supply controller (16); The effect of the first metal-oxide-semiconductor (8), the second metal-oxide-semiconductor (10) is composed in series desirable diode; The effect of the second capacitor (7), the 5th resistor (9) carries out voltage stabilizing and current limliting to the gate drive voltage of the first metal-oxide-semiconductor (8); The effect of the 6th resistor (11) is connected on positive end loop generation pressure drop to be supplied to controller (16) as current signal; The effect of the 3rd capacitor (12) is the cycle that setting fault turns off and cooling recovers.The effect of the 7th resistor (13), the 8th resistor (14) is that dividing potential drop is to controller (16) in proportion by output voltage, and being used for feedback output end voltage and internal reference point compares and control; The effect of the 4th capacitor (15) is used to eliminate the circuit resonance inputting overvoltage surge and bring; The effect of controller (16) is used to driving first metal-oxide-semiconductor (8), the second metal-oxide-semiconductor (10) realizes every control.
By adopting technique scheme, the present invention has following superiority:
The present invention is with the surge voltage clamp protection circuits of anti-reverse function to realize multinomial defencive function to the power supply that direct current inputs by adding; prevent unexpected reverse connecting protection; input overcurrent protection; input undervoltage is protected; the protection of input overvoltage surge; there is low voltage difference, low-loss, the recoverable function of fault when normal work.
Accompanying drawing explanation
Fig. 1 is the surge voltage-suppressing circuit schematic diagram being with anti-reverse function.
Fig. 2 is the application principle figure of the surge voltage clamp circuit being with anti-reverse function.
In Fig. 1, VI-direct current inputs, VO-direct current exports, DC power supply VI, direct current exports VO, 1-first resistor (1), 2-second resistor (2), 3-the 3rd resistor (3), 4-the 4th resistor (4), 5-first voltage-stabiliser tube (5), 6-first capacitor (6), 7-second capacitor (7), 8-first metal-oxide-semiconductor (8), 9-the 5th resistor (9), 10-second metal-oxide-semiconductor (10), 11-the 6th resistor (11), 12-the 3rd capacitor (12), 13-the 7th resistor (13), 14-the 8th resistor (14), 15-the 4th capacitor (15), 16-controller (16).
In Fig. 2, the surge voltage clamp circuit of 1-with anti-reverse function, 2-capacitor, 3-DC/DC transducer, 4-capacitor, 5-resistor.
Embodiment
Below in conjunction with accompanying drawing, further explanation is explained to this patent.But the protection range of this patent is not limited to concrete execution mode.
Embodiment 1
As shown in Figure 1, the surge current suppression circuit of this patent, concrete structure is: input DC power VI anode connects one end of the first resistor (1), one end of 4th resistor (4), the drain electrode of the first metal-oxide-semiconductor (8), input DC power VI negative terminal connects output DC power supply VO negative terminal, one end of 3rd resistor (3), the anode of the first voltage-stabiliser tube (5), one end of first capacitor (6), one end of second capacitor (7), one end of 3rd capacitor (12), one end of 8th resistor (14), one end of 4th capacitor (15), 12 pin of controller (16) and 13 pin and 14 pin, the other end of the first resistor (1) connects one end of the second resistor (2), 2 pin of controller (16), the other end of the second resistor (2) connects the other end of the 3rd resistor (3), 1 pin of controller (16), the other end of the 4th resistor (4) connects the negative electrode of the first voltage-stabiliser tube (5), the other end of the first capacitor (6), 3 pin of controller (16) and 4 pin, the grid of the first metal-oxide-semiconductor (8) connects one end of the 5th resistor (9), and the other end of the 5th resistor (9) connects the other end of the second capacitor (7), 5 pin of controller (16), the source electrode of the first metal-oxide-semiconductor (8) connects the source electrode of the second metal-oxide-semiconductor (10), 6 pin of controller (16), 7 pin of the grid connection control device (16) of the second metal-oxide-semiconductor (10), 8 pin of the drain electrode connection control device (16) of the second metal-oxide-semiconductor (10), one end of 6th resistor (11), exports the other end that DC power supply VO anode connects the 6th resistor (11), one end of 7th resistor (13), the positive pole of the 4th capacitor (15), 9 pin of controller (16), 11 pin of the other end connection control device (16) of the 3rd capacitor (12), the other end of the 8th resistor (14) connects the other end of the 7th resistor (13), 10 pin of controller (16).
Controller (16), its pin definitions is: pin 1 is OV, and pin 2 is UV, pin 3 is SHDN, and pin 4 is VCC, and pin 5 is HGATE, pin 6 is SOURCE, and pin 7 is DGATE, and pin 8 is SENSE, pin 9 is OUT, pin 10 is FB, and pin 11 is TMR, and pin 12 is GND, pin 13 is GND, and pin 14 is GND.
Surge current suppression circuit of the present invention; its working method is: when the DC power supply of input starts; the voltage-dividing detection circuit that controller (16) consists of the first resistor (1), the second resistor (2), the 3rd resistor (3), the 6th resistor (11), the 7th resistor (13), the 8th resistor (14) detects input voltage working condition; input voltage is controlled by protective circuit in normal range (NR), then exports to rear end DC/DC transducer or sensitive loads.
When input terminal voltage is normal, controller (16) controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) normally, and input voltage exports after first metal-oxide-semiconductor (8) of normally, the second metal-oxide-semiconductor (10) and the 6th resistor (11) again.
When input terminal voltage is under-voltage, controller (16) controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off, and constrained input disconnects, and exports and can not instead fill with to input.
When input overvoltage surge, controller (16) is by the dividing potential drop of collection the 7th resistor (13) and the 8th resistor (14), control the first metal-oxide-semiconductor (8) and carry out input voltage clamp, by unnecessary voltage drop on the first metal-oxide-semiconductor (8), convert heat energy to dissipate, and output will be clamped in normal range (NR).
When input circuit overcurrent, the pressure drop that controller (16) is arranged by sampling anode the 6th resistor (11), controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off in time, thus protection rear end DC/DC transducer and load.
When input overvoltage surge and overcurrent occur for a long time, controller (16) can be attempted starting under low-down initiation culture, both can ensure that the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) had enough cooling times and do not damage after being turned off because of fault, and ensure again to reset automatically.
When the reversal connection of input both positive and negative polarity, the negative voltage that controller (16) self can bear-40V does not damage, and controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off, and constrained input disconnects, and could recover normal work after must removing fault.
When input DC power VI is normal, electric current produces burning voltage by the 4th resistance at voltage-stabiliser tube and the first capacitor two ends and powers to controller, controller passes through sampling first to the 3rd resistor voltage drop detection input voltage, to sample the 6th resistor voltage drop detection input circuit electric current, to sample the 7th to the 8th resistor voltage drop detection output voltage, by the 5th resistor and the second capacitor drive first metal-oxide-semiconductor, again through controller Direct driver second metal-oxide-semiconductor, the one the second metal-oxide-semiconductor symmetries are composed in series ideal diode, by the conducting of controller Synchronization Control or cut-off, controlled direct current output VO is being produced after the 3rd capacitor filtering, thus realize reverse connecting protection, surge voltage clamper, overcurrent protection, restart after fault.
The present invention is with the surge voltage clamp protection circuits of anti-reverse function to realize multinomial defencive function to the power supply of direct current input by adding; prevent unexpected reverse connecting protection; input overcurrent protection; input undervoltage is protected; the protection of input overvoltage surge; there is low voltage difference, low-loss, the recoverable function of fault when normal work.
Claims (10)
1. be with a surge voltage-suppressing circuit for anti-reverse function, it is characterized in that: comprise input DC power VI, direct current exports VO, the first voltage-stabiliser tube (5), the first metal-oxide-semiconductor (8), the second metal-oxide-semiconductor (10), controller (16);
Input DC power VI anode connects one end of the first resistor (1), one end of 4th resistor (4), the drain electrode of the first metal-oxide-semiconductor (8), input DC power VI negative terminal connects output DC power supply VO negative terminal, one end of 3rd resistor (3), the anode of the first voltage-stabiliser tube (5), one end of first capacitor (6), one end of second capacitor (7), one end of 3rd capacitor (12), one end of 8th resistor (14), one end of 4th capacitor (15), 12 pin of controller (16) and 13 pin and 14 pin, the other end of the first resistor (1) connects one end of the second resistor (2), 2 pin of controller (16), the other end of the second resistor (2) connects the other end of the 3rd resistor (3), 1 pin of controller (16), the other end of the 4th resistor (4) connects the negative electrode of the first voltage-stabiliser tube (5), the other end of the first capacitor (6), 3 pin of controller (16) and 4 pin, the grid of the first metal-oxide-semiconductor (8) connects one end of the 5th resistor (9), and the other end of the 5th resistor (9) connects the other end of the second capacitor (7), 5 pin of controller (16), the source electrode of the first metal-oxide-semiconductor (8) connects the source electrode of the second metal-oxide-semiconductor (10), 6 pin of controller (16), 7 pin of the grid connection control device (16) of the second metal-oxide-semiconductor (10), 8 pin of the drain electrode connection control device (16) of the second metal-oxide-semiconductor (10), one end of 6th resistor (11), exports the other end that DC power supply VO anode connects the 6th resistor (11), one end of 7th resistor (13), the positive pole of the 4th capacitor (15), 9 pin of controller (16), 11 pin of the other end connection control device (16) of the 3rd capacitor (12), the other end of the 8th resistor (14) connects the other end of the 7th resistor (13), 10 pin of controller (16).
2. the surge voltage clamp circuit of the anti-reverse protection of band according to claim 1, is characterized in that: described controller (16), and its pin definitions is: pin 1 is OV; pin 2 is UV, and pin 3 is SHDN, and pin 4 is VCC; pin 5 is HGATE, and pin 6 is SOURCE, and pin 7 is DGATE; pin 8 is SENSE, and pin 9 is OUT, and pin 10 is FB; pin 11 is TMR; pin 12 is GND, and pin 13 is GND, and pin 14 is GND.
3. surge current suppression circuit according to claim 1, is characterized in that: described DC power supply (VI) voltage is 12VDC or 28VDC.
4. the method for work of surge current suppression circuit as claimed in claim 1: it is characterized in that:
One, when the DC power supply of input starts,
The voltage-dividing detection circuit that controller (16) consists of the first resistor (1), the second resistor (2), the 3rd resistor (3), the 6th resistor (11), the 7th resistor (13), the 8th resistor (14) detects input voltage working condition, input voltage is controlled by protective circuit in normal range (NR), then exports to rear end DC/DC transducer or sensitive loads;
1) when input terminal voltage is normal, controller (16) controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) normally, and input voltage exports after first metal-oxide-semiconductor (8) of normally, the second metal-oxide-semiconductor (10) and the 6th resistor (11) again;
2) when input terminal voltage is under-voltage, controller (16) controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off, and constrained input disconnects, and exports and can not instead fill with to input;
3) when input overvoltage surge, controller (16) is by the dividing potential drop of collection the 7th resistor (13) and the 8th resistor (14), control the first metal-oxide-semiconductor (8) and carry out input voltage clamp, by unnecessary voltage drop on the first metal-oxide-semiconductor (8), convert heat energy to dissipate, and output will be clamped in normal range (NR);
4) when input circuit overcurrent, the pressure drop that controller (16) is arranged by sampling anode the 6th resistor (11), controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off in time, thus protection rear end DC/DC transducer and load;
Two, when input overvoltage surge and overcurrent occur for a long time, controller (16) can be attempted starting under low-down initiation culture, both can ensure that the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) had enough cooling times and do not damage after being turned off because of fault, and guarantee again to reset automatically;
When the reversal connection of input both positive and negative polarity, the negative voltage that controller (16) self can bear-40V does not damage, and controls the first metal-oxide-semiconductor (8) and the second metal-oxide-semiconductor (10) cut-off, and constrained input disconnects, and could recover normal work after must removing fault.
5. the working method of surge current suppression circuit as claimed in claim 4: it is characterized in that: the effect of described first resistor (1), the second resistor (2), the 3rd resistor (3) is that dividing potential drop is to controller (16) in proportion by input voltage, and being used for sampling input terminal voltage and internal reference point compares and control.
6. the working method of surge current suppression circuit as claimed in claim 4: it is characterized in that: the effect of described 4th resistor (4), the first voltage-stabiliser tube (5), the first capacitor (6) is, allow input current produce stable voltage by the 4th resistor (4) at the first voltage-stabiliser tube (5) and the first capacitor (6) two ends voltage stabilizing, and supply controller (16); The effect of the first metal-oxide-semiconductor (8), the second metal-oxide-semiconductor (10) is composed in series desirable diode.
7. the working method of surge current suppression circuit as claimed in claim 4: it is characterized in that: the effect of described second capacitor (7), the 5th resistor (9) carries out voltage stabilizing and current limliting to the gate drive voltage of the first metal-oxide-semiconductor (8).
8. the working method of surge current suppression circuit as claimed in claim 4: it is characterized in that: the effect of described 6th resistor (11) is connected on positive end loop to produce pressure drop and be supplied to controller (16) as current signal; The effect of the 3rd capacitor (12) is the cycle that setting fault turns off and cooling recovers.
9. the working method of surge current suppression circuit as claimed in claim 4: it is characterized in that: the effect of described 7th resistor (13), the 8th resistor (14) is that dividing potential drop is to controller (16) in proportion by output voltage, and being used for feedback output end voltage and internal reference point compares and control.
10. the working method of surge current suppression circuit as claimed in claim 4: it is characterized in that: the effect of described 4th capacitor (15) is used to eliminate the circuit resonance that input overvoltage surge brings; The effect of controller (16) is used to driving first metal-oxide-semiconductor (8), the second metal-oxide-semiconductor (10) realizes every control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410517323.8A CN104319739A (en) | 2014-09-30 | 2014-09-30 | DC surge voltage clamping circuit with reversal connection protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410517323.8A CN104319739A (en) | 2014-09-30 | 2014-09-30 | DC surge voltage clamping circuit with reversal connection protection |
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| Publication Number | Publication Date |
|---|---|
| CN104319739A true CN104319739A (en) | 2015-01-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410517323.8A Pending CN104319739A (en) | 2014-09-30 | 2014-09-30 | DC surge voltage clamping circuit with reversal connection protection |
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| Country | Link |
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| CN (1) | CN104319739A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108233351A (en) * | 2018-01-16 | 2018-06-29 | 四川安迪科技实业有限公司 | A kind of Surge suppression protector |
| CN111106599A (en) * | 2020-01-10 | 2020-05-05 | 湖南中普技术股份有限公司 | Method for suppressing direct current surge of airborne electric equipment based on ideal diode |
| CN114336561A (en) * | 2021-11-21 | 2022-04-12 | 西安电子工程研究所 | Direct current surge voltage suppression circuit |
| CN116799920A (en) * | 2023-07-03 | 2023-09-22 | 湖南炬神电子有限公司 | Direct current charging protection circuit |
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| US20040080892A1 (en) * | 2002-10-24 | 2004-04-29 | Vlad Popescu-Stanesti | Battery over voltage and over current protection circuit and adjustable adapter current limit circuit |
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| CN204538667U (en) * | 2014-09-30 | 2015-08-05 | 洛阳隆盛科技有限责任公司 | A kind of direct current surge voltage clamp circuit with reverse connecting protection |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108233351A (en) * | 2018-01-16 | 2018-06-29 | 四川安迪科技实业有限公司 | A kind of Surge suppression protector |
| CN111106599A (en) * | 2020-01-10 | 2020-05-05 | 湖南中普技术股份有限公司 | Method for suppressing direct current surge of airborne electric equipment based on ideal diode |
| CN114336561A (en) * | 2021-11-21 | 2022-04-12 | 西安电子工程研究所 | Direct current surge voltage suppression circuit |
| CN116799920A (en) * | 2023-07-03 | 2023-09-22 | 湖南炬神电子有限公司 | Direct current charging protection circuit |
| CN116799920B (en) * | 2023-07-03 | 2024-01-02 | 湖南炬神电子有限公司 | Direct current charging protection circuit |
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