CN104317577A - Design method for realizing openCV by using ViadoHLS in FPGA (Field Programmable Gate Array) development - Google Patents

Abstract

The invention relates to a design method, in particular to a design method for realizing openCV by using ViadoHLS in FPGA (Field Programmable Gate Array) development. The design method for realizing the openCV by using ViadoHLS in FPGA development comprises the following steps of (1) developing an openCV application on a computer, and then generating an executable file; (2) using a synthesizable VivadoHLSVideo library function code to replace an openCV function for calling; (3) starting co-sim in the VivadoHLS engineering, enabling an HLS tool to automatically reuse openCV test actuation to validate generated RTL codes; performing RTL integration and SoC/FPGA implementation in the Xilinx ISE or Vivado development environment. According to the design method disclosed by the invention, programmable logic is embedded into an ARM kernel, and the design method is a solution for image processing integration with optimized performance and optimized power consumption.

Description

In FPGA exploitation, use ViadoHLS to realize the method for designing of openCV

Technical field

The present invention relates to a kind of method for designing, be specifically related to a kind of FPGA exploitation in use ViadoHLS to realize the method for designing of openCV.

Background technology

The data capsule relevant with image manipulation common in OpenCV has Ma t, CvMa t and IplImage, and this three types can represent and show image, but Mat type side overweights calculating, and mathematics is higher.And CvMat and IplImage type more lays particular emphasis on " image ", OpenCV is optimized image manipulation (extraction of convergent-divergent, single channel, image threshold operation etc.) wherein.

Summary of the invention

The present invention aim to provide a kind of FPGA exploitation in use ViadoHLS to realize the method for designing of openCV.

In FPGA exploitation, use ViadoHLS to realize the method for designing of openCV, comprise the following steps:

Step 1: develop OpenCV application on computers, adopts the compiler of C++ to compile it, emulate and debug, finally produces executable file;

Step 2: the part using I/O functions extract FPGA to realize, uses VivadoHLSVideo built-in function code that can be comprehensive to replace calling of OpenCV function;

Step 3: run HLS and generate RTL code, start co-sim in VivadoHLS engineering, the RTL code that the test and excitation checking that OpenCV reused automatically by HLS instrument produces; The integrated of RTL and SoC/FPGA realization is done in ISE or the Vivado development environment of Xilinx.

The present invention, by FPGA (Field Programmable Gate Array) embedded-type ARM kernel, is the image procossing integrated form solution of a performance optimised power consumption.

Embodiment

The present invention is a kind of uses ViadoHLS to realize the method for designing of openCV in FPGA exploitation, comprises the following steps:

Step 1: develop OpenCV application on computers, adopts the compiler of C++ to compile it, emulate and debug, finally produces executable file;

Step 2: the part using I/O functions extract FPGA to realize, uses VivadoHLSVideo built-in function code that can be comprehensive to replace calling of OpenCV function;

Step 3: run HLS and generate RTL code, start co-sim in VivadoHLS engineering, the RTL code that the test and excitation checking that OpenCV reused automatically by HLS instrument produces; The integrated of RTL and SoC/FPGA realization is done in ISE or the Vivado development environment of Xilinx.

Claims (1)

1. in FPGA exploitation, use ViadoHLS to realize the method for designing of openCV, it is characterized in that: comprise the following steps:

Step 1: develop OpenCV application on computers, adopts the compiler of C++ to compile it, emulate and debug, finally produces executable file;

Step 2: the part using I/O functions extract FPGA to realize, uses VivadoHLSVideo built-in function code that can be comprehensive to replace calling of OpenCV function;

Step 3: run HLS and generate RTL code, start co-sim in VivadoHLS engineering, the RTL code that the test and excitation checking that OpenCV reused automatically by HLS instrument produces; The integrated of RTL and SoC/FPGA realization is done in ISE or the Vivado development environment of Xilinx.