CN104301738A - Video coding and decoding method and three-dimensional video coding and decoding device - Google Patents
Video coding and decoding method and three-dimensional video coding and decoding device Download PDFInfo
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- CN104301738A CN104301738A CN201310303248.0A CN201310303248A CN104301738A CN 104301738 A CN104301738 A CN 104301738A CN 201310303248 A CN201310303248 A CN 201310303248A CN 104301738 A CN104301738 A CN 104301738A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/597—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
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Abstract
The invention discloses a video coding and decoding method and a three-dimensional video coding and decoding device. The video decoding method comprises steps that: if an MV-HEVC code stream is received, tools included in all 3D-HEVC but not included in MV-HEVC are closed, MV-HEVC code stream decoding is carried out; if a 3D-HEVC code stream is received, 3D-HEVC code stream decoding is carried out; the video coding method comprises steps that: 3D-HEVC code stream is encoded, tools included in all the 3D-HEVC but not included the MV-HEVC are provided with a switch marking position, and a value is set to indicate to open or close the corresponding tool. According to the method, MV-HEVC code stream decoding can be carried out by the three-dimensional video coding and decoding device, compatibility of the 3D-HEVC and the MV-HEVC is realized, and more flexibility is further provided for the 3D-HEVC.
Description
Technical field
The present invention relates to 3 D video encoding and decoding and multi-angle video encoding and decoding technique field, particularly relate to video coding-decoding method and 3 D video codec.
Background technology
3D-HEVC(3D High Efficiency Video Coding, 3 D video compression standard based on efficient video coding) MV-HEVC(Multi-View High Efficiency Video Coding can be regarded as, the multi-view video coding standard based on efficient video coding) expansion.But in existing design, 3D-HEVC can not compatible MV-HEVC.This irrational design wastes the ability of 3 D video decoder.
Summary of the invention
The embodiment of the present invention provides a kind of video encoding/decoding method, and in order to make 3 D video decoder can decode MV-HEVC code stream, realize the compatible MV-HEVC of 3D-HEVC, the method comprises:
If receive MV-HEVC code stream, then close all 3D-HEVC and comprise but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding;
If receive 3D-HEVC code stream, then carry out 3D-HEVC code stream decoding.
In an embodiment, above-mentioned video encoding/decoding method also comprises:
The flag bit of extending video parameter set 2 is obtained after receiving code stream;
According to the flag bit of extending video parameter set 2, determine that the code stream received is MV-HEVC code stream or 3D-HEVC code stream.
In an embodiment, above-mentioned video encoding/decoding method also comprises:
If receive MV-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes.
In an embodiment, describedly to comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits for all 3D-HEVC, and value is all set to instruction closes, comprises:
In extending video parameter set 2, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes, extending video parameter set 2 of now not decoding.
In an embodiment, above-mentioned video encoding/decoding method also comprises:
If receive 3D-HEVC code stream, according to comprising for all 3D-HEVC but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.
In an embodiment, described basis is that all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, opens or closes corresponding instrument, comprising:
Decoding expansion video parameter collection 2, according in extending video parameter set 2 for all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.
In an embodiment, describedly to comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC for all 3D-HEVC, the decoding capability according to decoding end is arranged.
The embodiment of the present invention also provides a kind of method for video coding, and with thinking that 3D-HEVC provides more flexibility, the method comprises:
Coding 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument.
In an embodiment, describedly to comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits for all 3D-HEVC, and value is set to instruction opens or closes corresponding instrument, comprises:
According to the decoding capability of decoding end, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits.
In an embodiment, above-mentioned method for video coding also comprises:
Arrange the value of the flag bit of extending video parameter set 2, the code stream coded by instruction is MV-HEVC code stream or 3D-HEVC code stream.
The embodiment of the present invention also provides a kind of 3 D video decoder, and in order to make 3 D video decoder can decode MV-HEVC code stream, realize the compatible MV-HEVC of 3D-HEVC, this 3 D video decoder comprises:
Determination module is MV-HEVC code stream or 3D-HEVC code stream with the code stream determining to receive;
Various visual angles decoder module, after determining to receive MV-HEVC code stream at described determination module, closes all 3D-HEVC and comprises but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding;
Three-dimensional decoder module, after determining to receive 3D-HEVC code stream at described determination module, carries out 3D-HEVC code stream decoding.
In an embodiment, described determination module comprises:
Obtain unit, for obtaining the flag bit of extending video parameter set 2 after receiving code stream;
Determining unit, for the flag bit according to extending video parameter set 2, determines that the code stream received is MV-HEVC code stream or 3D-HEVC code stream.
In an embodiment, above-mentioned 3 D video decoder also comprises:
Switching flag bits arranges module, and after determining to receive MV-HEVC code stream at described determination module, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes.
In an embodiment, described flag bit arranges module specifically in extending video parameter set 2, and for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes; Now described various visual angles decoder module is further used for extending video parameter set 2 of not decoding.
In an embodiment, above-mentioned 3 D video decoder also comprises:
Tool switch module, after determining to receive 3D-HEVC code stream at described determination module, according to comprising for all 3D-HEVC but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, opens or closes corresponding instrument.
In an embodiment, described three-dimensional decoder module is further used for decoding expansion video parameter collection 2; Described tool switch module specifically for according in extending video parameter set 2 for all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.
In an embodiment, describedly to comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC for all 3D-HEVC, arrange according to decoding capability.
The embodiment of the present invention also provides a kind of 3 d video encoding device, and with thinking that 3D-HEVC provides more flexibility, this 3 d video encoding device comprises:
Coding module, for 3D-HEVC code stream of encoding;
Switching flag bits arranges module, and for when described coding module coding 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument.
In an embodiment, described flag bit arranges module specifically for the decoding capability according to decoding end, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits.
In an embodiment, above-mentioned 3 d video encoding device also comprises:
Code stream traffic sign placement module, for arranging the value of the flag bit of extending video parameter set 2, the code stream coded by instruction is MV-HEVC code stream or 3D-HEVC code stream.
In the embodiment of the present invention, if receive MV-HEVC code stream, then close all 3D-HEVC and comprise but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding; If receive 3D-HEVC code stream, then carry out 3D-HEVC code stream decoding; Thus 3 D video decoder can be decoded MV-HEVC code stream, realize the compatible MV-HEVC of 3D-HEVC.
In the embodiment of the present invention, coding 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument, thus provide more flexibility for 3D-HEVC, open or close all 3D-HEVC flexibly and comprise but instrument not to be covered in MV-HEVC.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.In the accompanying drawings:
Fig. 1 is the process chart of video encoding/decoding method in the embodiment of the present invention;
Fig. 2 is the process chart of method for video coding in the embodiment of the present invention;
Fig. 3 is the structural representation of 3 D video decoder in the embodiment of the present invention;
Fig. 4 is the schematic diagram of the instantiation of determination module in the embodiment of the present invention;
Fig. 5 is the schematic diagram of the instantiation of the decoder of 3 D video shown in Fig. 3 in the embodiment of the present invention;
Fig. 6 is the schematic diagram of the instantiation of the decoder of 3 D video shown in Fig. 3 in the embodiment of the present invention;
Fig. 7 is the structural representation of 3 d video encoding device in the embodiment of the present invention;
Fig. 8 is the schematic diagram of the instantiation of the device of 3 d video encoding shown in Fig. 7 in the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly understand, below in conjunction with accompanying drawing, the embodiment of the present invention is described in further details.At this, schematic description and description of the present invention is for explaining the present invention, but not as a limitation of the invention.
Fig. 1 is the process chart of video encoding/decoding method in the embodiment of the present invention.As shown in Figure 1, in the embodiment of the present invention, video encoding/decoding method can comprise:
Step 101, determine that the code stream received is MV-HEVC code stream or 3D-HEVC code stream; If receive MV-HEVC code stream, then perform step 102; If receive 3D-HEVC code stream, then perform step 103;
Step 102, close all 3 D video compression standard 3D-HEVC based on efficient video coding and comprise but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding;
Step 103, carry out 3D-HEVC code stream decoding.
Flow process can be learnt as shown in Figure 1, in the embodiment of the present invention, when the code stream received is MV-HEVC code stream, close all 3D-HEVC to comprise but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding, 3 D video decoder can be decoded MV-HEVC code stream, realize the compatible MV-HEVC of 3D-HEVC.Because 3D-HEVC can regard the expansion of MV-HEVC as, MV-HEVC is a subset of 3D-HEVC in essence, therefore, all 3D-HEVC are comprised but instrument closedown not to be covered in MV-HEVC, the instrument that 3 D video decoder application MV-HEVC can be made to comprise decoding MV-HEVC code stream.
During concrete enforcement, can apply the code stream that a flag bit determines to receive is MV-HEVC code stream or 3D-HEVC code stream.Such as this flag bit can be video parameter collection (video parameter set, this parameter set has in MV-HEVC and 3D-HEVC code stream) in vps_extension2_flag(video parameter set extension2flag, the flag bit of extending video parameter set 2), the flag bit of extending video parameter set 2 can be obtained in enforcement after receiving code stream; According to the flag bit of extending video parameter set 2, determine that the code stream received is MV-HEVC code stream or 3D-HEVC code stream.During certain enforcement, this flag bit can be located at the other parts in code stream as required, such as, can be located at sequential parameter and concentrate.In an embodiment, when vps_extension2_flag is "false", can determine that the code stream received is MV-HEVC code stream, when vps_extension2_flag is "True", determine that the code stream received is 3D-HEVC code stream.
During concrete enforcement, when receiving MV-HEVC code stream, can to comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits for all 3D-HEVC, and value is all set to instruction closes, such as, is set to "false", and these instruments of corresponding closedown.Switching flag bits such as can be located in extending video parameter set 2, and when certainly implementing, switching flag bits also can be located at the other parts in code stream as required.In an embodiment, in extending video parameter set 2, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes, extending video parameter set 2 of now not decoding.
During concrete enforcement, if receive 3D-HEVC code stream, then according to comprising for all 3D-HEVC but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, corresponding instrument can be opened or closed.If switching flag bits is located in extending video parameter set 2, then when receiving 3D-HEVC code stream, can decoding expansion video parameter collection 2, according in extending video parameter set 2 for all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.Be that all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC during enforcement, can arrange according to the decoding capability of decoding end.Such as, at coding side, according to the decoding capability of decoding end, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits.
In an enforcement, also can not to comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits for all 3D-HEVC, but wherein only have Some tools to be provided with the value of switching flag bits, now, decoding end is when receiving 3D-HEVC code stream, the value of the switching flag bits only arranged according to this part instrument, opens or closes this part instrument.For all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits, be actually and can provide more flexibility for 3D-HEVC, all 3D-HEVC can be opened or closed flexibly according to factors such as the decoding capabilities of decoding end and comprise but instrument not to be covered in MV-HEVC.Such as, in existing 3D-HEVC, vps_extension2 only includes the switching flag bits of Some tools, if coding side does not carry out the setting of switching flag bits value to other instrument, then decoding end can only open or close this part instrument, if and coding side comprises all 3D-HEVC but in MV-HEVC, instrument not to be covered carries out the setting of switching flag bits value, can think that 3D-HEVC provides more flexibilities, all 3D-HEVC can be opened or closed flexibly according to factors such as the decoding capabilities of decoding end to comprise but instrument not to be covered in MV-HEVC, autgmentability is better.
Fig. 2 is the process chart of method for video coding in the embodiment of the present invention.As shown in Figure 2, in the embodiment of the present invention, method for video coding can comprise:
Step 201, coding 3D-HEVC code stream;
Step 202, to comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits for all 3D-HEVC, and value is set to instruction opens or closes corresponding instrument.
As previously mentioned, in the embodiment of the present invention, coding 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument, more flexibility can be provided for 3D-HEVC, open or close all 3D-HEVC flexibly and comprise but instrument not to be covered in MV-HEVC.
During concrete enforcement, describedly to comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits for all 3D-HEVC, and value is set to instruction opens or closes corresponding instrument, can comprise: according to the decoding capability of decoding end, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits.
During concrete enforcement, can also arrange the value of the flag bit of extending video parameter set 2, the code stream coded by instruction is MV-HEVC code stream or 3D-HEVC code stream.As previously mentioned, code stream during enforcement coded by instruction is the other parts that the flag bit of MV-HEVC code stream or 3D-HEVC code stream also can be located in code stream, such as, can be located at sequential parameter and concentrate.In an embodiment, can when vps_extension2_flag be "false", the code stream coded by instruction is MV-HEVC code stream, and when vps_extension2_flag is "True", the code stream coded by instruction is 3D-HEVC code stream.
Based on same inventive concept, additionally provide a kind of 3 D video decoder and 3 d video encoding device in the embodiment of the present invention, as described in the following examples.The principle of dealing with problems due to 3 D video decoder and 3 d video encoding device is similar to aforementioned video coding/decoding method and method for video coding respectively, therefore the enforcement of 3 D video decoder and 3 d video encoding device see the enforcement of correlation method, can repeat part and repeats no more.
Fig. 3 is the structural representation of 3 D video decoder in the embodiment of the present invention.As shown in Figure 3, in the embodiment of the present invention, 3 D video decoder can comprise:
Determination module 301 is MV-HEVC code stream or 3D-HEVC code stream with the code stream determining to receive;
Various visual angles decoder module 302, for after described determination module 301 determines to receive MV-HEVC code stream, closes all 3D-HEVC and comprises but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding;
Three-dimensional decoder module 303, for after described determination module 301 determines to receive 3D-HEVC code stream, carries out 3D-HEVC code stream decoding.
Fig. 4 is the schematic diagram of the instantiation of determination module in the embodiment of the present invention.As shown in Figure 4, determination module can comprise:
Obtain unit 401, for obtaining the flag bit of extending video parameter set 2 after receiving code stream;
Determining unit 402, for the flag bit according to extending video parameter set 2, determines that the code stream received is MV-HEVC code stream or 3D-HEVC code stream.
Fig. 5 is the schematic diagram of the instantiation of the decoder of 3 D video shown in Fig. 3 in the embodiment of the present invention.As shown in Figure 5, the decoder of 3 D video shown in Fig. 3 can also comprise:
Switching flag bits arranges module 501, and for after described determination module 301 determines to receive MV-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes.
During concrete enforcement, described flag bit arranges module can specifically in extending video parameter set 2, and for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes; Now described various visual angles decoder module can be further used for extending video parameter set 2 of not decoding.
Fig. 6 is the schematic diagram of the instantiation of the decoder of 3 D video shown in Fig. 3 in the embodiment of the present invention.As shown in Figure 6, the decoder of 3 D video shown in Fig. 3 can also comprise:
Tool switch module 601, for after described determination module 301 determines to receive 3D-HEVC code stream, according to comprising for all 3D-HEVC but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, opens or closes corresponding instrument.
During concrete enforcement, described three-dimensional decoder module can be further used for decoding expansion video parameter collection 2; Described tool switch module can specifically for according in extending video parameter set 2 for all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.
During concrete enforcement, describedly to comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC for all 3D-HEVC, can arrange according to decoding capability.
Fig. 7 is the structural representation of 3 d video encoding device in the embodiment of the present invention.As shown in Figure 7, in the embodiment of the present invention, 3 d video encoding device can comprise:
Coding module 701, for 3D-HEVC code stream of encoding;
Switching flag bits arranges module 702, and for when described coding module 701 encodes 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument.
During concrete enforcement, described flag bit arranges module can specifically for the decoding capability according to decoding end, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits.
Fig. 8 is the schematic diagram of the instantiation of the device of 3 d video encoding shown in Fig. 7 in the embodiment of the present invention.As shown in Figure 8, the device of 3 d video encoding shown in Fig. 7 can also comprise:
Code stream traffic sign placement module 801, for arranging the value of the flag bit of extending video parameter set 2, the code stream coded by instruction is MV-HEVC code stream or 3D-HEVC code stream.
In sum, in the embodiment of the present invention, if receive MV-HEVC code stream, then close all 3D-HEVC and comprise but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding; If receive 3D-HEVC code stream, then carry out 3D-HEVC code stream decoding; Thus 3 D video decoder can be decoded MV-HEVC code stream, realize the compatible MV-HEVC of 3D-HEVC.
In the embodiment of the present invention, coding 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument, thus provide more flexibility for 3D-HEVC, open or close all 3D-HEVC flexibly and comprise but instrument not to be covered in MV-HEVC.
Those skilled in the art should understand, embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disc store, CD-ROM, optical memory etc.) of computer usable program code.
The present invention describes with reference to according to the flow chart of the method for the embodiment of the present invention, equipment (system) and computer program and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can being provided to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device to produce a machine, making the instruction performed by the processor of computer or other programmable data processing device produce device for realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, make on computer or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computer or other programmable devices is provided for the step realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (20)
1. a video encoding/decoding method, is characterized in that, comprising:
If receive the multi-view video coding standard MV-HEVC code stream based on efficient video coding, then close all 3 D video compression standard 3D-HEVC based on efficient video coding and comprise but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding;
If receive 3D-HEVC code stream, then carry out 3D-HEVC code stream decoding.
2. the method for claim 1, is characterized in that, also comprises:
The flag bit of extending video parameter set 2 is obtained after receiving code stream;
According to the flag bit of extending video parameter set 2, determine that the code stream received is MV-HEVC code stream or 3D-HEVC code stream.
3. the method for claim 1, is characterized in that, also comprises:
If receive MV-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes.
4. method as claimed in claim 3, is characterized in that, describedly to comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits for all 3D-HEVC, and value is all set to instruction closes, and comprising:
In extending video parameter set 2, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes, extending video parameter set 2 of now not decoding.
5. the method for claim 1, is characterized in that, also comprises:
If receive 3D-HEVC code stream, according to comprising for all 3D-HEVC but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.
6. method as claimed in claim 5, is characterized in that, described basis is that all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, opens or closes corresponding instrument, comprising:
Decoding expansion video parameter collection 2, according in extending video parameter set 2 for all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.
7. method as claimed in claim 5, is characterized in that, describedly comprises but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC for all 3D-HEVC, and the decoding capability according to decoding end is arranged.
8. a method for video coding, is characterized in that, comprising:
Coding 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument.
9. method as claimed in claim 8, is characterized in that, describedly to comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits for all 3D-HEVC, and value is set to instruction opens or closes corresponding instrument, comprising:
According to the decoding capability of decoding end, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits.
10. method as claimed in claim 8, is characterized in that, also comprise:
Arrange the value of the flag bit of extending video parameter set 2, the code stream coded by instruction is MV-HEVC code stream or 3D-HEVC code stream.
11. 1 kinds of 3 D video decoders, is characterized in that, comprising:
Determination module is MV-HEVC code stream or 3D-HEVC code stream with the code stream determining to receive;
Various visual angles decoder module, after determining to receive MV-HEVC code stream at described determination module, closes all 3D-HEVC and comprises but instrument not to be covered in MV-HEVC, carry out MV-HEVC code stream decoding;
Three-dimensional decoder module, after determining to receive 3D-HEVC code stream at described determination module, carries out 3D-HEVC code stream decoding.
12. 3 D video decoders as claimed in claim 11, it is characterized in that, described determination module comprises:
Obtain unit, for obtaining the flag bit of extending video parameter set 2 after receiving code stream;
Determining unit, for the flag bit according to extending video parameter set 2, determines that the code stream received is MV-HEVC code stream or 3D-HEVC code stream.
13. 3 D video decoders as claimed in claim 11, is characterized in that, also comprise:
Switching flag bits arranges module, and after determining to receive MV-HEVC code stream at described determination module, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes.
14. 3 D video decoders as claimed in claim 13, it is characterized in that, described flag bit arranges module specifically in extending video parameter set 2, and for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is all set to instruction closes; Now described various visual angles decoder module is further used for extending video parameter set 2 of not decoding.
15. 3 D video decoders as claimed in claim 11, is characterized in that, also comprise:
Tool switch module, after determining to receive 3D-HEVC code stream at described determination module, according to comprising for all 3D-HEVC but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, opens or closes corresponding instrument.
16. 3 D video decoders as claimed in claim 15, it is characterized in that, described three-dimensional decoder module is further used for decoding expansion video parameter collection 2; Described tool switch module specifically for according in extending video parameter set 2 for all 3D-HEVC comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC, open or close corresponding instrument.
17. 3 D video decoders as claimed in claim 15, is characterized in that, describedly comprise but the value of the switching flag bits that instrument not to be covered is arranged in MV-HEVC for all 3D-HEVC, arrange according to decoding capability.
18. 1 kinds of 3 d video encoding devices, is characterized in that, comprising:
Coding module, for 3D-HEVC code stream of encoding;
Switching flag bits arranges module, and for when described coding module coding 3D-HEVC code stream, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges switching flag bits, and value is set to instruction opens or closes corresponding instrument.
19. 3 d video encoding devices as claimed in claim 18, it is characterized in that, described flag bit arranges module specifically for the decoding capability according to decoding end, for all 3D-HEVC comprise but in MV-HEVC, instrument not to be covered arranges the value of switching flag bits.
20. 3 d video encoding devices as claimed in claim 18, is characterized in that, also comprise:
Code stream traffic sign placement module, for arranging the value of the flag bit of extending video parameter set 2, the code stream coded by instruction is MV-HEVC code stream or 3D-HEVC code stream.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310303248.0A CN104301738B (en) | 2013-07-18 | 2013-07-18 | Video coding-decoding method and 3 D video codec |
| PCT/CN2013/090672 WO2015007066A1 (en) | 2013-07-18 | 2013-12-27 | Video encoding and decoding method and three-dimensional video codec |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310303248.0A CN104301738B (en) | 2013-07-18 | 2013-07-18 | Video coding-decoding method and 3 D video codec |
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| Publication Number | Publication Date |
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| CN104301738A true CN104301738A (en) | 2015-01-21 |
| CN104301738B CN104301738B (en) | 2018-03-23 |
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| CN (1) | CN104301738B (en) |
| WO (1) | WO2015007066A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020181434A1 (en) * | 2019-03-08 | 2020-09-17 | Zte Corporation | Parameter set signaling in digital video |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP3548523B1 (en) | 2016-12-05 | 2022-08-03 | Covestro Deutschland AG | Method and system for the production of an object through layered construction in a stamping process |
-
2013
- 2013-07-18 CN CN201310303248.0A patent/CN104301738B/en not_active Expired - Fee Related
- 2013-12-27 WO PCT/CN2013/090672 patent/WO2015007066A1/en active Application Filing
Non-Patent Citations (3)
| Title |
|---|
| GERHARD TECH等: "JCT3V-D1004-v4：MV-HEVC Draft Text 4", 《JOINT COLLABORATIVE TEAM ON 3D VIDEO CODING EXTENSION DEVELOPMENT》 * |
| GERHARD TECH等: "JCT3V-D1005-spec-v4：3D-HEVC Test Model 4", 《JOINT COLLABORATIVE TEAM ON 3D VIDEO CODING EXTENSION DEVELOPMENT》 * |
| YING CHEN 等: "JCTVC-J0124：AHG10: Video parameter setfor HEVC extensions", 《JOINT COLLABORATIVE TEAM ON VIDEO CODING (JCT-VC)》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020181434A1 (en) * | 2019-03-08 | 2020-09-17 | Zte Corporation | Parameter set signaling in digital video |
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| Publication number | Publication date |
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| WO2015007066A1 (en) | 2015-01-22 |
| CN104301738B (en) | 2018-03-23 |
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