CN104299650A - Improved optional grid driving circuit - Google Patents
Improved optional grid driving circuit Download PDFInfo
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- CN104299650A CN104299650A CN201410495240.3A CN201410495240A CN104299650A CN 104299650 A CN104299650 A CN 104299650A CN 201410495240 A CN201410495240 A CN 201410495240A CN 104299650 A CN104299650 A CN 104299650A
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- nmos tube
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- pmos
- grid
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Abstract
The invention discloses an improved optional grid driving circuit. Compared with the conventional optional grid driving circuit, the circuit is characterized in that two NMOS transistors of triple-well process are additionally arranged, wherein an NMOS transistor (a second NMOS tube M6) is capable of isolating during reading; the other NMOS transistor (a third NMOS tube M7) is capable of avoiding flotation node in the circuit during wiping. The optional grid driving circuit is relatively short in response time during reading, so that the reading is accelerated; the reading period is shortened; the influence of the flotation node is avoided during wiping; the hidden danger of error circuit function is avoided; the overall stability of a memorizer is improved; the access performance of the memorizer is improved.
Description
Technical field
The present invention relates to flash storage field, be specifically related to the selection gate driver circuit of many Gate Memory.
Background technology
In recent years, nonvolatile memory is applicable in a large amount of different types of application such as code and data storage.Especially, flash storage is used widely in the portable use of storage figure picture, sound, music and video etc.The most classical structure of flash storage is the ETOX single tube structure that Intel Company proposes, effectively reduce the area of storage unit, but brought erasing, the series of problems such as disturbance, be different from single tube Flash structure, 2-T Flash structure adopts storage tube and the structure selecting pipe to connect, by selecting not need the storage unit of accessing to turn off up hill and dale in pipe pair array.The anti-disturbance ability of 2-T structure is strong, and programming and erasing good stability, be generally applicable to voltage, power consumption requirements strictly, but low, the low density occasion of capacity.2-T Flash structure Storage Unit comprises the grid (selecting grid and control gate) of two independent bias, and control gate is coupled in control gate wordline and selects grid to be coupled in selection grid wordline.Storage unit is by controlling to select grid wordline and control gate wordline to conduct interviews.For this reason, must design and meet the requirements and the selection grid word line driving circuit of excellent performance, storage unit is correctly worked.
The word line driving circuit that a kind of multivoltage is selected is disclosed in US Patent No. 005265052A, as shown in Figure 1, its advantage is by the substrate of PMOS isolated transistor T1 with T2 is connected with the output of selector switch SW1, makes the reverse-biased generation achieving negative pressure all the time of the PN junction of PMOS transistor T1 and T2 substrate and diffusion region.But the ability of this cross-linked structure reactive circuit interference is poor, and circuit stability is not high, easily produces mistake and outputs to wordline.
As shown in Figure 2, by a signal control end CHIPERASE, and three voltage input end mouths WELL, VPPSG and VNNSG control the voltage outputting to SG end to the more selection grid driving circuit of current use.The positive high voltage of voltage input end mouth or negative high voltage can from the charge pump circuit of memory inside.Itself there are some defects in its electricity.When reading state, SG end should export the negative low pressure provided by voltage input end mouth VNNSG, and WELL and VPPSG end should export high level vdd, after XD becomes high level, M4 pipe turns off, and SG drops to negative low pressure from vdd, because M6 pipe does not turn off always, cause SGB terminal voltage unstable, have impact on the speed of SG voltage drop, impact is created on the reading speed of storer entirety.When erase status, CHIPERASE termination high level vdd, causes M5 pipe to turn off, and SGB node (grid of M7 pipe) is floating, affects the performance of circuit, easily makes SG hold the voltage of output error.
Summary of the invention
The object of the invention is to overcome prior art Problems existing, provide a kind of modified to select grid driving circuit.
For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:
A kind of modified selects grid driving circuit, comprises the first signal end WELL, secondary signal end VPPSG, the 3rd signal end CHIPERASE, the 4th signal end VNNSG, decoder output XD and signal output part SG;
And the first NMOS tube M1, the first PMOS M2 of decoder output XD is connected by grid, the drain electrode of described first NMOS tube M1 connects the input end of the first reverser I1 and the drain electrode of the second PMOS M3;
The output terminal of described first reverser I1 connects the grid of the second PMOS M3 and the grid of the 3rd PMOS M4;
The source electrode of described 3rd PMOS M4 connects secondary signal end VPPSG, drain electrode connection signal output terminal SG, the grid of the 4th NMOS tube M8 and the drain electrode of the 5th NMOS tube M9, and substrate connects the first signal end WELL;
Described first signal end WELL connects the N trap of the substrate of the 4th PMOS M5, the N trap of the 4th NMOS tube M8 and the 5th NMOS tube M9 respectively, and the grid of described 4th PMOS M5 meets the 3rd signal end CHIPERASE;
Described 5th NMOS tube M9 source electrode be connected with P trap, and connect the source electrode of the 4th NMOS tube M8 and P trap and the 4th signal end VNNSG simultaneously;
It is characterized in that, also include the second NMOS tube M6 and the 3rd NMOS tube M7;
The drain electrode of described second NMOS tube M6 connects the grid of the drain electrode of the 4th PMOS M5, the drain electrode of the 3rd NMOS tube M7 and the 5th NMOS tube M9 respectively, and form SGB node at connected node place, the N trap of the second NMOS tube M6 connects the first signal end WELL, P trap connects the 4th signal end VNNSG, the grid of the second NMOS tube M6 connects the drain electrode of the first NMOS tube M1, and the source electrode of the second NMOS tube M6 connects the source electrode of the 3rd NMOS tube M7;
The N trap of described 3rd NMOS tube M7 connects the first signal end WELL, and P trap connects the drain electrode of source electrode connection the 4th NMOS tube M8 of described 4th signal end VNNSG, the 3rd NMOS tube M7, and the grid of the 3rd NMOS tube M7 connects so the 3rd signal end CHIPERASE.
Further, described second NMOS tube M6, the 3rd NMOS tube M7, the 4th NMOS tube M8, the 5th NMOS tube M9 are triple-well process high pressure NMOS pipe.
Further, described triple-well process high pressure NMOS pipe comprises drain electrode end D, gate terminal G, source terminal S, PWI end and NWD end, and wherein PWI end connects P trap, and PWI end to be held with NWD through a parasitic diode and is connected, NWD termination N trap.
Further, described 3rd PMOS M4 and described 4th PMOS M5 is high voltage bearing PMOS.
Further, this driving circuit comprises programming state, reading state and erase status according to each signal end level change.
The invention has the beneficial effects as follows:
1, add the second NMOS tube M6, the effect of isolation SGB node and the 4th NMOS tube M8 is played when reading state, first signal end WELL and secondary signal end VPPSG meets high level vdd, 3rd signal end CHIPERASE is low level vdd, 4th signal end VNNSG bears low pressure, make selected storage unit SGB node not by the impact that high pressure NMOS pipe M8 opens in short-term, maintain vdd always, accelerate the velocity of discharge of signal output part SG, make signal output part SG can arrive required negative low pressure quickly, simultaneously, this also contributes to shortening read cycle, the reading performance of storer is provided.
2, add the 3rd NMOS tube M7, when erase status, first signal end WELL and secondary signal end VPPSG connects positive high voltage, 4th signal end VNNSG connects low level, 3rd signal end CHIPERASE is high level vdd, described 3rd NMOS tube M7 is opened, SGB node discharges into low level by the 3rd NMOS tube M7 and the 4th NMOS tube M8, 5th NMOS tube M9 is turned off, signal output part SG exports the positive high voltage needed for erasing, here SGB node is no longer floating, ensure that the correctness of circuit function, the stability of memory erase function is enhanced, improve the overall performance of storer.
Accompanying drawing explanation
The word line driving circuit schematic diagram that Fig. 1 selects for multivoltage a kind of disclosed in US Patent No. 005265052A;
Fig. 2 is traditional selection grid driving circuit schematic diagram;
Fig. 3 is selection grid driving circuit schematic diagram of the present invention;
Fig. 4 is the NMOS tube schematic diagram of triple-well process of the present invention;
The contrast schematic diagram of Fig. 5 output terminal response time when to be selection grid driving circuit of the present invention select grid driving circuit to read with tradition.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
As shown in Figure 3, a kind of modified selects grid driving circuit, comprises the first signal end WELL, secondary signal end VPPSG, the 3rd signal end CHIPERASE, the 4th signal end VNNSG, decoder output XD and signal output part SG.
Wherein, the grid of the first NMOS tube M1 meets code translator output signal XD, the source ground of the first NMOS tube M1, and the drain electrode of the first NMOS tube M1 is connected with the drain electrode of the first PMOS M2, the source electrode that the grid of the first PMOS M2 meets code translator output signal XD, the first PMOS M2 meets supply voltage vdd.The grid of the second PMOS M3 is connected with the output terminal of the first reverser I1, and the source electrode of the second PMOS M3 meets supply voltage vdd, and the drain electrode of the second PMOS M3 is connected with the drain electrode of described first NMOS tube.The input end of the first phase inverter I1 is connected with the drain electrode of a NOMS pipe M1, and the output terminal of the first phase inverter I1 is connected with the grid of the second PMOS M3.3rd PMOS M4 and the 4th PMOS M5 is high voltage bearing PMOS.The grid of the 3rd PMOS M4 is connected with the output terminal of the first phase inverter I1, and the source electrode of the 3rd PMOS M4 meets secondary signal end VPPSG, and the drain electrode of the 3rd PMOS M4 meets signal output part SG, and the substrate of the 3rd PMOS M4 meets the first signal end WELL.The grid of the 4th PMOS M5 meets the 3rd signal end CHIPERASE, the source electrode of the 4th PMOS M5 is connected with the grid of the 3rd PMOS M4, the drain electrode of the 4th PMOS M5 is connected with the drain electrode of the 3rd NMOS tube M7, and the substrate of the 4th PMOS M5 is connected with the first signal end WELL.Second NMOS tube M6, the 3rd NMOS tube M7, the 4th NMOS tube M8, the 5th NMOS tube M9 are the high pressure NMOS pipes of triple-well process, its structure as shown in Figure 4, D end is the drain electrode of integral device, G end is the grid of integral device, S end is the source electrode of integral device, PWI termination P trap, PWI to hold with NWD through a parasitic diode and is connected, NWD termination N trap.The grid of the second NMOS tube M6 is connected with the drain electrode of the first NMOS tube M1, the drain electrode of the second NMOS tube M6 is connected with the drain electrode of the 4th PMOS M5, the source electrode of the second NMOS tube M6 is connected with the source electrode of the 3rd NMOS tube M7, the P trap of the second NMOS tube M6 is connected with the 4th signal end VNNSG, and the N trap of the second NMOS tube M6 is connected with the first signal end WELL.The grid of the 3rd NMOS tube M7 meets the 3rd signal end CHIPERASE, the drain electrode of the 3rd NMOS tube M7 is connected with the drain electrode of the 4th PMOS M5, the source electrode of the 3rd NMOS tube M7 is connected with the source electrode of the second NMOS tube M6, the P trap of the 3rd NMOS tube M7 meets the 4th signal end VNNSG, and the N trap of the 3rd NMOS tube M7 meets described first signal end WELL.The signal output terminal SG of the 4th NMOS tube M8, the drain electrode of the 4th NMOS tube M8 is connected with the source electrode of the 3rd NMOS tube M7, the source electrode of the 4th NMOS tube M8 meets the 4th signal end VNNSG, the P trap of the 4th NMOS tube M8 meets described 4th signal end VNNSG, and the N trap of the 4th NMOS tube M8 meets the first signal end WELL.The grid of the 5th NMOS tube M9 is connected with the drain electrode of the 4th PMOS M5.The drain electrode of the 5th NMOS tube M9 meets signal output part SG, and the source electrode of the 5th NMOS tube M9 meets the 4th signal end VNNSG, and the P trap of the 5th NMOS tube M9 meets the 4th signal end VNNSG, and the N trap of the 5th NMOS tube M9 meets described first signal end WELL.
Above-mentioned is the present embodiment particular circuit configurations, continues with reference to Fig. 3:
During programming state, the first signal end WELL and secondary signal end VPPSG meets high level vdd, and the 3rd signal end CHIPERASE connects low level (0v), and the 4th signal end VNNSG connects negative high voltage; When storage unit is selected, decoder output XD exports high level vdd, then reverser I1 also exports high level vdd, and the 3rd PMOS M4 is turned off; Because the 3rd signal end CHIPERASE connects low level, therefore the 4th PMOS M5 opens, make node SGB maintain high level, SGB node is the grid of the 5th NMOS tube M9, cause the 5th NMOS tube M9 to open, signal output part SG is charged to the negative high voltage needed for programming with the 4th signal end VNNSG.
During reading state, first signal end WELL and secondary signal end VPPSG meets high level vdd, 3rd signal end CHIPERASE connects low level (0v), the 4th signal end VNNSG storage unit selected rear maintenance a period of time low level (0v) subsequently by boost to negative high-low pressure; When storage unit is selected, decoder output XD exports high level vdd, then reverser I1 also exports high level vdd, and the 3rd PMOS M4 is turned off; Because the 3rd signal end CHIPERASE connects low level, therefore the 4th PMOS M5 opens, isolate the second NMOS tube M6 to turn off, node SGB is made to maintain high level, SGB node is the grid of the 5th NMOS tube M9, cause the 5th NMOS tube M9 to open, signal output part SG is charged to the negative low pressure needed for programming with the 4th signal end VNNSG.
During erase status, the first signal end WELL and secondary signal end VPPSG connects positive high voltage, and the 3rd signal end CHIPERASE meets high level vdd, and the 4th signal end VNNSG connects low level (0v); Flash storage adopts monoblock erasing, because secondary signal end VPPSG connects positive high voltage, the 3rd PMOS M4 is opened; Signal output part SG is charged to the positive high voltage needed for programming with secondary signal end VPPSG.
Principle of the present invention:
Add the second NMOS tube M6, the effect of isolation SGB node and described 4th NMOS tube M8 is played when reading state, first signal end WELL and secondary signal end VPPSG meets high level vdd, 3rd signal end CHIPERASE is low level vdd, 4th signal end VNNSG bears low pressure, make selected storage unit SGB node not by the impact that high pressure NMOS pipe M8 opens in short-term, maintain vdd always, accelerate the velocity of discharge of signal output part SG, make signal output part SG can arrive required negative low pressure quickly.Meanwhile, this also contributes to shortening read cycle, provides the reading performance of storer.Figure 5 shows that the present invention's (dotted line) and prior art signal output part SG when reading state discharge into the time comparison diagram (adopting two-stage to discharge) of required negative low pressure, obviously can find out that from figure the present invention has the velocity of discharge faster.
Add the 3rd NMOS tube M7, when erase status, described first signal end WELL and described secondary signal end VPPSG connects positive high voltage, described 4th signal end VNNSG connects low level, described 3rd signal end CHIPERASE is high level vdd, and described 3rd NMOS tube M7 is opened, and SGB node discharges into low level by described 3rd NMOS tube M7 and described 4th NMOS tube M8, described 5th NMOS tube M9 is turned off, and signal output part SG exports the positive high voltage needed for erasing.Here SGB node is no longer floating, ensure that the correctness of circuit function, the stability of memory erase function is enhanced, improves the overall performance of storer.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. modified selects a grid driving circuit, comprises the first signal end WELL, secondary signal end VPPSG, the 3rd signal end CHIPERASE, the 4th signal end VNNSG, decoder output XD and signal output part SG;
And the first NMOS tube M1, the first PMOS M2 of decoder output XD is connected by grid, the drain electrode of described first NMOS tube M1 connects the input end of the first reverser I1 and the drain electrode of the second PMOS M3;
The output terminal of described first reverser I1 connects the grid of the second PMOS M3 and the grid of the 3rd PMOS M4;
The source electrode of described 3rd PMOS M4 connects secondary signal end VPPSG, drain electrode connection signal output terminal SG, the grid of the 4th NMOS tube M8 and the drain electrode of the 5th NMOS tube M9, and substrate connects the first signal end WELL;
Described first signal end WELL connects the N trap of the substrate of the 4th PMOS M5, the N trap of the 4th NMOS tube M8 and the 5th NMOS tube M9 respectively, and the grid of described 4th PMOS M5 meets the 3rd signal end CHIPERASE;
Described 5th NMOS tube M9 source electrode be connected with P trap, and connect the source electrode of the 4th NMOS tube M8 and P trap and the 4th signal end VNNSG simultaneously;
It is characterized in that, also include the second NMOS tube M6 and the 3rd NMOS tube M7;
The drain electrode of described second NMOS tube M6 connects the grid of the drain electrode of the 4th PMOS M5, the drain electrode of the 3rd NMOS tube M7 and the 5th NMOS tube M9 respectively, and form SGB node at connected node place, the N trap of the second NMOS tube M6 connects the first signal end WELL, P trap connects the 4th signal end VNNSG, the grid of the second NMOS tube M6 connects the drain electrode of the first NMOS tube M1, and the source electrode of the second NMOS tube M6 connects the source electrode of the 3rd NMOS tube M7;
The N trap of described 3rd NMOS tube M7 connects the first signal end WELL, and P trap connects the drain electrode of source electrode connection the 4th NMOS tube M8 of described 4th signal end VNNSG, the 3rd NMOS tube M7, and the grid of the 3rd NMOS tube M7 connects so the 3rd signal end CHIPERASE.
2. modified according to claim 1 selects grid driving circuit, and it is characterized in that, described second NMOS tube M6, the 3rd NMOS tube M7, the 4th NMOS tube M8, the 5th NMOS tube M9 are triple-well process high pressure NMOS pipe.
3. modified according to claim 2 selects grid driving circuit, it is characterized in that, described triple-well process high pressure NMOS pipe comprises drain electrode end D, gate terminal G, source terminal S, PWI end and NWD end, wherein PWI end connects P trap, and PWI end to be held with NWD through a parasitic diode and is connected, NWD termination N trap.
4. modified according to claim 1 selects grid driving circuit, and it is characterized in that, described 3rd PMOS M4 and described 4th PMOS M5 is high voltage bearing PMOS.
5. modified according to claim 1 selects grid driving circuit, it is characterized in that, this driving circuit comprises programming state, reading state and erase status according to each signal end level change.
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|---|---|---|---|
| CN201410495240.3A CN104299650A (en) | 2014-09-25 | 2014-09-25 | Improved optional grid driving circuit |
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| CN201410495240.3A CN104299650A (en) | 2014-09-25 | 2014-09-25 | Improved optional grid driving circuit |
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| CN104299650A true CN104299650A (en) | 2015-01-21 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5265052A (en) * | 1989-07-20 | 1993-11-23 | Texas Instruments Incorporated | Wordline driver circuit for EEPROM memory cell |
| US5513147A (en) * | 1994-12-19 | 1996-04-30 | Alliance Semiconductor Corporation | Row driving circuit for memory devices |
| CN1181632A (en) * | 1996-10-25 | 1998-05-13 | 株式会社日立制作所 | Dynamic memory |
| US20080298158A1 (en) * | 2007-05-31 | 2008-12-04 | Hari Giduturi | Two transistor wordline decoder output driver |
| CN102298967A (en) * | 2010-06-23 | 2011-12-28 | 上海宏力半导体制造有限公司 | Row decoding circuit of double-dissociation grid flash memory array and driving method thereof |
| CN204178727U (en) * | 2014-09-25 | 2015-02-25 | 苏州宽温电子科技有限公司 | A kind of modified selects grid driving circuit |
-
2014
- 2014-09-25 CN CN201410495240.3A patent/CN104299650A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5265052A (en) * | 1989-07-20 | 1993-11-23 | Texas Instruments Incorporated | Wordline driver circuit for EEPROM memory cell |
| US5513147A (en) * | 1994-12-19 | 1996-04-30 | Alliance Semiconductor Corporation | Row driving circuit for memory devices |
| CN1181632A (en) * | 1996-10-25 | 1998-05-13 | 株式会社日立制作所 | Dynamic memory |
| US20080298158A1 (en) * | 2007-05-31 | 2008-12-04 | Hari Giduturi | Two transistor wordline decoder output driver |
| CN102298967A (en) * | 2010-06-23 | 2011-12-28 | 上海宏力半导体制造有限公司 | Row decoding circuit of double-dissociation grid flash memory array and driving method thereof |
| CN204178727U (en) * | 2014-09-25 | 2015-02-25 | 苏州宽温电子科技有限公司 | A kind of modified selects grid driving circuit |
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Application publication date: 20150121 |