CN104282553A - Method for manufacturing IGBT - Google Patents
Method for manufacturing IGBT Download PDFInfo
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- CN104282553A CN104282553A CN201310281979.XA CN201310281979A CN104282553A CN 104282553 A CN104282553 A CN 104282553A CN 201310281979 A CN201310281979 A CN 201310281979A CN 104282553 A CN104282553 A CN 104282553A
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- substrate
- conduction type
- igbt
- manufacture method
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000008569 process Effects 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 description 6
- 230000004913 activation Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a method for manufacturing an IGBT. The method includes the steps that a substrate which is of a first conduction type or a second conduction type and is provided with a first surface and a second surface is provided; grooves formed at intervals are formed in the first surface of the substrate; the grooves are filled with a semiconductor material of the second conduction type or the first conduction type so that channels can be formed, wherein the conduction type of the channels is different from that of the substrate; a drift region of the second conduction type is formed on the first surface of the substrate in an epitaxial mode; a front structure of the IGBT is formed on the basis of the drift region; the substrate is thinned from the second surface of the substrate until the channels are exposed; a back metal electrode is formed on the channels and the thinned substrate. According to the method, the special requirement for sheet flow capacity is avoided, double-faced exposure machine equipment is not needed either, the method is compatible with an existing conventional process, the process is simple, and efficiency is high.
Description
[technical field]
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of IGBT(Insulated Gate Bipolar Transistor, igbt) manufacture method.
[background technology]
IGBT is by BJT(Bipolar Junction Transistor, bipolar junction transistor) and MOSFET(Metal-Oxide-Semiconductor-Field-Effect-Transistor, mos field effect transistor) the compound full-control type voltage driven type power semiconductor that forms, have the advantage of the high input impedance of MOSFET and low conduction voltage drop two aspect of BJT concurrently, there is operating frequency high, control circuit is simple, current density is high, on-state such as to force down at the feature, is widely used in power control field.In actual applications, IGBT seldom uses as an individual devices, and especially under the condition of inductive load, IGBT needs a fast recovery diode afterflow.Therefore, existing igbt product, the general fly-wheel diode in parallel (Freewheeling diode is called for short FWD) that adopts is to protect IGBT.In order to reduce costs, fly-wheel diode in parallel can be integrated in igbt chip, namely has the IGBT of diode-built-in or reverse-conducting.
The IGBT of common reverse-conducting needs thinning rear dual surface lithography to prepare the injection window of P+ collector area, the back side.The shortcoming of this scheme mainly contains two aspects: the first, need thinned wafer negotiability, and particularly for the IGBT of common below 1200V, its thickness, at below 200um, requires very high to thin slice flow-through process; The second, need special sided exposure machine to exposing wafer.In addition, the IGBT of existing reverse-conducting adopts back side Twi-lithography technology usually.
Therefore, be necessary to provide a kind of technical scheme of improvement to overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide the manufacture method of a kind of IGBT, itself and existing common process are compatible, and technique is simple, efficiency is high, greatly reduce process costs without the need to special equipment.
In order to solve the problem, according to an aspect of the present invention, the invention provides the manufacture method of a kind of IGBT, it comprises: provide and have the first conduction type of first surface and second surface or the substrate of the second conduction type; The groove at interval is formed at the first surface of described substrate; In described groove, fill the semi-conducting material of the second conduction type or the first conduction type to form passage, the conduction type of wherein said passage is different from the conduction type of described substrate; On the first surface of described substrate, extension forms the drift region of the second conduction type; The Facad structure of described IGBT is formed based on described drift region; Start thinning described substrate until expose described passage with the second surface from described substrate, now described passage and thinning after substrate space staggered; Described passage and thinning after substrate on form back metal electrode, this back metal electrode and described passage and thinning after substrate in electrical contact.
As a preferred embodiment of the present invention, the thickness of the substrate provided is 100-650um, and resistivity is 0.001 ~ 100 Ω * cm.The thickness of the drift region that extension is formed is 10 ~ 650um, and resistivity is 5 ~ 500 Ω * cm.The thickness of the drift region that the thickness of described substrate and described extension are formed and be the silicon wafer thickness that normally circulates.
As a preferred embodiment of the present invention, formed the groove at interval at the first surface at described substrate by photoetching, etch process.The degree of depth of described groove is 0.5 ~ 50um.
As a preferred embodiment of the present invention, after the semi-conducting material of filling second conduction type or the first conduction type, the semi-conducting material of filling is made to become monocrystalline silicon by high-temperature step, subsequently by the first surface of the smooth described substrate of CMP (Chemical Mechanical Polishing) process.
As a preferred embodiment of the present invention, the Facad structure of described IGBT comprises: the base of the first conduction type selectively formed on the upper surface of described drift region; The emitter region of the second conduction type selectively formed in described base; Be positioned at the gate oxide on the upper surface of described drift region; The polysilicon gate that the upper surface of described grid oxic horizon is formed; Cover the dielectric layer of described grid oxic horizon and polysilicon gate; With described base and described emitter region front metal electrode in electrical contact; Be formed at the passivation layer outside front metal electrode.
As a preferred embodiment of the present invention, described first conduction type is P type, and described second conduction type is N-type.
Compared with prior art, the manufacture method of IGBT in the present invention, first the spaced collector area at the back side of IGBT and the making of passage is completed, the Facad structure of IGBT is prepared afterwards on extension drift region, only need to do thinning and back face metalization step after Facad structure completes, particular/special requirement is not had to thin slice negotiability, does not more need double-sided exposure machine equipment.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the manufacture method flow chart in one embodiment of the IGBT in the present invention;
Fig. 2 to Fig. 8 is the vertical section schematic diagram that each manufacturing process of manufacture method in Fig. 1 obtains wafer.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.
Before the manufacture method introducing the IGBT in the present invention, it should be noted that, the emitter of IGBT and the face at grid place are understood to front usually, and the face at the collector electrode place of IGBT is understood reverse side usually.
Fig. 1 is manufacture method 100 flow chart in one embodiment of the IGBT in the present invention.As shown in Figure 1, described manufacture method 100 comprises the steps.
Step 110, shown in composition graphs 2, provides the P type or N-type substrate 10 with first surface 11 and second surface 12.
Concrete, the thickness of described substrate 10 can be 100 ~ 650um, and resistivity can be 0.001 ~ 100 Ω * cm.The thickness of described substrate 10 is relevant to the thickness of the extension drift region hereafter mentioned.
Step 120, as shown in Figure 3, forms the groove 13 at interval at the first surface 11 of described substrate 10 by photoetching, etch process.Concrete, the degree of depth of described groove can be 0.5 ~ 50um.
Step 130, shown in composition graphs 4, in described groove 13, filling N-type or P type semiconductor material are to form N-type or P type passage 14.
When described substrate is P type, form N-type passage in described step 130, when described substrate 10 is N-type, form P type passage in described step 130, conduction type is between the two contrary.In the embodiment shown by Fig. 2-7, be P type with backing material 10, passage 14 for N-type be that example is introduced.Concrete, as shown in Figure 3, N type semiconductor material (such as monocrystalline silicon, polysilicon, amorphous silicon) is filled in described groove 13, make the semi-conducting material of filling become monocrystalline silicon by high-temperature step thus obtain the N-type passage 14 after activating, subsequently by the first surface 11 of the smooth described substrate 10 of chemico-mechanical polishing (CMP) technique.Photoresist 30 in figure 3 can be removed in appropriate steps.
The activation of the N-type passage 14 in existing technique usually occurs in after front metal electrode formed, and the activation step in the present invention all occurs in before metal electrode formed, and improves the activation efficiency of doped region (such as N-type passage 14).
Step 140, shown in composition graphs 5, on the first surface 11 of described substrate 10, extension forms N-type drift region (N Drift) 15.
Concrete, the thickness of the drift region 15 that extension is formed is 10 ~ 650um, and resistivity is 5 ~ 500 Ω * cm.The thickness of described drift region 15 is relevant to the thickness of described substrate 10.The thickness of the drift region that the thickness of described substrate 10 and described extension are formed and be the silicon wafer thickness that normally circulates, the normal thickness such as 6 cun of sheets is 625um/675um, and the normal thickness of 8 cun of sheets is 725um.
Step 150, shown in composition graphs 6, adopts normal IGBT technological process to form the Facad structure of described IGBT based on described drift region 15.
The Facad structure of a kind of planar I GBT is illustrated in Fig. 6.The Facad structure of described IGBT comprises: the P type base (P-body) 16 selectively formed on the upper surface of described drift region 15, the N-type emitter region 17 selectively formed in described P type base 16, be positioned at the gate oxide 18 on the upper surface of described drift region 15, the polysilicon gate 19 (G) that described grid oxic horizon 18 is formed, cover the dielectric layer 20 of described grid oxic horizon 18 and polysilicon gate 19, and with described P type base 16 and described N-type emitter region 17 front metal electrode 21 (i.e. emitter E) in electrical contact.
Just schematically illustrate front metal electrode 21 in Fig. 6, in fact, front metal electrode 21 may cover whole dielectric layer 20.In addition, the Facad structure of described IGBT also may comprise the passivation layer (not shown) be formed at outside front metal electrode 21, such as silicon dioxide and silicon nitride.
In other embodiments, can manufacture groove-shaped IGBT, the described Facad structure of groove-shaped IGBT is not identical with the Facad structure of the IGBT in Fig. 6, but has disclosed a lot of groove-shaped IGBT in prior art yet, here just no longer repeated description.Need to know, from certain angle of the present invention, the present invention is not concerned about the concrete Facad structure of IGBT especially, as long as have Facad structure and can form operable IGBT device.
From another angle, about the concrete manufacturing process of the Facad structure of IGBT does not belong to emphasis of the present invention yet, it can adopt existing various manufacturing process manufacture to form, therefore in order to outstanding emphasis of the present invention, about the concrete manufacturing process of the Facad structure of IGBT is not described in detail in this article.
Step 160, shown in composition graphs 7, starts thinning described substrate 22 until expose described passage 14 from the second surface of described substrate 10, and the substrate 22 after thinning is arranged with described passage 14 interleaved.
When described substrate 10 is P type, the substrate 22 after thinning forms P type collector area, described N-type passage 14 formation type N-type cathodic region; When described substrate 10 is N-type, described passage 14 forms P type collector area, and the N-type substrate 22 after thinning forms N-type cathodic region.Described N-type cathodic region, N-type drift region 15 and P type base 16 form PIN type (positive intrinsic negative diode) backward diode jointly, and the IGBT in the present invention also can be called as the IGBT of reverse-conducting.
Concrete, can carry out thinning to described substrate 10 by grinding (Grinding) technique.
Step 170, shown in composition graphs 8, described passage 14 and thinning after substrate 22 outside by adopting the mode of sputtering or evaporation to obtain back metal electrode (collector electrode C) 23, this back metal electrode 23 and described passage 14 and described thinning after substrate 22 in electrical contact.
What the those of ordinary skill in affiliated field should be understood that is, one of feature of the present invention or object are: first complete the spaced P type collector area at the back side of IGBT and the making of N-type passage, the Facad structure of IGBT is prepared afterwards on extension drift region 15, only need to do thinning and back face metalization step after Facad structure completes, like this particular/special requirement be there is no to thin slice negotiability, more do not need double-sided exposure machine equipment.
P type in above-described embodiment can be called as the first conduction type, and N-type can be called as the second conduction type.In other embodiments, the region (such as P base, P type collector area) of the involved all P types in above-described embodiment can change to N-type, the region (N-type drift region, N-type emitter region, N-type cathodic region) of all N-types can change to P type, now can think that the first conduction type is N-type, the second conduction type is P type.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (10)
1. a manufacture method of IGBT, is characterized in that, it comprises:
There is provided and there is the first conduction type of first surface and second surface or the substrate of the second conduction type;
The groove at interval is formed at the first surface of described substrate;
In described groove, fill the semi-conducting material of the second conduction type or the first conduction type to form passage, the conduction type of wherein said passage is different from the conduction type of described substrate;
On the first surface of described substrate, extension forms the drift region of the second conduction type;
The Facad structure of described IGBT is formed based on described drift region;
Start thinning described substrate until expose described passage from the second surface of described substrate, now described passage and thinning after substrate space staggered;
Described passage and thinning after substrate on form back metal electrode, this back metal electrode and described passage and thinning after substrate in electrical contact.
2. the manufacture method of IGBT according to claim 1, is characterized in that, the thickness of the substrate provided is 100-650um, and resistivity is 0.001 ~ 100 Ω * cm.
3. the manufacture method of IGBT according to claim 1, is characterized in that, the thickness of the drift region that extension is formed is 10 ~ 650um, and resistivity is 5 ~ 500 Ω * cm.
4. the manufacture method of IGBT according to claim 1, is characterized in that, the thickness of the drift region that the thickness of described substrate and described extension are formed and be the silicon wafer thickness that normally circulates.
5. the manufacture method of IGBT according to claim 1, is characterized in that, is formed the groove at interval by photoetching, etch process at the first surface at described substrate.
6. the manufacture method of IGBT according to claim 5, is characterized in that, the degree of depth of described groove is 0.5 ~ 50um.
7. the manufacture method of IGBT according to claim 5, it is characterized in that, after the semi-conducting material of filling second conduction type or the first conduction type, the semi-conducting material of filling is made to become monocrystalline silicon by high-temperature step, subsequently by the first surface of the smooth described substrate of CMP (Chemical Mechanical Polishing) process.
8. the manufacture method of IGBT according to claim 1, is characterized in that, the Facad structure of described IGBT comprises:
The base of the first conduction type that the upper surface of described drift region is selectively formed;
The emitter region of the second conduction type selectively formed in described base;
Be positioned at the gate oxide on the upper surface of described drift region;
The polysilicon gate that the upper surface of described grid oxic horizon is formed;
Cover the dielectric layer of described grid oxic horizon and polysilicon gate;
With described base and described emitter region front metal electrode in electrical contact.
9. the manufacture method of IGBT according to claim 8, is characterized in that, the Facad structure of described IGBT comprises:
Be formed at the passivation layer outside front metal electrode.
10., according to the manufacture method of the arbitrary described IGBT of claim 1-9, it is characterized in that, described first conduction type is P type, and described second conduction type is N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310281979.XA CN104282553A (en) | 2013-07-05 | 2013-07-05 | Method for manufacturing IGBT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310281979.XA CN104282553A (en) | 2013-07-05 | 2013-07-05 | Method for manufacturing IGBT |
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| Publication Number | Publication Date |
|---|---|
| CN104282553A true CN104282553A (en) | 2015-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310281979.XA Pending CN104282553A (en) | 2013-07-05 | 2013-07-05 | Method for manufacturing IGBT |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640186A (en) * | 2009-07-20 | 2010-02-03 | 无锡凤凰半导体科技有限公司 | Manufacturing method of isolated gate bipolar transistor integrated fast recovery diode |
| CN104241124A (en) * | 2013-06-24 | 2014-12-24 | 无锡华润上华半导体有限公司 | Manufacturing method of non punch through reverse conducting insulated gate bipolar transistor |
-
2013
- 2013-07-05 CN CN201310281979.XA patent/CN104282553A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640186A (en) * | 2009-07-20 | 2010-02-03 | 无锡凤凰半导体科技有限公司 | Manufacturing method of isolated gate bipolar transistor integrated fast recovery diode |
| CN104241124A (en) * | 2013-06-24 | 2014-12-24 | 无锡华润上华半导体有限公司 | Manufacturing method of non punch through reverse conducting insulated gate bipolar transistor |
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Application publication date: 20150114 |