CN1042775C - Method of using Ge for silicon/silicon link and preparing silicon components lining chip - Google Patents
Method of using Ge for silicon/silicon link and preparing silicon components lining chip Download PDFInfo
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- CN1042775C CN1042775C CN96108505A CN96108505A CN1042775C CN 1042775 C CN1042775 C CN 1042775C CN 96108505 A CN96108505 A CN 96108505A CN 96108505 A CN96108505 A CN 96108505A CN 1042775 C CN1042775 C CN 1042775C
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- silicon
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- germanium
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Abstract
The present invention relates to a method using germanium for silicon/silicon bonding and a prepared silicon device substrate slice thereof. The present invention is characterized in that a germanium layer is deposited on a silicon polishing slice; afterwards, two opposite germanium layers are arranged at the middle; N<->/N<+>, P<->/P<+>, P<->/N<+>, N<->/P<+>, N<->/P<->, N<+>/P<+> type silicon device substrate slices can be prepared by placing the germanium layers in a sintering furnace for bonding. The method can realize silicon/silicon bonding, a bonding region has no cavity, and the bonding rate can reach more than 95%. The prepared substrate slice bonding region does not have a pollution layer, a polycrystalline layer and an oxidizing layer. The bonding strength can reach a body silicon level. Thereby, the performance of the prepared silicon device can be largely enhanced.
Description
The invention belongs to the silicon device substrate slice of a kind of silicon/silicon bonding method and preparation thereof, particularly a kind ofly carry out the method for silicon/silicon bonding and the silicon device substrate slice of preparation thereof with germanium.
At present, particularly Japan, the U.S., Russia etc. all adopt hydrophilic method to carry out silicon/Si direct bonding making silicon device substrate slice both at home and abroad.In Electrochem.Soc.Vol.139.No.11.November1992The Electrochemicai Society.Inc and the 18th volume the 2nd phase " application of silicon direct bonding technology in the bipolar power device " article of publishing in " electronic device " magazine June nineteen ninety-five and " wafer bonding prepares the SOI substrate " article of the 19th the 1st phase of volume of March in 1996, all disclose and a kind ofly carried out silicon/silicon bonding with hydrophilic method and prepare the method for silicon device substrate slice.The substrate slice of this method preparation, its bonded layer exists polycrystal layer or Si
xO
yAnd absorption contamination layer, be easy to generate cavity and nonbonding district, cause the bonding rate low, interlayer is arranged, thereby influence the preparation of devices performance, therefore can not be at industrial large-scale promotion application.
One of purpose of the present invention provides a kind of method of carrying out silicon/silicon bonding with germanium.
Two of purpose of the present invention provides a kind of silicon device substrate slice that carries out silicon/silicon bonding preparation with germanium.
Purpose of the present invention can realize by following measure:
The skill step that goes up of carrying out silicon/silicon bonding with germanium is:
(1) cleans pending polished silicon slice;
(2) the clean polished silicon slice after will cleaning is put in the epitaxial furnace that feeds hydrogen, under normal pressure or negative pressure, catches up with gas to be warming up to 1100～1200 ℃;
(3) under said temperature, carry in halogen gas or the halide gas feeding stove with hydrogen, its flow is 1l/min, carries out the gas phase polishing, removes the silicon chip affected layer and stains a layer 1-10 μ m;
(4) will go up-state epitaxial furnace and catch up with gas to be cooled to 300～1000 ℃, the compound that carries germanium with hydrogen feeds in the stove, and it feeds 0.01l～2l/min the most, mix simultaneously, and the deposit germanium layer, deposition time is 0.5～30min, deposition thickness is 1～3000nm,
(5) epitaxial furnace slowly is cooled to room temperature, takes out silicon chip;
(6) with the above-mentioned silicon chip of handling well, two relative germanium layers were put into sintering furnace in the centre, 740～990 ℃ of following bondings 20～50 minutes;
(7) sintering furnace slowly is cooled to room temperature, takes out, promptly make the silicon device substrate slice that carries out silicon/silicon bonding with germanium.
In above-mentioned method of carrying out silicon/silicon bonding with germanium, in epitaxial furnace, feed the compound that can also feed boron or phosphorus in the germanium compound, boron-doping or phosphorus in deposit germanium, its doping content is 1 * 10
19～1 * 10
21/ cm
3, make it at P
+Or N
+Form germanium layer on the silicon chip.Also can utilize autodoping, make it at P
-Or N
-Form germanium layer on the silicon chip.
The upper and lower layer of silicon device substrate slice that carries out making behind silicon/silicon bonding with germanium is a silicon, and the intermediate layer is the SiGe bonded layer that High temperature diffusion forms, and bonded layer does not exist pollution layer, polycrystal layer and oxide layer.
When the deposit germanium layer, as boron-doping, its bonded layer is the germanium-silicon layer that is mixed with boron; As mix phosphorus, its bonded layer is the germanium-silicon layer that is mixed with phosphorus.
But the upper and lower layer silicon N of substrate slice
-/ N
+, P
-/ P
+, P
-/ N
+, N
-/ P
+, N
-/ P
-, N
+/ P
+
The present invention compared with prior art has following advantage:
The present invention has utilized the high performance characteristics of silicon germanium material, and the germanium atom radius is big, can reduce the mismatch defective to being doped with good atomic radius stress compensation effect in the silicon, improves characteristics such as perfection and germanium fusing point low (941 ℃), easy bonding.Thereby its bonding rate is improved greatly, can reach more than 95%; There is not SiO in substrate behind the bonding
2Interlayer; There are not damage and polycrystal layer; The purity of monocrystalline does not reduce; Fineness is good, and can guarantee the perfection of silicon chip, and does not go out the cavity.
The drawing of accompanying drawing is described as follows:
Fig. 1 is at P
+The P that forms behind the deposit germanium layer on the silicon chip
+Ge layer silicon chip sectional schematic diagram;
Fig. 2 is at N
-The N that forms behind the deposit germanium layer on the silicon chip
-Ge layer silicon chip sectional schematic diagram;
Fig. 3 is the N that makes with behind Fig. 1 and Fig. 2 wafer bonding
-/ P
+Type silicon device substrate slice sectional schematic diagram.
1 is P among the figure
+Silicon chip, the 2nd, Ge layer, the 3rd, N
-Silicon chip, the 4th, Ge layer, the 5th, SiGe bonded layer.
The invention will be further described with specific embodiment below:
Embodiment 1:
Carry out silicon/silicon bonding with germanium and prepare N
-/ P
+Type silicon device substrate slice.
(1) cleans pending P
+The type polished silicon slice;
(2) the clean polished silicon slice after will cleaning is put in the epitaxial furnace that feeds hydrogen, under normal pressure, catches up with gas to be warming up to 1150 ℃;
(3) under this temperature, carry HCl gas with hydrogen, feed in the stove, the flow of HCl is 1l/min, carries out gas phase polishing 10min, removes the silicon face damage and stains layer 9 μ m;
(4) catch up with gas to be cooled to 900 ℃, carry GeCl with hydrogen
4And carry B, feed in the stove GeCl
4The feeding amount be 0.02l/min, the doping content of B is 1 * 10
19/ cm
3, the deposit germanium layer, deposition time is 2min, deposition thickness is 2nm, at P
+Form the Ge layer on the silicon chip;
(5) stove slowly is cooled to room temperature, takes out silicon chip;
(6) by above-mentioned same method step, utilize autodoping, at N
-Form the Ge layer on the silicon chip;
(7) with the above-mentioned P that handles well
+Ge layer silicon chip and N
-Ge layer silicon chip germanium face was relative, is separated by with molybdenum sheet for every group, puts into sintering furnace, 960 ℃ of following bondings 50 minutes;
(8) slowly be cooled to room temperature with stove, take out, just make N
-/ P
+Type carries out the substrate slice of silicon/silicon bonding with germanium.
This substrate slice upper strata is N
-Type silicon, lower floor is P
+Type silicon, centre are the SiGe bonded layers that is mixed with boron.
Sampling detects: the bonding rate reaches 95%;
Bond strength 150Kg/cm
2
Bonding region does not exist pollution layer, polycrystal layer, oxide layer.
Embodiment 2:
Carry out silicon/silicon bonding with germanium and prepare N
-/ N
+The type substrate slice.
(1) cleans pending N
+The type polished silicon slice;
(2) the clean polished silicon slice after will cleaning is put in the epitaxial furnace that feeds hydrogen, under normal pressure, catches up with gas to be warming up to 100 ℃;
(3) under this temperature, carry HCl gas with hydrogen, feed in the stove, the flow of HCl is 1l/min, carries out gas phase polishing 10min, removes the silicon face damage and stains layer 10 μ m;
(4) catch up with gas to be cooled to 300 ℃, carry GeH with hydrogen
4And carry P, feed in the stove GeH
4The feeding amount be 1l/min, the doping content of P is 1 * 10
19/ cm
3, the deposit germanium layer, deposition time is 10min, deposition thickness is 300nm, at N
+Form the Ge layer on the silicon chip;
(5) stove slowly is cooled to room temperature, takes out silicon chip;
(6) step is as stated above utilized autodoping, at N
-Form the Ge layer on the silicon chip;
(7) with the above-mentioned N that handles well
+Ge layer silicon chip and N
-Ge layer silicon chip germanium face was relative, is separated by with molybdenum sheet for every group, puts into sintering furnace, 900 ℃ of following bondings 20 minutes;
(8) slowly be cooled to room temperature with stove, take out, just make N
-/ N
+Type carries out the substrate slice of silicon/silicon bonding with germanium.
This substrate slice upper strata is N
-Type silicon, lower floor is N
+Type silicon, centre are the SiGe bonded layers that is mixed with phosphorus.
Sampling detects: the bonding rate reaches 97%;
Bond strength 160Kg/cm
2
Bonding region does not exist pollution layer, polycrystal layer, oxide layer.
Embodiment 3:
Carry out silicon/silicon bonding with germanium and prepare P
+/ N
+The type substrate slice.
(1) cleans pending P
+The type polished silicon slice;
(2) the clean polished silicon slice after will cleaning is put in the epitaxial furnace that feeds hydrogen, under normal pressure, catches up with gas to be warming up to 1200 ℃;
(3) under this temperature, carry HBr gas with hydrogen, feed in the stove, the flow of HBr is 1l/min, carries out gas phase polishing 10min, removes the silicon face damage and stains layer 10 μ m;
(4) catch up with gas to be cooled to 1000 ℃, carry GeCl with hydrogen
4And carry B, feed in the stove GeCl
4The feeding amount be 0.2l/min, the doping content of B is 5～9 * 10
20/ cm
3, deposition time is 10min, deposit germanium layer thickness is 600nm, at P
+Form the Ge layer on the type silicon chip;
(5) stove slowly is cooled to room temperature, takes out silicon chip;
(6) step as stated above is at N
+Heavily doped P during the deposit germanium layer on the type silicon chip, doping content is 4～6 * 10
20/ cm
3, at N
+Form the Ge layer on the type silicon chip;
(7) with the above-mentioned P that handles well
+Ge layer silicon chip and N
+Ge layer silicon chip germanium face was relative, and every group separates with molybdenum sheet, puts into sintering furnace, 740 ℃ of following bondings 30 minutes;
(8) slowly be cooled to room temperature with stove, take out, just make P
+/ N
+Type carries out the substrate slice of silicon/silicon bonding with germanium.
This substrate slice upper strata is P
+Type silicon, lower floor is N
+Type silicon, centre are the SiGe bonded layers that is mixed with phosphorus and boron.
Sampling detects: the bonding rate reaches 96%;
Bond strength 170Kg/cm
2
Bonding region does not exist pollution layer, polycrystal layer, oxide layer.
Embodiment 4:
Carry out silicon/silicon bonding with germanium and prepare N
-/ P
-The type substrate slice.
(1) cleans pending P
-The type polished silicon slice;
(2) the clean polished silicon slice after will cleaning is put in the epitaxial furnace that feeds hydrogen, under normal pressure, catches up with gas to be warming up to 1200 ℃;
(3) under this temperature, carry Br gas with hydrogen and feed in the stove, the flow of Br is 1l/min, carries out gas phase polishing 2min, removes the silicon face damage and stains layer 1 μ m;
(4) stove is cooled to 800 ℃, carries GeCl with hydrogen
4In the feeding stove, GeCl
4The feeding amount be 2l/min, utilize autodoping, the deposit germanium layer, deposition time is 30min, deposit germanium layer thickness 3000nm is at N
-Form the Ge layer on the type silicon chip;
(5) stove slowly is cooled to room temperature, takes out silicon chip;
(6) with the above-mentioned N that handles well
-Ge layer silicon chip and P
-Type silicon chip germanium face and silicon chip were positive relative, and every group separates with molybdenum sheet, puts into sintering furnace, 990 ℃ of following bondings 50 minutes;
(7) slowly be cooled to room temperature with stove, take out, just make N
-/ P
-Type carries out the substrate slice of silicon/silicon bonding with germanium.
This substrate slice upper strata is N
-Type silicon, lower floor is P
-Type silicon, centre are the SiGe bonded layers.
Sampling detects: the bonding rate reaches 95%;
Bond strength 150Kg/cm
2
Bonding region does not exist pollution layer, polycrystal layer, oxide layer.
Claims (7)
1, the method for a kind of silicon/silicon bonding is characterized in that: carry out silicon/silicon bonding with germanium, its processing step is:
(1) cleans pending polished silicon slice;
(2) the clean polished silicon slice after will cleaning is put in the epitaxial furnace that feeds hydrogen, under normal pressure or negative pressure, catches up with gas to be warming up to 1100～1200 ℃;
(3) under said temperature, bring halogen gas or halide gas into hydrogen, its flow is 1l/min, carries out the gas phase polishing, removes the silicon chip affected layer and stains layer 1-10 μ m;
(4) above-mentioned epitaxial furnace is caught up with gas be cooled to 300～1000 ℃, the compound that carries germanium with hydrogen feeds in the stove, and its feeding amount is 0.01l～2l/min, mix simultaneously, and the deposit germanium layer, deposition time is 0.5～30min, deposition thickness is 1～3000nm;
(5) epitaxial furnace slowly is cooled to room temperature, takes out silicon chip;
(6) with the above-mentioned silicon chip of handling well, two relative germanium layers were put into sintering furnace in the centre, 740～990 ℃ of following bondings 20～50 minutes;
(7) sintering furnace slowly is cooled to room temperature, takes out, promptly make the silicon device substrate slice that carries out silicon/silicon bonding with germanium.
2, according to the method for the said silicon of claim 1/silicon bonding, it is characterized in that: in epitaxial furnace, feed the compound of boron or phosphorus in the feeding germanium compound, boron-doping or phosphorus in deposit germanium, its doping content is 1 * 10
19～1 * 10
21/ cm
3Thereby, make it at P
+Or N
+Form the germanium layer of boron-doping or phosphorus on the silicon chip.
3, according to the method for the said silicon of claim 1/silicon bonding, it is characterized in that: when the deposit germanium layer, utilize autodoping, make it at P
-Or N
-Form germanium layer on the silicon chip.
4, a kind of silicon device substrate slice that carries out silicon/silicon bonding preparation with germanium, the upper strata is a silicon, it is characterized in that: lower floor also is a silicon, and the intermediate layer is the bonded layer that contains SiGe, and bonded layer does not exist pollution layer, polycrystal layer and oxide layer.
5, according to the said silicon device substrate slice of claim 4, it is characterized in that: the upper and lower layer silicon of substrate slice, but N
-/ N
+, P
-/ P
+, P
-/ N
+, N
-/ P
+, N
-/ P
-, N
+/ P
+
6, according to claim 4 or 5 said silicon device substrate slices, it is characterized in that: bonded layer is the germanium-silicon layer of boron-doping.
7, according to claim 4 or 5 said silicon device substrate slices, it is characterized in that: bonded layer is a germanium-silicon layer of mixing phosphorus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96108505A CN1042775C (en) | 1996-06-21 | 1996-06-21 | Method of using Ge for silicon/silicon link and preparing silicon components lining chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96108505A CN1042775C (en) | 1996-06-21 | 1996-06-21 | Method of using Ge for silicon/silicon link and preparing silicon components lining chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1145529A CN1145529A (en) | 1997-03-19 |
| CN1042775C true CN1042775C (en) | 1999-03-31 |
Family
ID=5119984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96108505A Expired - Fee Related CN1042775C (en) | 1996-06-21 | 1996-06-21 | Method of using Ge for silicon/silicon link and preparing silicon components lining chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1042775C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100481319C (en) * | 2004-07-30 | 2009-04-22 | 飞思卡尔半导体公司 | Interfacial layer for use with high K dielectric materials |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104362117B (en) * | 2014-11-24 | 2018-04-20 | 苏州晶方半导体科技股份有限公司 | Substrate bonding apparatus and bonding method |
| CN115483091A (en) * | 2022-09-23 | 2022-12-16 | 闽南师范大学 | Method for realizing low-temperature Si-Ge and Si-InP bonding by utilizing microcrystalline germanium film |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04351019A (en) * | 1990-09-20 | 1992-12-04 | Ampex Corp | Device concealing digital data signal |
-
1996
- 1996-06-21 CN CN96108505A patent/CN1042775C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04351019A (en) * | 1990-09-20 | 1992-12-04 | Ampex Corp | Device concealing digital data signal |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100481319C (en) * | 2004-07-30 | 2009-04-22 | 飞思卡尔半导体公司 | Interfacial layer for use with high K dielectric materials |
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| Publication number | Publication date |
|---|---|
| CN1145529A (en) | 1997-03-19 |
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