CN104268113A - LCD (Liquid Crystal Display) controller of DPI interface and bandwidth automatic adaption method thereof - Google Patents
LCD (Liquid Crystal Display) controller of DPI interface and bandwidth automatic adaption method thereof Download PDFInfo
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- CN104268113A CN104268113A CN201410490580.7A CN201410490580A CN104268113A CN 104268113 A CN104268113 A CN 104268113A CN 201410490580 A CN201410490580 A CN 201410490580A CN 104268113 A CN104268113 A CN 104268113A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3618—Control of matrices with row and column drivers with automatic refresh of the display panel using sense/write circuits
Abstract
The invention provides an LCD (Liquid Crystal Display) controller of a DPI interface and a bandwidth automatic adaption method thereof. The automatic adaption and adjustment is implemented through a row cache and cache control unit structure when the access bandwidth provided by the LCD controller for a storage changes. The refreshing operation can be performed through adjacent last row pixel data which are stored in the row cache when system storage equipment cannot met the access bandwidth requirements of the LCD controller and accordingly the access request number of the system storage equipment is reduced, the data correlation between the adjacent row and the same column pixels of a display image is utilized, and the macroblocking produced in the image display of an LCD screen is effectively reduced.
Description
Technical field
The invention belongs to lcd controller technical field, especially relate to a kind of lcd controller of DPI interface and the method for its adaptive bandwidth.
Background technology
Along with SoC chip becomes the main control chip of embedded system gradually, the man-machine interaction standard of embedded product also progressively improves, and the application of LCD display in embedded product of large image size and high definition is more and more extensive.LCD display because of DPI interface has very large cost advantage, and in the LCD display that embedded product uses, the LCD display of DPI interface has occupied very large ratio.
The display data of pixel each in one two field picture are passed through DPI interface according to frame by the lcd controller of SoC chip, and OK, the sequential of pixel is sequentially sent to LCD display line by line, and this operation is called " refreshing ".The LCD display of DPI interface generally can not the display data of buffer memory input, therefore " refreshing " operation of lcd controller will be carried out always, lcd controller constantly will take system bus, from system memory devices, obtain the display data of each pixel, namely lcd controller will take the access bandwidth of certain system memory devices.
Along with the increase of the display picture size of the LCD display of DPI interface, the access bandwidth that lcd controller needs also progressively increases.The scale of embedded system and the increase of complicacy, also make increasing equipment need the high bandwidth support of memory device, and system bandwidth has become a bottleneck of development of embedded system.Within certain time period, because memory device is by the hold facility of a high bandwidth requirements, result in lcd controller when accessing storage device, can not be responded in time.On the one hand, lcd controller can not obtain pixel data in time, causes can not normally completing the refresh operation of LCD display, makes LCD display occur serious problems such as " flower screens ".On the other hand, when memory device recovers the request of access of response lcd controller, the data first returned can't be used, because the pixel of corresponding appearance " flower screen " phenomenon of these data completes refresh operation.And the data of new non-refreshing pixels need to wait for that lcd controller sends new request of access, this results in when memory device recovers to provide the access bandwidth of lcd controller demand, lcd controller does not send effective request of access in time.In current lcd controller design, generally all improve the priority of lcd controller accessing storage device, make the request of access of memory device always preferential answering lcd controller.Even if but like this, still can not guarantee that each request of access of lcd controller can be responded in time, and the raising of the access privileges of lcd controller can cause larger impact to system, some visual plants such as processor can strengthen the access delay of memory device.In order to solve the problem, the mode dynamically arranging access privileges is have employed in some designs, namely according to the monitor message of bandwidth, by the priority of processor dynamic-configuration lcd controller accessing storage device, do and bring the software resource expense of processor collocating LCD controller like this and realize the hardware resource cost of monitoring bandwidth.Some designs also distribute special pixel data memory device for lcd controller, to guarantee that the request of access of lcd controller can be responded in time.But refresh large-scale LCD and manifest the jumbo special purpose memory devices of screen needs, so just bring significantly improving of cost, the market competitiveness of embedded product is had a great impact.
Summary of the invention
The problem to be solved in the present invention is to provide and is a kind ofly applied to the lcd controller of DPI interface and the method for its adaptive bandwidth, is particularly useful for the situation that storage device access bandwidth that lcd controller obtains can not satisfy the demands always.
For solving the problems of the technologies described above, the technical solution used in the present invention be a kind of can the lcd controller of DPI interface of adaptive bandwidth, comprise system bus interface, processor interface, row cache (Line Buffer), caching control unit (Buffer Control Unit), post processing of image unit and DPI interface;
Described system bus interface receives the read data request of caching control unit (Buffer Control Unit), be converted to system bus sequential and initiate read request to memory device, receive the read data that memory device returns and output to caching control unit (Buffer Control Unit);
Described processor interface is used for the running parameter of collocating LCD controller;
Further, described running parameter comprises: the dimensional parameters that the processor in system is shielded by processor interface collocating LCD; Refresh time sequence parameter; For caching control unit (Buffer Control Unit) configures frame start address (Frame Start Address), row number of pixels, write pointer jump (wrp_inc_value) operating parameter; Read dummy status frequency threshold value (empty_count_threshold) parameter; Post processing of image cell operation parameter;
Described row cache (Line Buffer) is for the pixel display data (Pixel Data) of the every one-row pixels of buffer memory LCD display;
Described caching control unit (Buffer Control Unit) is for the write of control lines buffer memory (Line Buffer) and reading;
The pixel data that described post processing of image unit reads from row cache (Line Buffer) for receiving caching control unit (Buffer Control Unit), carries out the post-processing operation of image;
Described DPI interface, for receiving the pixel data of post processing of image, is sent to LCD screen according to DPI sequential.
Further, described caching control unit (Buffer Control Unit) by bus read request control module, write buffer control module, error counter, pointer comparison module, read buffer control module and configurable register forms;
Described bus read request control module, for generation of read request, is converted to the read request of the accessing storage device meeting system bus protocol through system bus interface, the return data obtained mails to writes buffer control module;
Described buffer control module of writing writes to row cache (Line Buffer) for the pixel data (Pixel Data) bus read request control module returned;
Described buffer control module of reading, for reading pixel display data (Pixel Data) from row cache (Line Buffer), outputs to image processor block;
Described pointer comparison module, for comparing the write pointer (wrt_pointer) writing buffer control module and the read pointer (rd_pointer) reading buffer control module, produces row cache (Line Buffer) and reads dummy status (Buffer Empty) and write full state (Buffer Full) signal;
Described error counter is used for the number of times (Empty Cnt) occurring when being recorded in a line refresh operation reading dummy status (Buffer Empty);
Described configurable register is used for the parameter that storage comprises frame first address (Frame Start Address), jump numerical value (wrp_inc_value), threshold value (empty_count_threshold).
Present invention also offers a kind of method of lcd controller adaptive bandwidth of DPI interface, comprise the following steps:
Step 300: caching control unit (Buffer Control Unit) waits frame synchronizing signal; After receiving frame synchronizing signal (Vsync), read request address becomes frame first address (Frame Start Address);
Step 301: caching control unit (Buffer Control Unit) waits line synchronizing signal; After receiving line synchronizing signal (Hsync), by row cache (Line Buffer) write pointer (wrt_pointer) clear 0, read pointer (rd_pointer) clear 0; Caching control unit (Buffer Control Unit) carries out refresh operation, carries out step 302 and step 304 simultaneously;
Step 302: caching control unit (Buffer Control Unit) sends read request, returns the pixel display data (Pixel Data) of pixel from memory device;
Step 303: pixel display data (Pixel Data) the writing line buffer memory (Line Buffer) that caching control unit (Buffer Control Unit) will return, upgrades write pointer (wrt_pointer);
Step 304: caching control unit (Buffer Control Unit) waits pixel synchronizing signal (Pixel_En), after receiving pixel synchronizing signal (Pixel_En), enters step 305;
Step 305: the pixel display data (Pixel Data) of caching control unit (Buffer Control Unit) read pixel from row cache (Line Buffer), upgrades read pointer (rd_pointer);
Step 306: if caching control unit (Buffer Control Unit) is in refresh operation, row cache (Line Buffer) there occurs writes full state (Buffer Full), then return step 305, data are read, until it is invalid to write full state (Buffer Full) in row cache (Line Buffer); If row cache (Line Buffer) does not have to write full state (Buffer Full), then enter step 307;
Step 307: if caching control unit (Buffer Control Unit) in refresh operation row cache (Line Buffer) state for reading dummy status (Buffer Empty), enter step 310, otherwise enter step 308;
Step 308: if caching control unit (Buffer Control Unit) has completed the refresh operation of one-row pixels, enter step 309; Otherwise return step 302 and step 304;
Step 309: if completed the pixel refresh operation of a two field picture, return step 300, waited for new frame synchronizing signal; Otherwise return step 301, wait for new line synchronizing signal;
Step 310: row cache (Line Buffer) state is for after reading dummy status (Buffer Empty), and error counter number of times (Empty Cnt) adds 1;
Step 311: error counter number of times (Empty Cnt), if exceed threshold value (empty_count_threshold), enters step 313; If do not exceed threshold value, enter step 312;
Step 312: write pointer (wrt_pointer) increases jump numerical value (wrp_inc_value), skips jump numerical value (wrp_inc_value) individual pixel; Pixel display data (Pixel Data) for the pixel do not returned no longer obtains from memory device, but uses the pixel display data (Pixel Data) of the respective pixel of the adjacent lastrow stored in row cache (Line Buffer); Continue refresh operation, namely return step 302 and step 304;
Step 313: write pointer (wrt_pointer) clear 0; Current line remains updated pixel and all no longer obtains from memory device, but uses the pixel data of the adjacent lastrow stored in row cache (Line Buffer); After completing residual pixel refresh operation, return step 309;
Further, described row cache (Line Buffer) adopts the first-in first-out that the pixel display data of first writing line buffer memory (Line Buffer) (Pixel Data) first reads in refresh operation;
Further, the degree of depth of described row cache (Line Buffer) is greater than the display data of the one-row pixels of the full-size LCD screen that lcd controller is supported;
Further, the pixel display data (Pixel Data) writing described row cache (Line Buffer) writes from row cache (Line Buffer) address 0, and each pixel takies an address location of row cache (Line Buffer);
Further, the pixel of a two field picture same column different rows takies identical address location in described row cache (Line Buffer).
The advantage that the present invention has and good effect are: when system memory devices can not meet the access bandwidth demand of lcd controller, refresh operation can be carried out by using the data of the adjacent lastrow pixel stored in row cache (Line Buffer), thus the request of access number of times decreased system memory devices, and the data dependence that make use of between adjacent lines same column pixel, effectively reduces the generation of " flower screen " phenomenon.
Accompanying drawing explanation
Fig. 1 is the theory diagram of the lcd controller of DPI interface of the present invention;
Fig. 2 is the theory diagram of the specific embodiment of the invention;
Fig. 3 is the workflow diagram of lcd controller adaptive bandwidth of the present invention design.
Embodiment
As shown in Figure 1, the invention provides a kind of can the lcd controller 100 of DPI interface of adaptive bandwidth, comprise system bus interface 101, processor interface 102, row cache (Line Buffer) 103, caching control unit (Buffer Control Unit) 104, post processing of image unit 105 and DPI interface 106;
Described system bus interface 101 receives the read data request of caching control unit (Buffer Control Unit) 104, be converted to system bus sequential and initiate read request to memory device, receive the read data that memory device returns and output to caching control unit (Buffer Control Unit) 104;
Processor interface 102 is for the running parameter of collocating LCD controller; Described running parameter comprises: the dimensional parameters that the processor in system is shielded by processor interface collocating LCD; Refresh time sequence parameter; For caching control unit (Buffer Control Unit) configures frame start address (Frame Start Address), row number of pixels, write pointer jump (wrp_inc_value) operating parameter; Read dummy status frequency threshold value (empty_count_threshold) parameter; Post processing of image cell operation parameter;
Described row cache (Line Buffer) 103 is for the pixel display data (Pixel Data) of the every one-row pixels of buffer memory LCD display;
Caching control unit (Buffer Control Unit) 104 is for the write of control lines buffer memory (Line Buffer) 103 and reading; Row cache (Line Buffer) 103 and caching control unit (Buffer Control Unit) 104 achieve the adaptation function of lcd controller to bandwidth;
Described post processing of image unit 105 connects the pixel data that caching control unit (Buffer Control Unit) 104 reads from row cache (Line Buffer) 103, carries out the post-processing operation of image.
DPI interface 106, for receiving the pixel data of post processing of image, is sent to LCD screen according to DPI sequential.
Fig. 2 is a kind of embodiment of adaptive bandwidth design in the lcd controller shown in Fig. 1.Caching control unit (Buffer Control Unit) 200 by bus read request control module 201, write buffer control module 202, error counter 203, pointer comparison module 204, read buffer control module 205 and configurable register 206 forms;
Described bus read request control module 201, for generation of read request, is converted to the read request of the accessing storage device meeting system bus protocol through system bus interface, the return data obtained mails to writes buffer control module 202; Write buffer control module 202 to write to row cache (Line Buffer) for the pixel display data (Pixel Data) that bus read request control module 201 is returned, reading buffer control module 205 for reading pixel display data (Pixel Data) from row cache (Line Buffer), outputting to image processor block; Pointer comparison module 204 is write the write pointer (wrt_pointer) of buffer control module 202 and is read the read pointer (rd_pointer) of buffer control module 205 for comparing, produce reading dummy status (Buffer Empty) and writing full state (Buffer Full) signal of row cache (Line Buffer);
The number of times (Empty Cnt) reading dummy status (Buffer Empty) is there is when error counter 203 is for being recorded in a line refresh operation;
Configurable register 206 store operational parameters, comprises frame first address (Frame Start Address), jump numerical value (wrp_inc_value), threshold value (empty_count_threshold);
System processor configures these parameters by processor interface before refresh operation starts.
When starting refresh operation, bus read request control module 201 receives the frame synchronizing signal (Vsync) of DPI interface, and reference address is set to frame first address (Frame Start Address); Bus read request control module 201 sends read request, is converted to the read request of access system memory device through system bus interface after receiving the line synchronizing signal (Hsync) of DPI interface.The read request data returned output to writes buffer control module 202.Bus read request control module 201 can continue to send out read request, and according to the number of pixels that the last time asks the packet returned to contain, increases the address of read request.When bus read request control module 201 receive pointer comparison module 204 write full state (Buffer Full) signal after, can stop sending read request, until write full state (Buffer Full) invalidating signal.After the pixel display data (Pixel Data) of one-row pixels all returns, bus read request control module 201 stops sending read request.Until after receiving the line synchronizing signal (Hsync) of the next line of DPI interface, bus read request control module 201 sends new read request.When the number of times (Empty Cnt) of error counter 203 changes, namely there occurs and read dummy status (Buffer Empty), the memory address length that the start address that bus read request control module 201 sends new read request will increase shared by jump numerical value (wrp_inc_value) individual pixel.When number of times (Empty Cnt) exceedes threshold value (empty_count_threshold), bus read request control module 201 stops sending read request, until receive the new line synchronizing signal of DPI interface (Hsync).
Write after buffer control module 202 receives the pixel display data (Pixel Data) of bus read request control module 201, writing line buffer memory (Line Buffer).Often write a pixel data to row cache (Line Buffer), write pointer (wrt_pointer) just increases by 1.After often receiving the line synchronizing signal (Hsync) of DPI interface, write pointer (wrt_pointer) is with regard to clear 0.Write buffer control module 202 and write pointer (wrt_pointer) is outputted to pointer comparison module 204.When the number of times (Empty Cnt) of error counter 203 changes, namely row cache (Line Buffer) state is for reading dummy status (BufferEmpty), write pointer (wrt_pointer) skips jump numerical value (wrp_inc_value) individual pixel, namely increases jump numerical value (wrp_inc_value).When number of times (Empty Cnt) exceedes threshold value (empty_count_threshold), write pointer (wrt_pointer) is by clear 0.After receiving line synchronizing signal (Hsync) signal of DPI interface, write pointer (wrt_pointer) is by clear 0.
Read buffer control module 205 after receiving the pixel synchronizing signal (Pixel_En) of DPI interface, from row cache (Line Buffer), the pixel display data (Pixel Data) of read pixel, outputs to post processing of image unit.Often read a pixel, read pointer (rd_pointer) just increases by 1.After receiving the line synchronizing signal (Hsync) of DPI interface, read pointer (rd_pointer) is by clear 0.
Fig. 3 describes the workflow of adaptive bandwidth of the present invention:
Step 300: caching control unit (Buffer Control Unit) waits frame synchronizing signal.After receiving new number of frame synchronization (Vsync), read request address becomes frame first address (Frame Start Address);
Step 301: caching control unit (Buffer Control Unit) waits line synchronizing signal.After receiving line synchronizing signal (Hsync), by row cache (Line Buffer) write pointer (wrt_pointer) clear 0, read pointer (rd_pointer) clear 0.Caching control unit (Buffer Control Unit) carries out refresh operation, carries out step 302 and step 304 simultaneously;
Step 302: caching control unit (Buffer Control Unit) sends read request, returns the pixel display data (Pixel Data) of pixel from memory device;
Step 303: pixel display data (Pixel Data) the writing line buffer memory (Line Buffer) that caching control unit (Buffer Control Unit) will return, upgrades write pointer (wrt_pointer);
Step 304: caching control unit (Buffer Control Unit) waits pixel synchronizing signal (Pixel_En), after receiving pixel synchronizing signal (Pixel_En), enters step 305;
Step 305: the pixel display data (Pixel Data) of caching control unit (Buffer Control Unit) read pixel from row cache (Line Buffer), upgrades read pointer (rd_pointer);
Step 306: if caching control unit (Buffer Control Unit) is in refresh operation, row cache (Line Buffer) there occurs writes full state (Buffer Full), then return step 305, data are read, until it is invalid to write full state (Buffer Full) from row cache (Line Buffer).If row cache (Line Buffer) does not have to write full state (Buffer Full), then enter step 307;
Step 307: if caching control unit (Buffer Control Unit) in refresh operation row cache (Line Buffer) state for reading dummy status (Buffer Empty), enter step 310, otherwise enter step 308;
Step 308: if caching control unit (Buffer Control Unit) has completed the refresh operation of one-row pixels, enter step 309.Otherwise proceed refresh operation, namely return step 302 and step 304;
Step 309: if completed the pixel refresh operation of a two field picture, return step 300, waited for new frame synchronizing signal; Otherwise return step 301, wait for new line synchronizing signal;
Step 310: row cache (Line Buffer) state is for after reading dummy status (Buffer Empty), and error counter number of times (Empty Cnt) adds 1;
If step 311:Empty Cnt exceedes threshold value (empty_count_threshold), enter step 313; If do not exceed threshold value, enter step 312;
Step 312: write pointer (wrt_pointer) increases jump numerical value (wrp_inc_value), namely skips jump numerical value (wrp_inc_value) individual pixel.The pixel display data (Pixel Data) of these pixels do not returned will no longer obtain from memory device, but uses the pixel display data (Pixel Data) of the respective pixel of the adjacent lastrow stored in row cache (Line Buffer).Continue refresh operation, namely return step 302 and step 304;
Step 313: write pointer (wrt_pointer) clear 0.One's own profession remains updated pixel and all no longer obtains from memory device, but uses the pixel data of the adjacent lastrow stored in row cache (Line Buffer).After completing residual pixel refresh operation, return step 309.
Can be found out by foregoing description, when memory device can not respond the request of access of lcd controller in time, caching control unit (Buffer Control Unit) reduces the request of access to memory device by write pointer (wrp_pointer) skip operation, reduces the bandwidth demand of self.When memory device can not respond the request of access of lcd controller in time, the number of times that write pointer (wrp_pointer) jumps is more, until skip the updated pixel of all residues of current refreshed rows.So decrease the access bandwidth demand to memory device, thus reach the automatic adaptation that lcd controller changes bandwidth.
It is emphasized that; embodiment of the present invention is illustrative; instead of it is determinate; therefore the present invention is not limited to the embodiment described in embodiment; every other embodiments drawn by those skilled in the art's technical scheme according to the present invention, belong to the scope of protection of the invention equally.
Claims (8)
- The lcd controller of 1.DPI interface, is characterized in that: comprise system bus interface, processor interface, row cache, caching control unit, post processing of image unit and DPI interface;Described system bus interface is for receiving the read data request of caching control unit;Described processor interface is used for the running parameter of collocating LCD controller;Described row cache is used for the pixel display data of the every one-row pixels of buffer memory LCD display;Described caching control unit is used for the data cached write of control lines and reading;The pixel data that described post processing of image unit reads from row cache for receiving caching control unit, carries out the post-processing operation of image;Described DPI interface is for receiving the pixel data of post processing of image.
- 2. the lcd controller of DPI interface according to claim 1, is characterized in that: described running parameter comprises: the dimensional parameters that the processor in system is shielded by processor interface collocating LCD; Refresh time sequence parameter; For caching control unit configuration frame start address, row number of pixels, write pointer skip operation parameter; Read dummy status frequency threshold parameter; Post processing of image cell operation parameter.
- 3. the lcd controller of DPI interface according to claim 1, is characterized in that: described caching control unit by bus read request control module, write buffer control module, error counter, pointer comparison module, read buffer control module and configurable register forms;Described bus read request control module is for generation of read request;Described buffer control module of writing writes to row cache for pixel data bus read request control module returned;Described buffer control module of reading, for reading pixel display data from row cache, outputs to image processor block;Described pointer comparison module, for comparing the write pointer writing buffer control module and the read pointer reading buffer control module, produces row cache and reads dummy status and write full status signal;The number of times reading dummy status is there is when described error counter is for being recorded in a line refresh operation;Described configurable register is used for stored parameter, comprising: comprise frame first address, jump numerical value, threshold value.
- The method of the lcd controller adaptive bandwidth of 4.DPI interface, comprises the following steps:Step 300: caching control unit waits frame synchronizing signal; After receiving frame synchronizing signal, read request address becomes frame first address;Step 301: caching control unit waits line synchronizing signal; After receiving line synchronizing signal, by clear for row cache write pointer 0, read pointer clear 0; Caching control unit carries out refresh operation, carries out step 302 and step 304 simultaneously;Step 302: caching control unit sends read request, returns the pixel display data of pixel from memory device;Step 303: the pixel display data writing line buffer memory that caching control unit will return, upgrades write pointer;Step 304: caching control unit waits pixel synchronizing signal; After receiving pixel synchronizing signal, enter step 305;Step 305: the pixel display data of caching control unit read pixel from row cache, upgrades read pointer;Step 306: if caching control unit is in refresh operation, row cache there occurs writes full state, returns step 305, reads data in row cache, until it is invalid to write full state; If row cache does not write full state, enter step 307;Step 307: if caching control unit row cache state in refresh operation, for reading dummy status, enters step 310, otherwise enter step 308;Step 308: if caching control unit has completed the refresh operation of one-row pixels, enter step 309; Otherwise return step 302 and step 304;Step 309: if complete the pixel refresh operation of a two field picture, return step 300, wait for new frame synchronizing signal; Otherwise return step 301, wait for new line synchronizing signal;Step 310: row cache state is for after reading dummy status, and error counter number of times adds 1;Step 311: if error counter number of times exceedes threshold value, enter step 313; If do not exceed threshold value, enter step 312;Step 312: write pointer increases jump numerical value of N, skips N number of pixel; Continue refresh operation, return step 302 and step 304;Step 313: write pointer clear 0; After completing residual pixel refresh operation, return step 309.
- 5. the method for the lcd controller adaptive bandwidth of DPI interface according to claim 4, is characterized in that: the first-in first-out that described row cache adopts the pixel display data of first writing line buffer memory first to read in refresh operation.
- 6. the method for the lcd controller adaptive bandwidth of DPI interface according to claim 4, is characterized in that: the degree of depth of described row cache is greater than the display data of the one-row pixels of the full-size LCD screen that lcd controller is supported.
- 7. the method for the lcd controller adaptive bandwidth of DPI interface according to claim 4, is characterized in that: the pixel display data writing described row cache writes from row cache address 0, and each pixel takies an address location of row cache.
- 8. the method for the lcd controller adaptive bandwidth of DPI interface according to claim 4, is characterized in that: the pixel of a two field picture same column different rows takies identical address location in described row cache.
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