CN104218942A - Anti-radiation latch employing four-input guard gate - Google Patents

Abstract

The invention relates to the field of design of anti-radiation integrated circuits, and provided a latch capable of being applied to a radiation environment. The latch can resist SEU (Single Event Upset) and some MBU (Multiple Bit Upset). The latch is characterized in that when a storage node and an input signal of the latch are subjected to double bit upset due to particle bombardment, the charge deposited on a sensitive node can be released through the guard gate, thus the storage state of the latch can be maintained, and an accurate level signal can be transmitted into a post-stage circuit. According to the technical scheme, the anti-radiation latch employing the four-input guard gate comprises seven transmission gates TG1-6, three phase inverters INV1-3, three double input guard gates (DIG) 1-3, and a four-input guard gate. The anti-radiation latch employing the four-input guard gate is mainly applied to the design of the anti-radiation integrated circuit.

Description

Apply the radioresistance latch of four input protection doors

Technical field

The present invention relates to radiation hardened integrated circuit design field; especially design is used two input protection doors and four input protection doors to reinforce sequence circuit; there is anti-single particle overturn (Single event upset; the ability of SEU) and partly resisting many bit reversals (Multiple-bit upset, MBU).Specifically, relate to the radioresistance latch of a kind of application four input protection doors.

Background technology

Application of integrated circuit is in the time of space field, can suffer particle bombardment to cause soft error, radiation mechanism in common space has the bombardment of α particle, high energy neutrons, high energy cosmic ray, low energy cosmic neutron, and these particles are beaten to silicon face and caused the transistor unnecessary electric charge of inner generation and wrong unlatching or shutoff.For the digital circuit being applied in space environment, particularly sequence circuit, the generation of single-particle inversion can have a strong impact on the correctness of chip functions.When the quantity of electric charge injecting is not enough to cause level upset and while causing the momentary pulse of level, single-ion transient state effect (Single Event Transient, SET) occurs.Existing reinforcement technique majority is for SEU, but along with the reducing and the decline of chip power supply voltage of integrated circuit size, MBU odds progressively rises, thereby affects the performance of circuit.

Latch is the most frequently used memory cell arriving in circuit, particularly important for the reinforcing of latch.Conventional design reinforcement method (Radiation Hardened-by Design, RHBD) has module redundancy and uses shutter.Module redundancy can increase circuit area and power consumption greatly, and shutter circuit can not.That conventional is two input protection doors (Double Input Guard_gate, DIG), can resist the SEU and the SET that occur in two inputs.This structure has also been applied four input protection doors (Four Input Guard_gate, FIG) in addition.

Summary of the invention

For overcoming the deficiencies in the prior art, the present invention aims to provide a kind of latch that can be applied under radiation environment, can resist SEU and part MBU.In the time there is dibit upset due to particle bombardment in the memory node of latch and input signal; this latch can be released and is deposited on the electric charge on sensitive nodes by shutter; thereby the store status of latch can not be changed, make correct level signal import late-class circuit into.For this reason, the technical solution used in the present invention is, apply the radioresistance latch of four input protection doors, by 7 transmission gate TG1～6, 3 inverter INV1～3, 3 two input protection doors (Double Input Guardgate, DIG) DIG1～3 and four input protection doors form, identical input signal Zhong San road, four tunnels respectively correspondence is input to input D1, D2, D3, input D1, D2, D3 is corresponding to transmission gate TG1 successively respectively, transmission gate T G2, transmission gate TG3 sends into two corresponding input protection door DIG1～3, input signal is through input D1, input D2 is as the input of two input protection door DIG1, the output A of two input protection door DIG1 is connected to input D1 through inverter INV1 and transmission gate TG5, input D2, input D3 are as the input of two input protection door DIG2, and the output B of two input protection door DIG2 is connected to input D2 via inverter INV2 and transmission gate TG6, input D1, input D3 are as the input of two input protection door DIG3, and the output C of two input protection door DIG3 is connected to input D3 through inverter INV3 and TG7, output A, B, C are as the input signal of four input protection doors, and beyond aforementioned three road input signals, four input protection doors output Q are inputted on Yi road.

Two input protection door DIG structures are, use two PMOS pipe PM1 and PM2 series connection, two NMOS pipe NM1 and NM2 series connection; The source class of PM1 meets VDD, and the drain electrode of PM2 connects the drain electrode of NM2, and the source class of NM1 meets GND, and the grid of PM1 and NM1 is as an input A, and the grid of PM2 and NM2 is inputted B as another, and the drain electrode of PM2 and NM2 is as output O.

The structure of four input protection doors is to use four PMOS pipe string connection, four NMOS pipe string connection; The source class of the 4th PMOS pipe meets VDD, the drain electrode of the 1st PMOS pipe connects the drain electrode of the 1st NMOS pipe, the source class of the 4th NMOS pipe meets GND, the grid of the 1st NMOS pipe and the 1st PMOS pipe connects respectively just anticlockwise, the grid of the 2nd NMOS pipe and the 2nd PMOS pipe is as an input, the grid of the 3rd NMOS pipe and the 3rd PMOS pipe is inputted as another, the grid of the 4th NMOS pipe and the 4th PMOS pipe is re-used as an input, and the drain electrode of the 1st NMOS pipe and the 1st PMOS pipe is as output O.

Technical characterstic of the present invention and effect:

The present invention reinforces circuit by the means of structural design, upset when therefore can resisting in the different traps that cause due to single radiating particle multiple sensitive nodes, thus the store status of latch can not be changed.

The present invention, owing to directly reaching Q by D when the transparent stage, has reduced propagation delay, and has been directly to drive Q by D, so the transistorized size of FIG can be used minimum dimension, has reduced chip area.

Brief description of the drawings

Fig. 1 applies the circuit structure of the radioresistance latch of four input protection doors;

The transistor level structure of Fig. 2 (a) DIG, (b) logical symbol of DIG, (c) sequential chart of DIG;

The transistor level structure of Fig. 3 (a) FIG, (b) logical symbol of FIG, (c) sequential chart of FIG.

Embodiment

The formation of latch of the present invention is used 7 transmission gate TG1～7,3 inverter INV1～3,3 two input protection door DIG1～3 and a FIG.The identical input signal in Ta You tetra-tunnels is respectively D1, D2, D3, D4, and they send into latch by switch TG1, TG2, TG3, TG4 separately.D1, D2 are as the input of DIG1, and the output A of DIG1 feeds back to its an input D1 through an inverter INV1 and switch TG5.Same D2, D3 are as the input of DIG2, and output B feeds back to D2 via INV2 and TG6.D1, D3 are as the input of DIG3, and output C feeds back to D3 through INV3 and TG7.A connects PM4 and the NM4 of FIG structure, and B connects PM3 and NM3, and C connects PM2 and NM2, and PM1 meets clock signal C K, and NM1 meets the anti-phase NCK of clock signal.Output is Q.DIG is wherein (as Fig. 2 (a) is depicted as its transistor level structure, (b) be its logical symbol, (c) be its sequential chart) use two PMOS and two NMOS series connection, PM1 and PM2 series connection, NM1 and NM2 connect, the source class of PM1 meets VDD, the drain electrode of PM2 connects the drain electrode of NM2, and the source class of NM1 meets GND, and the grid of PM1 and NM1 is as an input A, the grid of PM2 and NM2 is inputted B as another, and the drain electrode of PM2 and NM2 is as output O.DIG is output as high-impedance state in the time that two inputs are not identical.In the time that two input signals are identical, the function of this unit is consistent with the function of inverter.FIG is (as Fig. 3 (a) is depicted as its transistor level structure, (b) be its logical symbol, (c) be its sequential chart) similar with DIG, use four PMOS and four NMOS series connection, there are four inputs, in the time that four input signals are not identical, are output as high-impedance state.In the time that four input signals are identical, the function of this unit is consistent with the function of inverter.

Latch in the time of CK=1 in the transparent stage, TG1～4 conducting, TG5～7 cut-offs, FIG cut-off.The conducting of D4 branch road, input signal directly passes to Q.Latch is in the maintenance stage in the time of CK=0, and end TG1～4, TG5～7 conducting, and FIG conducting, the state of D1, D2, D3 passes to Q via DIG.May there is SEU and MBU in the maintenance stage, need to protect this.

Internal node has 7, keeps stage TG4 to disconnect, so whether D4 does not correctly affect Q.Remaining 6 nodes can be divided into 2 groups, are respectively node { D1, D2, D3} and { A, B, C}, also can classify by Component units, is divided into 3 branch roads { DIG1, INV1}, { DIG2, INV2}, { DIG3, INV3}.While there is SEU, can be divided into 2 classes, SEU occurs in respectively the first group node and the second group node.First analyze D2 and how A node shields SEU, other the first group node and D2 are similar, and the second group node and category-A are seemingly.When SEU occurs in D2, D2 is the input of DIG1 and DIG2, so these two DIG states are floating empty, output A and B and C remain unchanged within this clock cycle, shielding mistake, and latch output Q also just remains unchanged.When SEU occurs in node A, { DIG1, INV1} is floating empty, normal but B and C keep, so latch output Q remains unchanged for branch road.

In the time there is binode upset (Double-node Upset, DNU), have 15 kinds of combinations, can be divided three classes.We get three kinds of typical case and describe.In the time of D1 and D2 generation DNU, two inputs of DIG1 change simultaneously, and the state of A overturns, branch road DIG1, INV1} is floating empty, makes the state of D1 irrecoverable within this clock cycle by INV1, and the state of B is constant, the state of D2 is recovered by INV2, and the state of C is also constant.So there is a state A to change in three inputs of TIG, output Q remains unchanged.In the time that DNU occurs in D2 and A, the error level of A overturns D1 by INV1, two input signal D1 of DIG2 and all mistakes of D2, the upset so B also makes a mistake, branch road { DIG1, INV1} and { DIG2, INV2} is floating empty.But C is correct, so the output level of TIG is still correct.In the time that DNU occurs in A and B, the state of D1 and D2 is by INV1 and the INV2 upset that makes a mistake, branch road { DIG1, INV1} and { DIG2, INV2} is floating empty, but D3 and C are correct, so the output Q of TIG is still correct.If level upset is irresistible but output node Q makes a mistake.So the opposing probability of DNU is

Unit	PMOS/ minimum dimension	NMOS/ minimum dimension
			Switch	1	1
Inverter	2	1
			DIG	4	2
FIG	2	1

Table 1

This circuit transistorized breadth length ratio used is as shown in table 1.In circuit transmission gate transistor used adopt minimum dimension (in 180nm commercial standard (CS) cell library PMOS raceway groove minimum long and wide be respectively 220nm and 180nm, be breadth length ratio 180/220), the width of the P pipe of inverter is 2 times of minimum widith, ensures the consistent of rise time and fall time.DIG transistor size used is that 2 times of inverter drive intensity with guarantee, and TIG transistorized size used is identical with inverter, can reduce chip area.

Claims (3)

1. the radioresistance latch of application four input protection doors, it is characterized in that, by 7 transmission gate TG1～6, 3 inverter INV1～3, 3 two input protection doors (Double Input Guardgate, DIG) DIG1～3 and four input protection doors form, identical input signal Zhong San road, four tunnels respectively correspondence is input to input D1, D2, D3, input D1, D2, D3 is corresponding to transmission gate TG1 successively respectively, transmission gate T G2, transmission gate TG3 sends into two corresponding input protection door DIG1～3, input signal is through input D1, input D2 is as the input of two input protection door DIG1, the output A of two input protection door DIG1 is connected to input D1 through inverter INV1 and transmission gate TG5, input D2, input D3 are as the input of two input protection door DIG2, and the output B of two input protection door DIG2 is connected to input D2 via inverter INV2 and transmission gate TG6, input D1, input D3 are as the input of two input protection door DIG3, and the output C of two input protection door DIG3 is connected to input D3 through inverter INV3 and TG7, output A, B, C are as the input signal of four input protection doors, and beyond aforementioned three road input signals, four input protection doors output Q are inputted on Yi road.

2. the radioresistance latch of application four input protection doors as claimed in claim 1, is characterized in that, two input protection door DIG structures are, uses two PMOS pipe PM1 and PM2 series connection, two NMOS pipe NM1 and NM2 series connection; The source class of PM1 meets VDD, and the drain electrode of PM2 connects the drain electrode of NM2, and the source class of NM1 meets GND, and the grid of PM1 and NM1 is as an input A, and the grid of PM2 and NM2 is inputted B as another, and the drain electrode of PM2 and NM2 is as output O.

3. the radioresistance latch of application four input protection doors as claimed in claim 1, is characterized in that, the structure of four input protection doors is: use four PMOS pipe string connection, four NMOS pipe string connection; The source class of the 4th PMOS pipe meets VDD, the drain electrode of the 1st PMOS pipe connects the drain electrode of the 1st NMOS pipe, the source class of the 4th NMOS pipe meets GND, the grid of the 1st NMOS pipe and the 1st PMOS pipe connects respectively just anticlockwise, the grid of the 2nd NMOS pipe and the 2nd PMOS pipe is as an input, the grid of the 3rd NMOS pipe and the 3rd PMOS pipe is inputted as another, the grid of the 4th NMOS pipe and the 4th PMOS pipe is re-used as an input, and the drain electrode of the 1st NMOS pipe and the 1st PMOS pipe is as output O.