CN104218036A - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN104218036A CN104218036A CN201310218889.6A CN201310218889A CN104218036A CN 104218036 A CN104218036 A CN 104218036A CN 201310218889 A CN201310218889 A CN 201310218889A CN 104218036 A CN104218036 A CN 104218036A
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Abstract
The invention discloses a semiconductor device comprising a substrate, an insulating layer, a DRAM (dynamic random access memory) capacitor and an RRAM (resistive random access memory) storage unit. The substrate comprises a DRAM cell region and an RRAM cell region. The insulating layer is arranged on the substrate. The DRAM cell region is provided with a first opening; the RRAM cell region is provided with a second opening. The DRAM capacitor is arranged in the first opening of the insulating layer. The RRAM storage unit is arranged in the second opening of the insulating layer. A first electrode of the DRAM capacitor is larger than a second electrode of the RRAM storage unit. An RRAM and a DRAM can be made on a same chip and are equally high on the chip; an additional RRAM need not be made by a following interconnect process.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof of integrating resistive random access memory (RRAM) and dynamic random access memory (DRAM).
Background technology
Current memory can be divided into two large types.Wherein the memory of a type is called working storage, it can read fast and write and have good durability (endurance), and the memory of this type is for example static RAM (SRAM) and dynamic random access memory (DRAM).The memory of another kind of type has non-volatile characteristic, and the data that deposit in also can not disappear after power-off, and the memory element of this type is for example flash memories.For the application of high-density storage, be best selection with dynamic random access memory as operational store.But, because its technique is comparatively complicated, therefore by very high the cost of the technique of dynamic randon access memory and a chip of flash memories integration.
Resistive random access memory (resistive random access memory, RRAM) is next generation nonvolatile memory of one of current develop actively.Resistive random access memory is a kind of simple metal-insulator-metal (MIM) structure, can be incorporated into by two extra cover curtain steps the smithcraft of back segment.But the resistive random access memory that this mode forms, may be excessive because of the spacing of metal interconnecting, and the problem that causes memory cell size to increase, and can increase extra process costs.
Summary of the invention
The object of the invention is to propose a kind of semiconductor element, can resistive random access memory and dynamic random access memory be incorporated on single chip by simple technique.
The present invention proposes a kind of semiconductor element, can promote the switching characteristic that resistive random access memory and dynamic random access memory is incorporated into single the resistive random access memory on chip.
The present invention proposes a kind of manufacture method of semiconductor element, can integrate the technique of resistive random access memory and dynamic random access memory, and can not increase too much process costs.
The present invention proposes a kind of RRAM memory cell, and it has the size that is less than dynamic random access memory.
The present invention proposes a kind of manufacture method of RRAM memory cell, its can with the process integration of dynamic random access memory.
The present invention proposes a kind of semiconductor element, comprises substrate, insulating barrier, DRAM capacitor and RRAM memory cell.Substrate comprises DRAM cell region and RRAM cell region.Insulating barrier is positioned in substrate, has the first opening on DRAM cell region, and on RRAM cell region, has the second opening.DRAM capacitor is arranged in the first opening of the insulating barrier on DRAM cell region.RRAM memory cell is arranged in the second opening of the insulating barrier on RRAM cell region.The size of the first electrode of DRAM capacitor is greater than the size of the second electrode of RRAM memory cell.
The present invention proposes a kind of manufacture method of semiconductor element, comprises substrate is provided.Substrate comprises DRAM cell region and RRAM cell region.In substrate, form insulating barrier, cover DRAM cell region and RRAM cell region.In insulating barrier on above-mentioned DRAM cell region, form the first opening, and form the second opening in insulating barrier on RRAM cell region.Bottom and sidewall in the first opening form the first electrode.In the second opening, form the second electrode.The size of above-mentioned the second electrode is less than the size of the first electrode, and the second electrode covers bottom and the Part I sidewall of the second opening, the Part II sidewall of exposed the second opening.On the first electrode in the first opening of DRAM cell region and insulating barrier, form the first dielectric layer.On the second electrode of RRAM cell region and the Part II sidewall of the second opening and insulating barrier, form the second dielectric layer.On the first dielectric layer, form third electrode.On the second dielectric layer, form the 4th electrode.The first electrode, the first dielectric layer and third electrode composition DRAM capacitor, and the second electrode, the second dielectric layer and the 4th electrode composition RRAM memory cell.
Described in one embodiment of the invention, above-mentioned formation the first electrode is included in above-mentioned substrate and forms electrode material layer with the step that forms the second electrode, covers sidewall and the bottom of above-mentioned insulating barrier and above-mentioned the first opening and above-mentioned second opening of above-mentioned DRAM cell region and above-mentioned RRAM cell region.In above-mentioned substrate, form sacrifice layer, cover the above-mentioned electrode material layer of above-mentioned DRAM cell region and above-mentioned RRAM cell region, and fill up above-mentioned the first opening and above-mentioned the second opening.Remove above-mentioned sacrifice layer and above-mentioned electrode material layer on the above-mentioned insulating barrier of above-mentioned DRAM cell region and above-mentioned RRAM cell region, expose the surface of above-mentioned insulating barrier.In above-mentioned substrate, form cover curtain layer, cover above-mentioned DRAM cell region.Taking above-mentioned cover curtain layer as cover curtain, remove the partial sacrifice layer in above-mentioned the second opening, make the height of the above-mentioned sacrifice layer in above-mentioned the second opening lower than the height of the above-mentioned sacrifice layer in above-mentioned the first opening.Taking above-mentioned cover curtain layer and above-mentioned sacrifice layer as cover curtain, above-mentioned electrode material layer in above-mentioned the second opening of etch-back, the above-mentioned electrode material layer of staying in above-mentioned the second opening forms above-mentioned the second electrode, and the above-mentioned electrode material layer of staying in above-mentioned the first opening forms above-mentioned the first electrode.Remove above-mentioned cover curtain layer.Remove above-mentioned sacrifice layer, expose the above-mentioned Part II sidewall of above-mentioned the first electrode and above-mentioned the second electrode and above-mentioned the second opening.
Semiconductor element of the present invention and manufacture method are incorporated into resistive random access memory and dynamic random access memory on single chip.
Semiconductor element of the present invention, can promote the switching characteristic that resistive random access memory and dynamic random access memory is incorporated into single the resistive random access memory on chip.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Brief description of the drawings
Figure 1A to Fig. 1 E is the profile according to the manufacture method of a kind of semiconductor element of one embodiment of the invention.
Fig. 2 A to Fig. 2 F is the profile according to the manufacture method of a kind of semiconductor element of another embodiment of the present invention.
Wherein, description of reference numerals is as follows:
10: substrate
12:DRAM cell region
14:RRAM cell region
16,22: insulating barrier
18,20: connector
24,26: opening
26a, 26b: partial sidewall
28: electrode material layer
30,30a, 30b, 60: sacrifice layer
32,48,62,68: cover curtain layer
34,36,44,46: electrode
38,58,64: dielectric layer
54,74:DRAM capacitor
56,76:RRAM memory cell
66: metal level
Embodiment
The present invention dwindles the size of the hearth electrode of DRAM capacitor to make the hearth electrode of RRAM memory cell, and therefore, the present invention can be by the process integration of RRAM and DRAM, utilizes easy technique that RRAM and DRAM are produced on same chip.Below illustrate for two example two, so the present invention is not as limit.
Figure 1A to Fig. 1 E is the profile according to the manufacture method of a kind of semiconductor element of one embodiment of the invention.
Please refer to Figure 1A, substrate 10 is provided, this substrate 10 comprises DRAM cell region 12 and RRAM cell region 14.The material of substrate 10 can be semiconductor or semiconducting compound, for example, be silicon or germanium silicide.Substrate 10 can be also on insulating barrier, to have silicon (SOI).In substrate 10, can be to have formed various elements, for example, be MOS (metal-oxide-semiconductor) transistor, diode or electric capacity etc. (but not as limit), in graphic, these elements do not illustrated out.In substrate 10, form insulating barrier 16.The material of insulating barrier 16 is for example silicon nitride, and the method for formation is for example chemical vapour deposition technique, and thickness is for example 30nm to 60nm.Then, in the insulating barrier 16 of DRAM cell region 12, form connector 18, and form connector 20 in the insulating barrier 16 of RRAM cell region 14.Connector 18 can be electrically connected with another conductor layer of insulating barrier 16 belows respectively with connector 20.In one embodiment, described another conductor layer can be the doped region (not illustrating) in substrate 10.In another embodiment, described another conductor layer can be also polysilicon gate or the metal level (not illustrating) in substrate 100.Connector 18 is for example in the insulating barrier 16 of DRAM cell region 12 and RRAM cell region 14, to form plug open respectively with the formation method of connector 20, then form conductor layer (not illustrating), this conductor layer is covered on insulating barrier 16 and fills in plug open, removes the conductor layer on insulating barrier 16 more afterwards via chemical mechanical milling tech or etch back process.The material of conductor layer is for example tungsten or titanium oxide.,, in substrate 10, form insulating barrier 22 thereafter.The material of insulating barrier 22 is different from insulating barrier 16, for example, be silica, and the method for formation is for example chemical vapour deposition technique, and thickness is for example 1000nm to 1600nm.
Then, please refer to Figure 1B, utilize micro-shadow and etch process, in the insulating barrier 22 of DRAM cell region 12, form opening 24, and form opening 26 in the insulating barrier 22 of RRAM cell region 14.Opening 24 exposes connector 18; Opening 26 exposes connector 20.
Afterwards, in substrate 10, form electrode material layer 28.Electrode material layer 28 covers sidewall and the bottom of insulating barrier 22 and opening 24,26.The material of electrode material layer 28 is for example titanium nitride, and the method for formation is for example physical vaporous deposition (PVD), and thickness is for example 5nm to 10nm.,, in substrate 10, form sacrifice layer 30 thereafter.Sacrifice layer 30 covered by electrode material layers 28, and fill up opening 24 and opening 26.The material of sacrifice layer 30 is for example silica or boron doped silicon oxide, and the method for formation is for example rubbing method or chemical vapour deposition technique, and thickness is for example 100nm to 300nm.
, please refer to Fig. 1 C, remove sacrifice layer 30 and electrode material layer 28 on insulating barrier 22, expose the surface of insulating barrier 22 thereafter.The method removing can adopt chemical mechanical milling method to carry out planarization.To utilize chemical mechanical milling method but not etch-back method, the antenna effect (antenna effect) causing so can avoid the charge accumulation of etch-back method because this removes step.
Afterwards, please refer to Fig. 1 D, in substrate 10, form cover curtain layer 32.Cover curtain layer 32 covers DRAM cell region 12, exposes RRAM cell region 14.Cover curtain layer 32 is for example photoresist layer.Afterwards, remove the partial sacrifice layer 30 in the opening 26 on RRAM cell region 14, make to stay the height of the sacrifice layer 30b in opening 26 lower than the height of the sacrifice layer 30a in the opening 24 of DRAM cell region 12.Thereafter electrode material layer 28 in etch-back opening 26.Stay electrode material layer in opening 24 as electrode 34 (or being called hearth electrode), be electrically connected with connector 18; And stay electrode material layer on the partial sidewall 26a of opening 26 as electrode 36 (or being called hearth electrode), be electrically connected with connector 20.
Then, please refer to Fig. 1 E, remove cover curtain layer 32, then, remove the sacrifice layer 30a in DRAM cell region 12 openings 24, expose electrode 34, and remove the sacrifice layer 30b in the opening 26 of RRAM cell region 14, to expose the partial sidewall 26b of electrode 36 and opening 26.Afterwards, in substrate 10, form dielectric layer 38, cover DRAM cell region 12 and RRAM cell region 14.Dielectric layer 38 on DRAM cell region 12 covers the electrode 34 in insulating barrier 22 and opening 24.Dielectric layer 38 on RRAM cell region 14 covers electrode 36 in insulating barrier 22, opening 26 and the partial sidewall 26a of opening 26.The material of dielectric layer 38 can be variable-resistance material, for example, be silica or transition metal oxide (for example ZrO
2, HfO
2, Ta
2o
5, Al
2o
3or TiO
2, its formation method comprises carries out atomic layer deposition method (ALD), and thickness is for example 5nm to 20nm., on substrate 10 form electrode material layer, and utilize micro-shadow and etch process by its patterning, to form electrode 44 and electrode 46 (or being called top electrode) thereafter.Electrode material layer can adopt the stack layer of metal, metal nitride or its combination, for example, be titanium, titanium nitride or its stack layer (such as Ti/TiN), and its formation method comprises and carries out atomic layer deposition method, physical vaporous deposition or chemical vapour deposition technique.Electrode 44 is covered on the dielectric layer 38 of DRAM cell region 12; Electrode 46 is covered on the dielectric layer 38 of RRAM cell region 14.Electrode 34, dielectric layer 38 and electrode 44 on DRAM cell region 12 forms the capacitor 54 of DRAM.Electrode 36, dielectric layer 38 and electrode 46 on RRAM cell region 14 form RRAM memory cell 56.
Please refer to Fig. 1 E, the semiconductor element of the embodiment of the present invention comprises capacitor 54 and the RRAM memory cell 56 of substrate 10, insulating barrier 22, DRAM.Substrate 10 comprises DRAM cell region 12 and RRAM cell region 14.Insulating barrier 22 is positioned in substrate 10, has opening 24 on DRAM cell region 12.DRAM capacitor 54 is positioned on DRAM cell region 12, and it comprises electrode 34, dielectric layer 38 and electrode 44.Electrode 34 is positioned at bottom and the sidewall of opening 24.Dielectric layer 38 covers on the electrode 34 in opening 24, and extension is covered on insulating barrier 22.Electrode 44 is covered on dielectric layer 38.Insulating barrier 22 on RRAM cell region 14 has opening 26.RRAM memory cell 56 is positioned on RRAM cell region 14, and it comprises electrode 36, dielectric layer 38 and electrode 46.Electrode 36 is positioned at the bottom of opening 26, and extends the partial sidewall 26a that is covered to opening 26, the partial sidewall 26b of exposed opening 26.Dielectric layer 38 coated electrodes 36, and extension is covered on the partial sidewall 26b and insulating barrier 22 of opening 26.Electrode 46 is covered on dielectric layer 38.Because capacitor 54 and the RRAM memory cell 56 of DRAM are to be embedded among the different openings 24 and 26 of insulating barrier 22 of same layer, therefore, the bottom of the bottom of the electrode 36 of RRAM memory cell 56 and the electrode 34 of DRAM capacitor 54 is at roughly the same height; The electrode 46 of RRAM memory cell 56 also with the electrode 44 of DRAM capacitor 54 at roughly the same height, and wherein the size of the electrode 34 of DRAM capacitor 54 is greater than the electrode 36 of RRAM memory cell 56.
In above embodiment, the dielectric layer 38 of DRAM capacitor 54 is to make with identical material with the dielectric layer 38 of RRAM memory cell 56, but, the present invention must be as limit, in other embodiment, the transistorized dielectric layer of DRAM also can be made by different materials from the dielectric layer of RRAM memory cell, below illustrates for an embodiment, but the present invention is not as limit.
Fig. 2 A to Fig. 2 F is the profile according to the manufacture method of a kind of semiconductor element of another embodiment of the present invention.
Please refer to Fig. 2 A, according to the method for Figure 1A to Fig. 1 D, in substrate 10, form insulating barrier 16 and 22, connector 18 and 20, and in the opening 24 of insulating barrier 16, form electrode 34 and sacrifice layer 30a, in the opening 26 of insulating barrier 16, form electrode 36 and sacrifice layer 30b, and remove cover curtain layer 32 (as Fig. 1 D).Afterwards, on RRAM cell region 14, form cover curtain layer 48.Cover curtain layer 48 is for example photoresist layer.
Please refer to Fig. 2 A and 2B, taking cover curtain layer 48 as etch mask, etching removes the sacrifice layer 30a of the opening 26 being arranged on DRAM cell region 12, exposes the surface of electrode 34.,, remove cover curtain layer 48 thereafter.Then, in substrate 10, form dielectric layer 58, cover DRAM cell region 12 and RRAM cell region 14.Dielectric layer 58 is suitable for the dielectric layer as DRAM capacitor, and its material is for example ZrO2, and the method for formation is for example atomic layer deposition method, and thickness is for example 5nm to 20nm., on substrate 10 form another sacrifice layer 60, cover the dielectric layer 58 on DRAM cell region 12 and RRAM cell region 14 thereafter.The material of sacrifice layer 60 is for example silica or boron doped silicon oxide, and the method for formation is for example rubbing method or chemical vapour deposition technique, and thickness is for example 100nm to 300nm.Afterwards, in substrate 10, form cover curtain layer 62, cover the sacrifice layer 60 on DRAM cell region 12.Cover curtain layer 62 is for example photoresist layer.
Please refer to Fig. 2 C, taking cover curtain layer 62 as etch mask, etching removes sacrifice layer 60, dielectric layer 58 and the sacrifice layer 30b on RRAM cell region 14, exposes the electrode 36 in opening 26.
Afterwards, please refer to Fig. 2 D, remove cover curtain layer 62.Then, in substrate 10, form dielectric layer 64, the electrode 36 in partial sidewall 26b and the opening 26 of the sacrifice layer 60 on covering DRAM cell region 12 and the insulating barrier 22 on RRAM cell region 14 and opening 26.The material of dielectric layer 64 is different from dielectric layer 58.Dielectric layer 64 is suitable for the dielectric layer as RRAM memory cell.The material of dielectric layer 64 can be variable-resistance material, for example, be silica or transition metal oxide (for example ZrO2, HfO2, Ta2O5, Al2O3 or TiO2), and its formation method comprises and carry out atomic layer deposition method, and thickness is for example 5nm to 20nm.,, can selectivity in substrate 10, form metal level 66, to cover dielectric layer 64 thereafter.The material of metal level 66 is for example titanium, and its formation method comprises carries out atomic layer deposition method, and thickness is for example 5nm to 20nm.Afterwards, on RRAM cell region 14, form cover curtain layer 68.Cover curtain layer 68 is for example photoresist layer.
Thereafter, please refer to Fig. 2 E, taking cover curtain layer 68 as etch mask, etching removes metal level 66, dielectric layer 64 and the sacrifice layer 60 on DRAM cell region 12, exposes the dielectric layer 58 of DRAM cell region 12.
Afterwards, please refer to Fig. 2 F, remove cover curtain layer 68, expose the metal level 66 on RRAM cell region 14.Not forming in the embodiment of metal level 66,44, electrode is formed on dielectric layer 64.Again in the dielectric layer 58 of DRAM cell region 12 on form above-mentioned electrode 44, and form above-mentioned electrode 46 on metal level 66 on RRAM cell region 14 thereafter.Electrode 34, dielectric layer 58 and electrode 44 on DRAM cell region 12 forms the capacitor 74 of DRAM.Electrode 36, dielectric layer 64, metal level 66 and electrode 46 on RRAM cell region 14 form RRAM memory cell 76, and wherein the size of the electrode 34 of DRAM capacitor 74 is greater than the electrode 36 of RRAM memory cell 76.
In above embodiment, be the dielectric layer 58 that first forms the capacitor 74 of DRAM, and then the dielectric layer 64 and the metal level 66 that form RRAM memory cell 76 illustrate, but the present invention is not as limit.In other embodiment, can also first form dielectric layer 64 and the metal level 66 of RRAM memory cell 76, then form again the dielectric layer 58 of the capacitor 74 of DRAM.
Please refer to Fig. 2 F, the semiconductor element of the embodiment of the present invention comprises capacitor 74 and the RRAM memory cell 76 of substrate 10, insulating barrier 22, DRAM.Substrate 10 comprises DRAM cell region 12 and RRAM cell region 14.Insulating barrier 22 is positioned in substrate 10, in the insulating barrier 22 on DRAM cell region 12, has opening 24.DRAM capacitor 74, is positioned on DRAM cell region 12, and it comprises electrode 34, dielectric layer 58 and electrode 44.Electrode 34 is positioned at bottom and the sidewall of opening 24.Dielectric layer 58 covers on the electrode 34 in opening 24, and extension is covered on insulating barrier 22.Electrode 44 is covered on dielectric layer 58.In insulating barrier 22 on RRAM cell region 14, there is opening 26.RRAM memory cell 76, is positioned on RRAM cell region 14, and it comprises electrode 36, dielectric layer 64 and electrode 46.Electrode 36 is positioned at the bottom of opening 26, and extends the partial sidewall 26a that is covered to opening 26, the partial sidewall 26b of exposed opening 26.Dielectric layer 64 covers on electrode 36, and extension is covered on the partial sidewall 26b and insulating barrier 22 of opening 26.Electrode 46 is covered on dielectric layer 64.RRAM memory cell 76 also alternative comprises that metal level 66 is between dielectric layer 64 and electrode 46.Because capacitor 74 and the RRAM memory cell 76 of DRAM are to be embedded among the different openings 24 and 26 of insulating barrier 22 of same layer, therefore, the bottom of the bottom of the electrode 36 of RRAM memory cell 76 and the electrode 34 of DRAM capacitor 74 is at roughly the same height; The electrode 46 of RRAM memory cell 76 also with the electrode 44 of DRAM capacitor 74 at roughly the same height.In addition, in embodiments of the invention, DRAM selects different dielectric layers from RRAM, and can in the MIM capacitor of RRAM memory cell, increase metal level, therefore can be used to improve its switching characteristic (switching characteristics).
Comprehensive the above, the present invention integrates the technique of RRAM and DRAM, by the size of the hearth electrode of DRAM being dwindled to make the hearth electrode of RRAM memory cell, therefore, RRAM and DRAM can be produced on same chip, and the height on chip is roughly the same, do not need additionally to form again RRAM by follow-up metal interconnecting technique.In addition, the embodiment of the present invention, by the size of the hearth electrode of RRAM memory cell is dwindled, therefore can reduce the electric capacity of RRAM memory cell, and the resistance switching characteristic of lift element, makes RRAM be suitable for high speed operation.Moreover embodiments of the invention can also change the material of the dielectric layer of RRAM, or increase metal level in the MIM capacitor of RRAM memory cell, be used for improving its switching characteristic.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; technical staff in technical field under any; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim scope of the applying for a patent person of defining.
Claims (12)
1. a semiconductor element, is characterized in that comprising:
Substrate, described substrate comprises DRAM cell region and RRAM cell region;
Insulating barrier, is positioned in described substrate, on described DRAM cell region, has the first opening, and has the second opening on described RRAM cell region;
DRAM capacitor, is arranged in described first opening of the described insulating barrier on described DRAM cell region; And
RRAM memory cell, is arranged in described second opening of the described insulating barrier on described RRAM cell region,
The size of the first electrode of wherein said DRAM capacitor is greater than the size of the second electrode of described RRAM memory cell.
2. semiconductor element as claimed in claim 1, wherein
Described DRAM capacitor comprises:
Described the first electrode, is positioned at bottom and the sidewall of described the first opening;
The first dielectric layer, covers on described the first electrode in described the first opening, and extension is covered on described insulating barrier; And
Third electrode, is covered on described the first dielectric layer; And
Described RRAM memory cell comprises:
Described the second electrode, is positioned at the bottom of described the second opening, and extends the Part I sidewall that is covered to described the second opening, a Part II sidewall of exposed described the second opening;
The second dielectric layer, covers on described the second electrode, and extension is covered on the described Part II sidewall and described insulating barrier of described the second opening; And
The 4th electrode, is covered on described the second dielectric layer.
3. semiconductor element as claimed in claim 2, wherein said the first dielectric layer is identical with the material of described the second dielectric layer.
4. semiconductor element as claimed in claim 2, wherein said the first dielectric layer is different from the material of described the second dielectric layer.
5. semiconductor element as claimed in claim 4, the material of wherein said the second dielectric layer comprises variable-resistance material.
6. semiconductor element as claimed in claim 4, also comprises metal level, between described the second dielectric layer and described the 4th electrode.
7. a manufacture method for semiconductor element, is characterized in that comprising:
One substrate is provided, and described substrate comprises DRAM cell region and RRAM cell region;
In described substrate, form an insulating barrier, cover described DRAM cell region and described RRAM cell region;
In described insulating barrier on described DRAM cell region, form the first opening, and form the second opening in described insulating barrier on described RRAM cell region;
Bottom and sidewall in described the first opening form the first electrode;
In described the second opening, form the second electrode, the size of described the second electrode is less than the size of the first electrode, and described the second electrode covers bottom and the Part I sidewall of described the second opening, the Part II sidewall of exposed described the second opening;
On described the first electrode in described first opening of described DRAM cell region and described insulating barrier, form the first dielectric layer;
On described second electrode of described RRAM cell region and the described Part II sidewall of described the second opening and described insulating barrier, form the second dielectric layer;
On described the first dielectric layer, form third electrode; And
On described the second dielectric layer, form one the 4th electrode,
Wherein said the first electrode, described the first dielectric layer and described third electrode composition DRAM capacitor, and described the second electrode, described the second dielectric layer and described the 4th electrode composition RRAM memory cell.
8. the manufacture method of semiconductor element as claimed in claim 7, wherein forms described the first electrode and comprises with the step that forms described the second electrode:
In described substrate, form electrode material layer, cover sidewall and the bottom of described insulating barrier and described the first opening and described second opening of described DRAM cell region and described RRAM cell region;
In described substrate, form sacrifice layer, cover the described electrode material layer of described DRAM cell region and described RRAM cell region, and fill up described the first opening and described the second opening;
Remove described sacrifice layer and described electrode material layer on the described insulating barrier of described DRAM cell region and described RRAM cell region, expose the surface of described insulating barrier;
In described substrate, form cover curtain layer, cover described DRAM cell region;
Taking described cover curtain layer as cover curtain, remove the partial sacrifice layer in described the second opening, make the height of the described sacrifice layer in described the second opening lower than the height of the described sacrifice layer in described the first opening;
Taking described cover curtain layer and described sacrifice layer as cover curtain, described electrode material layer described in etch-back in the second opening, the described electrode material layer of staying in described the second opening forms described the second electrode, and the described electrode material layer of staying in described the first opening forms described the first electrode;
Remove described cover curtain layer; And
Remove described sacrifice layer, expose the described Part II sidewall of described the first electrode and described the second electrode and described the second opening.
9. the manufacture method of semiconductor element as claimed in claim 7, the material of wherein said the first dielectric layer and described the second dielectric layer is identical and be to form simultaneously.
10. the manufacture method of semiconductor element as claimed in claim 7, the material of wherein said the first dielectric layer and described the second dielectric layer is different and form while being different.
The manufacture method of 11. semiconductor elements as claimed in claim 10, the material of wherein said the second dielectric layer comprises variable-resistance material.
The manufacture method of 12. semiconductor elements as claimed in claim 10, is also included between described the second dielectric layer and described the 4th electrode and forms metal level.
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| CN109742064A (en) * | 2015-04-27 | 2019-05-10 | 精材科技股份有限公司 | Wafer encapsulation body and its manufacturing method |
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|---|---|---|---|---|
| KR20090020391A (en) * | 2007-08-23 | 2009-02-26 | 삼성전자주식회사 | Multi-level nonvolatile memory device, program method thereof, and fabricating method thereof |
| US20100001331A1 (en) * | 2008-07-04 | 2010-01-07 | Elpida Memory, Inc. | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20090020391A (en) * | 2007-08-23 | 2009-02-26 | 삼성전자주식회사 | Multi-level nonvolatile memory device, program method thereof, and fabricating method thereof |
| US20100001331A1 (en) * | 2008-07-04 | 2010-01-07 | Elpida Memory, Inc. | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109742064A (en) * | 2015-04-27 | 2019-05-10 | 精材科技股份有限公司 | Wafer encapsulation body and its manufacturing method |
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