CN104216450B - A kind of power device and simulative debugging circuit thereof - Google Patents
A kind of power device and simulative debugging circuit thereof Download PDFInfo
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- CN104216450B CN104216450B CN201310220323.7A CN201310220323A CN104216450B CN 104216450 B CN104216450 B CN 104216450B CN 201310220323 A CN201310220323 A CN 201310220323A CN 104216450 B CN104216450 B CN 104216450B
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Abstract
The present invention is applicable to power device field, particularly relates to a kind of power device and simulative debugging circuit thereof, exports electronics optical gate signal by electronics shutter control circuit to excitation power supply circuit and gate pulse control circuit; By high power pulse control circuit to excitation power supply circuit output high power pulse signal or to gate pulse control circuit out gate pulse signal; Gate pulse control circuit generates square-wave signal, and to the square-wave signal after the adjustment of Super pulse control circuit output amplitude, meanwhile, gate pulse control circuit is controlled to excitation power supply circuit out gate pulse signal or square-wave signal by this electronics optical gate signal; Super pulse control circuit exports ultrawideband impulse signal to excitation power supply circuit; More optimizedly, the amplitude of the electronics optical gate signal, high power pulse signal, door pulse signal and the ultrawideband impulse signal that export to excitation power supply circuit is adjusted by adjustment current regulating circuit.Thus the embodiment of the present invention controls to export different signals to excitation power supply, is convenient to debugging.
Description
Technical field
The invention belongs to power device field, particularly relate to a kind of power device and simulative debugging circuit thereof.
Background technology
At present, excitation power supply is as the critical component of high power gas laser, and during high power gas laser work, excitation power supply control signal is provided by Laser Control System.But when excitation power supply is debugged as independent equipment, because Laser Control System is complicated, and there is the control signal of a lot of non-actuated power supply needs, can inconvenient debugging be caused.
Summary of the invention
The object of the present invention is to provide a kind of simulative debugging circuit, aim to provide a kind of control exports simulative debugging circuit from different control signals to excitation power supply.
The present invention is achieved in that the external excitation power supply circuit of described simulative debugging circuit, and described simulative debugging circuit comprises:
For controlling whether to generate electronics optical gate signal according to switch order and the electronics shutter control circuit exporting described electronics optical gate signal to described excitation power supply circuit and gate pulse control circuit;
For generating high power pulse signal or door pulse signal according to generation steering order and export described high power pulse signal to described excitation power supply circuit or export the high power pulse control circuit of described door pulse signal to described gate pulse control circuit;
For regulating the current regulating circuit of the size of current of described excitation power supply circuit;
For generating square-wave signal and exporting described square-wave signal to Super pulse control circuit, control according to selection instruction the described gate pulse control circuit exporting described door pulse signal or described square-wave signal to described excitation power supply circuit; And
For generating ultrawideband impulse signal and exporting the described Super pulse control circuit of described ultrawideband impulse signal to described excitation power supply circuit;
Described electronics shutter control circuit connects described excitation power supply circuit, described current regulating circuit and described gate pulse control circuit, described high power pulse control circuit connects described excitation power supply circuit, described current regulating circuit and described gate pulse control circuit, described Super pulse control circuit connects described excitation power supply circuit and described gate pulse control circuit, and described gate pulse control circuit and described current regulating circuit connect described excitation power supply circuit.
Another object of the present invention is to provide a kind of power device, described power device comprises excitation power supply circuit, and described power device also comprises above-mentioned simulative debugging circuit; The external excitation power supply circuit of described simulative debugging circuit.
In the present invention, electronics optical gate signal is exported by electronics shutter control circuit to excitation power supply circuit and gate pulse control circuit; By high power pulse control circuit to excitation power supply circuit output high power pulse signal or to gate pulse control circuit out gate pulse signal; By this electronics optical gate signal control gate pulse control circuit whether to excitation power supply circuit out gate pulse signal; Gate pulse control circuit generates square-wave signal, and to the square-wave signal after the adjustment of Super pulse control circuit output amplitude, meanwhile, controls to excitation power supply circuit out gate pulse signal or square-wave signal; Super pulse control circuit, by after superposing the square-wave signal after square-wave signal and two divided-frequency, generates ultrawideband impulse signal and also exports excitation power supply circuit to; More optimizedly, the amplitude of the electronics optical gate signal, high power pulse signal, door pulse signal and the ultrawideband impulse signal that export to excitation power supply circuit is adjusted by adjustment current regulating circuit.Thus the simulative debugging control circui that the embodiment of the present invention provides exports different signals to excitation power supply, be convenient to debugging.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the simulative debugging circuit that the embodiment of the present invention provides;
Fig. 2 is the circuit diagram that simulative debugging circuit that the embodiment of the present invention provides comprises electronics shutter control circuit, high power pulse control circuit and current regulating circuit;
Fig. 3 is the circuit diagram of the gate pulse control circuit in the simulative debugging circuit that provides of the embodiment of the present invention;
Fig. 4 is the circuit diagram of the Super pulse control circuit in the simulative debugging circuit that provides of the embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 1 shows the structure of the simulative debugging circuit that the embodiment of the present invention provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention, details are as follows.
A kind of simulative debugging circuit, the external excitation power supply circuit of described simulative debugging circuit, described simulative debugging circuit comprises:
For controlling whether to generate electronics optical gate signal according to switch order and the electronics shutter control circuit 1 exporting described electronics optical gate signal to described excitation power supply circuit and gate pulse control circuit 3;
For generating high power pulse signal or door pulse signal according to generation steering order and export described high power pulse signal to described excitation power supply circuit or export the high power pulse control circuit 2 of described door pulse signal to gate pulse control circuit 3;
For regulating the current regulating circuit 5 of the size of current of described excitation power supply circuit;
For generating square-wave signal and exporting described square-wave signal to Super pulse control circuit 4, control according to selection instruction the gate pulse control circuit 3 exporting described door pulse signal or described square-wave signal to described excitation power supply circuit; And
For generating ultrawideband impulse signal and exporting the Super pulse control circuit 4 of described ultrawideband impulse signal to described excitation power supply circuit;
Electronics shutter control circuit 1 connects described excitation power supply circuit, current regulating circuit 5 and gate pulse control circuit 3, high power pulse control circuit 2 connects described excitation power supply circuit, current regulating circuit 5 and gate pulse control circuit 3, Super pulse control circuit 4 connects described excitation power supply circuit and gate pulse control circuit 3, and gate pulse control circuit 3 and current regulating circuit 5 connect described excitation power supply circuit.
It should be noted that, described switch order can be: user's manual ON physical switch, the switch order of generation, or the switch order produced by programmable logic controller (PLC) (ProgrammableLogicController, PLC).
It should be noted that, described generation steering order can be: the gating switch of user's manual ON physics, produce the generation steering order generating high power pulse signal or the generation steering order generating door pulse signal, or produce the generation steering order generating high power pulse signal or the generation steering order generating door pulse signal by PLC.
It should be noted that, described selection instruction can be: the gating switch of user's manual ON physics, selects the selection instruction of out gate pulse signal or square-wave signal, or is produced the selection instruction selecting out gate pulse signal or square-wave signal by PLC.
The simulative debugging circuit that Fig. 2 shows the embodiment of the present invention to be provided comprises the physical circuit of electronics shutter control circuit 1, high power pulse control circuit 2 and current regulating circuit 5, for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention, details are as follows.
As one embodiment of the invention, described current regulating circuit 5 comprises:
Battery BT1, the first three terminal regulator TL1, the second three terminal regulator TL2, the 3rd three terminal regulator TL3, the 4th three terminal regulator TL4, potentiometer RL1 and the 3rd current-limiting resistance R3;
The positive pole of described battery BT1 and negative pole connect power supply VCC and ground respectively, the first termination power VCC of described 3rd current-limiting resistance R3, the reference pole of described first three terminal regulator TL1 connects negative electrode, the negative electrode of described first three terminal regulator TL1 and anode connect second end of described 3rd current-limiting resistance R3 and the negative electrode of described second three terminal regulator TL2 respectively, the reference pole of described second three terminal regulator TL2 connects negative electrode, the anode of described second three terminal regulator TL2 connects the negative electrode of described 3rd three terminal regulator TL3, the reference pole of described 3rd three terminal regulator TL3 connects negative electrode, the reference pole of described 4th three terminal regulator TL4 connects negative electrode, the negative electrode of described 4th three terminal regulator TL4 and anode connect anode and the ground of described 3rd three terminal regulator TL3 respectively, the first end of described potentiometer RL1 and the second end connect the second end and the ground of described 3rd current-limiting resistance R3 respectively, electronics shutter control circuit 1 and described high power pulse control circuit 2 described in first termination of described 3rd current-limiting resistance R3, excitation power supply circuit described in the slip termination of described potentiometer RL1.
More optimizedly, the slip termination Current adjustment pin CP1 of described potentiometer RL1, by this Current adjustment pin CP1 to excitation power supply circuit output current conditioning signal.
It should be noted that, the voltage that battery BT1 exports, by after the first three terminal regulator TL1, the second three terminal regulator TL2, the 3rd three terminal regulator TL3 and the 4th three terminal regulator TL4 voltage stabilizing, is powered to potentiometer RL1; By the sliding end of migration potential device RL1, Current adjustment pin CP1, to excitation power supply circuit output current conditioning signal, carries out linear regulation by this current regulating signal to the electric current in excitation power supply circuit.
As one embodiment of the invention, described electronics shutter control circuit 1 comprises:
First current-limiting resistance R1 and the first three-terminal switch SW1;
The first end of described first current-limiting resistance R1 and the second end connect the first end of described 3rd current-limiting resistance R3 and first movable end of described first three-terminal switch SW1 respectively, excitation power supply circuit and described gate pulse control circuit 3 described in the fixing termination of described first three-terminal switch SW1.
More optimizedly, the fixing termination electronic light lock pin EP0 of described first three-terminal switch SW1, exports electronics optical gate signal to excitation power supply circuit and gate pulse control circuit 3 by this electronics optical gate pin EP0 simultaneously.
It should be noted that, after current regulating circuit 5 generates original electron optical gate signal, this original electron optical gate signal adjusts after current/voltage through the first current-limiting resistance R1, when the stiff end of the first three-terminal switch SW1 and the first movable end close, electronics optical gate pin EP0 exports electronics optical gate signal to excitation power supply circuit and gate pulse control circuit 3 simultaneously.
As one embodiment of the invention, described high power pulse control circuit 2 comprises:
Second current-limiting resistance R2 and the second three-terminal switch SW2;
The first end of described second current-limiting resistance R2 and the second end connect the first end of described 3rd current-limiting resistance R3 and the stiff end of described second three-terminal switch SW2 respectively, and first movable end of described second three-terminal switch SW2 and the second movable end connect described excitation power supply circuit and described gate pulse control circuit 3 respectively.
More optimizedly, the first activity termination high power pulse pin SP1 of described second three-terminal switch SW2, exports high power pulse signal by this high power pulse pin SP1 to excitation power supply circuit.The second activity termination gate pulse pin DP1 of described second three-terminal switch SW2, by this gate pulse pin DP1 to gate pulse control circuit 3 out gate pulse signal.
It should be noted that, after current regulating circuit 5 generates original burst signal, this original burst signal adjusts after current/voltage through the second current-limiting resistance R2, when the stiff end of the second three-terminal switch SW2 and the first movable end close, high power pulse pin SP1 exports high power pulse signal to excitation power supply circuit.After current regulating circuit 5 generates original burst signal, this original burst signal adjusts after current/voltage through the second current-limiting resistance R2, when the stiff end of the second three-terminal switch SW2 and the second movable end close, gate pulse pin DP1 is to gate pulse control circuit 3 out gate pulse signal.
Fig. 3 shows the physical circuit of the gate pulse control circuit 3 in the simulative debugging circuit that the embodiment of the present invention provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention, details are as follows.
As one embodiment of the invention, described gate pulse control circuit 3 comprises:
NPN type triode Q1, the 4th current-limiting resistance R4, the 3rd three-terminal switch SW3, the 5th divider resistance R5, the 6th divider resistance R6, the 7th divider resistance R7, the 8th divider resistance R8, the first filter capacitor C1, the second filter capacitor C2, the 3rd filter capacitor C3 and 555 timer chip U1;
The stiff end of the first three-terminal switch SW1 described in first termination of described 4th current-limiting resistance R4, the collector of described NPN type triode Q1, base stage and emitter connect second movable end of described second three-terminal switch SW2 respectively, second end of described 4th current-limiting resistance R4 and first movable end of described 3rd three-terminal switch SW3, second movable end of described 3rd three-terminal switch SW3 and stiff end connect the first end of described first filter capacitor C1 and described excitation power supply circuit respectively, the first end of described 5th divider resistance R5 and the second end connect described Super pulse control circuit 4 and ground respectively, the first end of described 6th divider resistance R6 and the second end meet the first end of described 5th divider resistance R5 and the output pin OUT of 555 timer chip U1 respectively, reset pin RD and the power pins VCC of described 555 timer chip U1 meet power supply VCC, the trigger pin TR of described 555 timer chip U1 and thresholding pin TH connects the first end of described 3rd filter capacitor C3, the ground pin GND of described 555 timer chip U1, electric discharge pin D and control pin CO ground connection respectively, the first end of described 8th divider resistance R8 and the first end of described second filter capacitor C2, second end of described second filter capacitor C2 and the second end ground connection of described 3rd filter capacitor C3, the first end of the 3rd filter capacitor C3 described in second termination of described 8th divider resistance R8, the first end of described 7th divider resistance R7 and the second end connect the first end of power supply VCC and described 8th divider resistance R8 respectively.
More optimizedly, the collector of described NPN type triode Q1 meets gate pulse pin DP1, is received the door pulse signal of high power pulse control circuit 2 output by this gate pulse pin DP1.The first termination electronic light lock pin EP0 of the 4th current-limiting resistance R4, receives the electronics optical gate signal of electronics shutter control circuit 1 output by this electronics optical gate pin EP0.The fixing termination gate pulse pin DP0 of the 3rd three-terminal switch SW3, by this gate pulse pin DP0 to excitation power supply circuit out gate pulse signal.The first termination square wave pin SP0 of the 5th divider resistance R5, exports square-wave signal by this square wave pin SP0 to Super pulse control circuit 4.
It should be noted that, when the base stage of NPN type triode Q1 receives electronics optical gate signal that electronics shutter control circuit 1 exports, high level by the 4th current-limiting resistance R4, NPN type triode Q1 conducting, meanwhile, if when the stiff end of the 3rd three-terminal switch SW3 and the first movable end close, gate pulse pin DP0 is to excitation power supply circuit out gate pulse signal.Therefore, the electronics optical gate signal produced by shutter control circuit, controls the ON/OFF of NPN type triode Q1, thus control gate pulse pin DP0 is to excitation power supply circuit whether out gate pulse signal.
555 timer chip U1, the 7th divider resistance R7, the 8th divider resistance R8, the first filter capacitor C1, the second filter capacitor C2 and the 3rd filter capacitor C3 composition generates the circuit of square-wave signal; By regulating the resistance of the 7th divider resistance R7 and the 8th divider resistance R8, regulating the capacitance of the 3rd filter capacitor C3, the output pin OUT controlling 555 timer chip U1 exports the square-wave signal of different frequency, different duty.If when the stiff end of the 3rd three-terminal switch SW3 and the second movable end close, the output pin OUT of 555 timer chip U1 exports square-wave signal by gate pulse pin DP0 to excitation power supply circuit.In addition, by the 5th divider resistance R5 and the 6th divider resistance R6, range-adjusting is done to the square-wave signal that the output pin OUT of 555 timer chip U1 exports, by square wave pin SP0 to the square-wave signal after the adjustment of Super pulse control circuit 4 output amplitude, the highest amplitude of the square-wave signal after this range-adjusting is the magnitude of voltage at the 5th divider resistance R5 two ends.
Fig. 4 shows the physical circuit of the Super pulse control circuit 4 in the simulative debugging circuit that the embodiment of the present invention provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention, details are as follows.
As one embodiment of the invention, described Super pulse control circuit 4 comprises:
9th current-limiting resistance R9, the tenth current-limiting resistance R10, the 11 current-limiting resistance R11, the 12 divider resistance R12, the 13 divider resistance R13, the 14 divider resistance R14, the 15 divider resistance R15, the 16 divider resistance R16, the 17 divider resistance R17, the 4th filter capacitor C4, the 5th filter capacitor C5, the 6th filter capacitor C6, the 3rd amplifier chip U3, the 4th amplifier chip U4, d type flip flop chip U2 and switch S 1;
The first end of the 5th divider resistance R5 described in first termination of described tenth current-limiting resistance R10, the first end of described tenth current-limiting resistance R10 and the second end meet the first end of described 5th divider resistance R5 and the high voltage input pin VI+ of described 3rd amplifier chip U3 respectively, between the low-voltage input pin VI-that described 11 current-limiting resistance R11 is connected to described 3rd amplifier chip U3 and output pin VO, the first end of described 4th filter capacitor C4 and the second end connect output pin VO and the ground of described 3rd amplifier chip U3 respectively, the first end of described 9th current-limiting resistance R9 and the second end meet the first end of described tenth current-limiting resistance R10 and the clock pins CLK of described d type flip flop chip U2 respectively, the input pin D of described d type flip flop chip U2 meets reverse output pin Q2, the first end of described 5th filter capacitor C5 and the second end connect forward output pin Q1 and the ground of described d type flip flop chip U2 respectively, the first end of described 13 divider resistance R13 and the second end meet the first end of described 5th filter capacitor C5 and the high voltage input pin VI+ of described 4th amplifier chip U4 respectively, between the second end that described 12 divider resistance R12 is connected to described 4th filter capacitor C4 and second end of described 13 divider resistance R13, the first end of described 15 divider resistance R15 and the second end connect the second end and the ground of described 13 divider resistance R13 respectively, the first end of described 14 divider resistance R14 and the second end connect low-voltage input pin VI-and the ground of described 4th amplifier chip U4 respectively, between the low-voltage input pin VI-that described 16 divider resistance R16 is connected to described 4th amplifier chip U4 and output pin VO, between the output pin VO being connected to described 4th amplifier chip U4 after described 17 divider resistance R17 and described 6th filter capacitor C6 parallel connection and ground, the first end of described switch S 1 and the second end connect the output pin VO of described 4th amplifier chip U4 and described excitation power supply circuit respectively.
More optimizedly, the second termination Super pulse pin SP2 of switch S 1, exports ultrawideband impulse signal by this Super pulse pin SP2 to excitation power supply circuit.
More optimizedly, the first termination square wave pin SP0 of the tenth current-limiting resistance R10, the square-wave signal after the range-adjusting exported by this square wave pin SP0 receiving gate pulse control circuit 3, this square-wave signal after the tenth current-limiting resistance R10, then after the voltage follower that the 11 current-limiting resistance R11 and the 3rd amplifier chip U3 forms, exports the square-wave signal that driving force is stronger, meanwhile, this square-wave signal after the 9th current-limiting resistance R9, then carries out two divided-frequency through d type flip flop chip U2, to export the square-wave signal of 1/2nd frequencies of the square-wave signal that square wave pin SP0 receives, by the 4th amplifier chip U4, 12 divider resistance R12, 13 divider resistance R13, 14 divider resistance R14, the adding circuit that 15 divider resistance R15 and the 16 divider resistance R16 forms, square-wave signal after the two divided-frequency that the square-wave signal export the 3rd amplifier chip U3 and d type flip flop chip U2 export is added, generate original ultrawideband impulse signal, after switch S 1 is closed, after the filtering circuit of this original ultrawideband impulse signal by the 17 divider resistance R17 and the 6th filter capacitor C6 composition, generate ultrawideband impulse signal, and export this ultrawideband impulse signal by Super pulse pin SP2 to excitation power supply circuit.
As another embodiment of the present invention, the embodiment of the present invention also provides a kind of power device, and described power device comprises excitation power supply circuit, and described power device also comprises above-mentioned simulative debugging circuit; The external excitation power supply circuit of described simulative debugging circuit.
In embodiments of the present invention, electronics optical gate signal is exported by the first three-terminal switch SW1 of electronics shutter control circuit to excitation power supply circuit and gate pulse control circuit; High power pulse signal is exported or to gate pulse control circuit out gate pulse signal to excitation power supply circuit by the second three-terminal switch SW2 of high power pulse control circuit; By the ON/OFF of NPN type triode Q1 in this electronics optical gate signal control gate pulse control circuit, with control gate pulse control circuit whether to excitation power supply circuit out gate pulse signal; Gate pulse control circuit generates square-wave signal, and to the square-wave signal after the adjustment of Super pulse control circuit output amplitude; By the 3rd three-terminal switch SW3, control to excitation power supply circuit out gate pulse signal or square-wave signal; Super pulse control circuit, by after superposing the square-wave signal after square-wave signal and two divided-frequency, generates ultrawideband impulse signal, to export excitation power supply circuit to; More optimizedly, by regulating the potentiometer RL1 in current regulating circuit, the amplitude of electronics optical gate signal, high power pulse signal, door pulse signal and the ultrawideband impulse signal exported to excitation power supply circuit is adjusted.Thus the simulative debugging control circui that the embodiment of the present invention provides exports different signals to excitation power supply, be convenient to debugging.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a simulative debugging circuit, the external excitation power supply circuit of described simulative debugging circuit, is characterized in that, described simulative debugging circuit comprises:
For controlling whether to generate electronics optical gate signal according to switch order and the electronics shutter control circuit exporting described electronics optical gate signal to described excitation power supply circuit and gate pulse control circuit;
For generating high power pulse signal or door pulse signal according to generation steering order and export described high power pulse signal to described excitation power supply circuit or export the high power pulse control circuit of described door pulse signal to described gate pulse control circuit;
For regulating the current regulating circuit of the size of current of described excitation power supply circuit;
For generating square-wave signal and exporting described square-wave signal to Super pulse control circuit, control according to selection instruction the described gate pulse control circuit exporting described door pulse signal or described square-wave signal to described excitation power supply circuit; And
For generating ultrawideband impulse signal and exporting the described Super pulse control circuit of described ultrawideband impulse signal to described excitation power supply circuit;
Described electronics shutter control circuit connects described excitation power supply circuit, described current regulating circuit and described gate pulse control circuit, described high power pulse control circuit connects described excitation power supply circuit, described current regulating circuit and described gate pulse control circuit, described Super pulse control circuit connects described excitation power supply circuit and described gate pulse control circuit, and described gate pulse control circuit and described current regulating circuit connect described excitation power supply circuit.
2. simulative debugging circuit as claimed in claim 1, it is characterized in that, described current regulating circuit comprises:
Battery (BT1), the first three terminal regulator (TL1), the second three terminal regulator (TL2), the 3rd three terminal regulator (TL3), the 4th three terminal regulator (TL4), potentiometer (RL1) and the 3rd current-limiting resistance (R3);
Positive pole and the negative pole of described battery (BT1) connect VDD-to-VSS respectively, first termination power of described 3rd current-limiting resistance (R3), the reference pole of described first three terminal regulator (TL1) connects negative electrode, the negative electrode of described first three terminal regulator (TL1) and anode connect described second end of the 3rd current-limiting resistance (R3) and the negative electrode of described second three terminal regulator (TL2) respectively, the reference pole of described second three terminal regulator (TL2) connects negative electrode, the anode of described second three terminal regulator (TL2) connects the negative electrode of described 3rd three terminal regulator (TL3), the reference pole of described 3rd three terminal regulator (TL3) connects negative electrode, the reference pole of described 4th three terminal regulator (TL4) connects negative electrode, the negative electrode of described 4th three terminal regulator (TL4) and anode connect anode and the ground of described 3rd three terminal regulator (TL3) respectively, the first end of described potentiometer (RL1) and the second end connect the second end and the ground of described 3rd current-limiting resistance (R3) respectively, electronics shutter control circuit and described high power pulse control circuit described in first termination of described 3rd current-limiting resistance (R3), excitation power supply circuit described in the slip termination of described potentiometer (RL1).
3. simulative debugging circuit as claimed in claim 2, it is characterized in that, described electronics shutter control circuit comprises:
First current-limiting resistance (R1) and the first three-terminal switch (SW1);
The first end of described first current-limiting resistance (R1) and the second end connect the described first end of the 3rd current-limiting resistance (R3) and the first movable end of described first three-terminal switch (SW1) respectively, excitation power supply circuit and described gate pulse control circuit described in the fixing termination of described first three-terminal switch (SW1).
4. simulative debugging circuit as claimed in claim 2, it is characterized in that, described high power pulse control circuit comprises:
Second current-limiting resistance (R2) and the second three-terminal switch (SW2);
The first end of described second current-limiting resistance (R2) and the second end connect the described first end of the 3rd current-limiting resistance (R3) and the stiff end of described second three-terminal switch (SW2) respectively, and the first movable end of described second three-terminal switch (SW2) and the second movable end connect described excitation power supply circuit and described gate pulse control circuit respectively.
5. simulative debugging circuit as claimed in claim 3, it is characterized in that, described gate pulse control circuit comprises:
NPN type triode (Q1), the 4th current-limiting resistance (R4), the 3rd three-terminal switch (SW3), the 5th divider resistance (R5), the 6th divider resistance (R6), the 7th divider resistance (R7), the 8th divider resistance (R8), the first filter capacitor (C1), the second filter capacitor (C2), the 3rd filter capacitor (C3) and 555 timer chips (U1);
The stiff end of the first three-terminal switch (SW1) described in first termination of described 4th current-limiting resistance (R4), the collector of described NPN type triode (Q1), base stage and emitter connect the second movable end of described second three-terminal switch (SW2) respectively, second end of described 4th current-limiting resistance (R4) and the first movable end of described 3rd three-terminal switch (SW3), second movable end and the stiff end of described 3rd three-terminal switch (SW3) connect the first end of described first filter capacitor (C1) and described excitation power supply circuit respectively, the first end of described 5th divider resistance (R5) and the second end connect described Super pulse control circuit and ground respectively, the first end of described 6th divider resistance (R6) and the second end connect the described first end of the 5th divider resistance (R5) and the output pin of 555 timer chips (U1) respectively, reset pin and the power pins of described 555 timer chips (U1) connect power supply, the trigger pin of described 555 timer chips (U1) and thresholding pin connect the first end of described 3rd filter capacitor (C3), the ground pin of described 555 timer chips (U1), electric discharge pin and control pin ground connection respectively, the described first end of the 8th divider resistance (R8) and the first end of described second filter capacitor (C2), second end of described second filter capacitor (C2) and the second end ground connection of described 3rd filter capacitor (C3), the first end of the 3rd filter capacitor (C3) described in second termination of described 8th divider resistance (R8), the first end of described 7th divider resistance (R7) and the second end connect the first end of power supply and described 8th divider resistance (R8) respectively.
6. simulative debugging circuit as claimed in claim 5, it is characterized in that, described Super pulse control circuit comprises:
9th current-limiting resistance (R9), tenth current-limiting resistance (R10), 11 current-limiting resistance (R11), 12 divider resistance (R12), 13 divider resistance (R13), 14 divider resistance (R14), 15 divider resistance (R15), 16 divider resistance (R16), 17 divider resistance (R17), 4th filter capacitor (C4), 5th filter capacitor (C5), 6th filter capacitor (C6), 3rd amplifier chip (U3), 4th amplifier chip (U4), d type flip flop chip (U2) and switch (S1),
The first end of the 5th divider resistance (R5) described in first termination of described tenth current-limiting resistance (R10), the first end of described tenth current-limiting resistance (R10) and the second end connect the first end of described 5th divider resistance (R5) and the high voltage input pin of described 3rd amplifier chip (U3) respectively, between the low-voltage input pin that described 11 current-limiting resistance (R11) is connected to described 3rd amplifier chip (U3) and output pin, the first end of described 4th filter capacitor (C4) and the second end connect output pin and the ground of described amplifier chip (U3) respectively, the first end of described 9th current-limiting resistance (R9) and the second end connect the described first end of the tenth current-limiting resistance (R10) and the clock pins of described d type flip flop chip (U2) respectively, the input pin of described d type flip flop chip (U2) connects reverse output pin, the first end of described 5th filter capacitor (C5) and the second end connect forward output pin and the ground of described d type flip flop chip (U2) respectively, the first end of described 13 divider resistance (R13) and the second end connect the first end of described 5th filter capacitor (C5) and the high voltage input pin of described 4th amplifier chip (U4) respectively, between the second end that described 12 divider resistance (R12) is connected to described 4th filter capacitor (C4) and the second end of described 13 divider resistance (R13), the first end of described 15 divider resistance (R15) and the second end connect the second end and the ground of described 13 divider resistance (R13) respectively, the first end of described 14 divider resistance (R14) and the second end connect low-voltage input pin and the ground of described 4th amplifier chip (U4) respectively, between the low-voltage input pin that described 16 divider resistance (R16) is connected to described 4th amplifier chip (U4) and output pin, between the output pin being connected to described 4th amplifier chip (U4) after described 17 divider resistance (R17) and described 6th filter capacitor (C6) parallel connection and ground, the first end of described switch (S1) and the second end connect the output pin of described 4th amplifier chip (U4) and described excitation power supply circuit respectively.
7. a power device, described power device comprises excitation power supply circuit, it is characterized in that, described power device also comprises the simulative debugging circuit as described in any one of claim 1 to 6;
The external excitation power supply circuit of described simulative debugging circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310220323.7A CN104216450B (en) | 2013-06-05 | 2013-06-05 | A kind of power device and simulative debugging circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310220323.7A CN104216450B (en) | 2013-06-05 | 2013-06-05 | A kind of power device and simulative debugging circuit thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104216450A CN104216450A (en) | 2014-12-17 |
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| CN201310220323.7A Active CN104216450B (en) | 2013-06-05 | 2013-06-05 | A kind of power device and simulative debugging circuit thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107565369B (en) * | 2017-08-17 | 2020-05-19 | 大族激光科技产业集团股份有限公司 | Pulse waveform modulation system of laser |
| CN113110242B (en) * | 2021-05-14 | 2022-04-08 | 中国核动力研究设计院 | High-efficiency analog quantity signal output device |
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| GB2099244A (en) * | 1981-05-01 | 1982-12-01 | Nippon Infrared Ind | Laser apparatus |
| CN86207551U (en) * | 1986-10-17 | 1987-07-29 | 湖南省技术物理研究所 | Light intensity controlling device for carbon-dioxide laser |
| WO1997019526A1 (en) * | 1995-11-21 | 1997-05-29 | University Of Rochester | Improvements in transmission of optical signals |
| US6072427A (en) * | 1999-04-01 | 2000-06-06 | Mcewan; Thomas E. | Precision radar timebase using harmonically related offset oscillators |
| CN1260614A (en) * | 1999-01-12 | 2000-07-19 | 宫地技术株式会社 | Laser apparatus |
| CN102545010A (en) * | 2011-12-25 | 2012-07-04 | 深圳市大族激光科技股份有限公司 | Oil tank control device of laser |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2099244A (en) * | 1981-05-01 | 1982-12-01 | Nippon Infrared Ind | Laser apparatus |
| CN86207551U (en) * | 1986-10-17 | 1987-07-29 | 湖南省技术物理研究所 | Light intensity controlling device for carbon-dioxide laser |
| WO1997019526A1 (en) * | 1995-11-21 | 1997-05-29 | University Of Rochester | Improvements in transmission of optical signals |
| CN1260614A (en) * | 1999-01-12 | 2000-07-19 | 宫地技术株式会社 | Laser apparatus |
| US6072427A (en) * | 1999-04-01 | 2000-06-06 | Mcewan; Thomas E. | Precision radar timebase using harmonically related offset oscillators |
| CN102545010A (en) * | 2011-12-25 | 2012-07-04 | 深圳市大族激光科技股份有限公司 | Oil tank control device of laser |
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| CN104216450A (en) | 2014-12-17 |
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