CN104202910A - Hole wall desmear process for fine-line multilayer circuit boards - Google Patents
Hole wall desmear process for fine-line multilayer circuit boards Download PDFInfo
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- CN104202910A CN104202910A CN201410473368.XA CN201410473368A CN104202910A CN 104202910 A CN104202910 A CN 104202910A CN 201410473368 A CN201410473368 A CN 201410473368A CN 104202910 A CN104202910 A CN 104202910A
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- cleaning fluid
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Cleaning By Liquid Or Steam (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention relates to a hole wall desmear process for fine-line multilayer circuit boards. The process includes the following steps: S1, for cleaning fluid preparation, taking 350-500ml of PI regulator and 35-45g of additive with mixing, adding water to supplement the mixture to 1000ml, and stirring uniformly; S2, for heating, heating cleaning fluid prepared in the step S1 to 40-47 DEG C, and maintaining constant temperature; S3, for cleaning, pouring the cleaning fluid into a cleaning tank of an ultrasonic cleaner, maintaining constant temperature, and turning on the ultrasonic cleaner for cleaning for 5-20 min after to-be-cleaned circuit boards are placed in the cleaning fluid; S4, for cleaning fluid removal, flushing the circuit boards with deionized water for 3-5min, and taking out the circuit boards prior to drying; S5, for detection, performing sampling prior to microsectioning, measuring amount of pitting, and observing cleaning quality. The process has the advantages of low cost, simplicity and good desmear effect.
Description
Technical field
The present invention relates to circuit board desmearing technique, particularly the hole wall of fine-line multilayer circuit board is removed and is bored dirty technique.
Background technology
Mostly the at present design of all electronic instrument circuits is take that printed circuit board (PCB) is basic with being connected, scientific and technological progress along with electronics industry, in order better to adapt to the demand of electronics miniaturization, the number of plies of flex circuit application constantly increases, via diameter constantly reduces, thickness of slab/aperture ratio is increasing, and it is more and more difficult that dirt is bored in the removing of hole wall.If the brill dirt in hole does not clean up, will affect the quality of hole metallization, cause conforming product rate to decline, affect the economic benefit of manufacturing enterprise.
At present, remove to bore dirty method and be divided into two kinds of dry method and wet methods: dry method is with Plasma Desmearing, needs specific plasma apparatus, and expense is high.Wet method desmearing comprises that the concentrated sulfuric acid, dense chromic acid, potassium permanganate PI adjust the solution such as liquid, and expense is lower.But in wet method desmearing technique, because the concentrated sulfuric acid can only be removed the dirt of epoxy resin brill, potassium permanganate desmearing easily causes the layering of flexible multi-layer plate, the toxicity of dense chromic acid can not be used on flexible multi-layer circuit board too greatly.
Summary of the invention
The object of the invention is to overcome the shortcoming of prior art, provide the hole wall removing of the fine-line multilayer circuit board that a kind of cost is low, technique simple and the dirt of removing brill is effective to bore dirty technique.
Object of the present invention is achieved through the following technical solutions: the hole wall of fine-line multilayer circuit board is removed and bored dirty technique, and it comprises the following steps:
S1, preparation cleaning fluid: get 350ml~500mlPI adjusting agent, 35g~45g additive, mix, add water and be supplemented to 1000ml, stir;
S2, heating: the cleaning fluid that step S1 is prepared is heated to 40 ℃~47 ℃, keep constant temperature;
S3, cleaning: cleaning fluid is poured in supersonic wave cleaning machine rinse bath, kept constant temperature, circuit board to be cleaned is put into described cleaning fluid, start is cleaned, and scavenging period is 5min~20min;
S4, removal cleaning fluid: with deionized water irrigation circuit plate 3min~5min, after taking-up, drying circuit plate;
S5, detection: sample, cook microsection, measure etchback amount, observe cleaning quality.
Before cooking microsection, also comprise heavy copper, copper-plated step.
The present invention has the following advantages:
1, PI adjusting agent for can buy on the market and cost low, in cleaning process, equipment cost used is also lower, realize to clean bores dirty cost low.
2, technique of the present invention is simple, easily realizes, and to operator quality level, requires lower.
3, ultrasonic wave physical cleaning method and PI adjust the effective combination of chemical cleaning method, obtain a kind of new cleaning method, especially aspect blind hole decontamination, are obtaining better effect.
Accompanying drawing explanation
Fig. 1 is the influence curve figure of PI adjusting agent content to etch-rate;
Fig. 2 is the influence curve figure of temperature to etch-rate;
Fig. 3 is the influence curve figure of additive level to etch-rate;
Embodiment
Below in conjunction with embodiment, the present invention will be further described, but protection scope of the present invention is not limited to the following stated.
[embodiment 1]:
The hole wall of fine-line multilayer circuit board is removed and is bored dirty technique, and it comprises the following steps:
S1, preparation cleaning fluid: get 500mlPI adjusting agent, 45g additive, mix, add water and be supplemented to 1000ml, stir;
S2, heating: the cleaning fluid that step S1 is prepared is heated to 47 ℃, keep constant temperature;
S3, cleaning: cleaning fluid is poured in supersonic wave cleaning machine rinse bath, kept constant temperature, circuit board to be cleaned is put into described cleaning fluid, start is cleaned, and scavenging period is 20min;
S4, removal cleaning fluid: with deionized water irrigation circuit plate 3min, after taking-up, drying circuit plate;
S5, detection: sample, cook microsection, measure etchback amount, observe cleaning quality.
Before cooking microsection, also comprise heavy copper, copper-plated step.
[embodiment 2]:
The hole wall of fine-line multilayer circuit board is removed and is bored dirty technique, and it comprises the following steps:
S1, preparation cleaning fluid: get 400mlPI adjusting agent, 40g additive, mix, add water and be supplemented to 1000ml, stir;
S2, heating: the cleaning fluid that step S1 is prepared is heated to 45 ℃, keep constant temperature;
S3, cleaning: cleaning fluid is poured in supersonic wave cleaning machine rinse bath, kept constant temperature, circuit board to be cleaned is put into described cleaning fluid, start is cleaned, and scavenging period is 10min;
S4, removal cleaning fluid: with deionized water irrigation circuit plate 4min, after taking-up, drying circuit plate;
S5, detection: sample, cook microsection, measure etchback amount, observe cleaning quality.
Before cooking microsection, also comprise heavy copper, copper-plated step.
[embodiment 3]:
The hole wall of fine-line multilayer circuit board is removed and is bored dirty technique, and it comprises the following steps:
S1, preparation cleaning fluid: get 350mlPI adjusting agent, 35g additive, mix, add water and be supplemented to 1000ml, stir;
S2, heating: the cleaning fluid that step S1 is prepared is heated to 40 ℃, keep constant temperature;
S3, cleaning: cleaning fluid is poured in supersonic wave cleaning machine rinse bath, kept constant temperature, circuit board to be cleaned is put into described cleaning fluid, start is cleaned, and scavenging period is 5min;
S4, removal cleaning fluid: with deionized water irrigation circuit plate 5min, after taking-up, drying circuit plate;
S5, detection: sample, cook microsection, measure etchback amount, observe cleaning quality.
Before cooking microsection, also comprise heavy copper, copper-plated step.
[embodiment 4]:
The hole wall of fine-line multilayer circuit board is removed and is bored dirty technique, and it comprises the following steps:
S1, preparation cleaning fluid: get 425mlPI adjusting agent, 39g additive, mix, add water and be supplemented to 1000ml, stir;
S2, heating: the cleaning fluid that step S1 is prepared is heated to 43 ℃, keep constant temperature;
S3, cleaning: cleaning fluid is poured in supersonic wave cleaning machine rinse bath, kept constant temperature, circuit board to be cleaned is put into described cleaning fluid, start is cleaned, and scavenging period is 15min;
S4, removal cleaning fluid: with deionized water irrigation circuit plate 4min, after taking-up, drying circuit plate;
S5, detection: sample, cook microsection, measure etchback amount, observe cleaning quality.
Before cooking microsection, also comprise heavy copper, copper-plated step.
The present invention, when determining the proportioning of cleaning fluid and process conditions, is according to factor related in cleaning fluid, the impact of etch-rate to be tested and determined by weight-loss method:
A, get 15 large little identical, to be pressed into by three layers of acrylic acid glued membrane and four strata acid imides breadboards;
B, at 120 ℃, toast 30 minutes, weigh one by one, record weight;
C, the in the situation that of fixing wherein three parameters, change respectively the test that then PI adjusting agent content, additive level and temperature do desmearing;
D, all at 120 ℃, toast 30 minutes after finishing, then weigh one by one, record weight;
Variation and the etch-rate of weight before and after E, calculating.
Experimental result:
1, as shown in Figure 1, temperature, additive level are certain, and along with the increase etch-rate of PI adjusting agent content constantly increases, when PI adjusting agent content surpasses after 500ml/L, etch-rate starts again to decline.
2, as shown in Figure 2, PI adjusting agent and additive level are certain, and along with the rising of temperature, etch-rate is increasing.
3, as shown in Figure 3, temperature, PI adjusting agent content are certain, and while just starting, along with the increase of additive level, etch-rate constantly increases, but when its content surpasses 50g/L, etch-rate no longer increases.
In sum, in cleaning fluid, the content of each composition is not that more etch-rates are just faster, but has a value range, and when component content one timing, temperature is better within the scope of 40 ℃~47 ℃.
According to above-mentioned experiment, determine the formula of cleaning fluid and control parameter, as shown in the table:
Governing factor | Technical parameter |
PI adjusting agent | 350ml/L~500ml/L |
Additive | 35g/L~45g/L |
Temperature | 40℃~47℃ |
Time | 3min~5min |
Agitating mode | Vacuum stirring |
Claims (2)
1. the hole wall of fine-line multilayer circuit board is removed and is bored dirty technique, it is characterized in that: it comprises the following steps:
S1, preparation cleaning fluid: get 350ml~500mlPI adjusting agent, 35g~45g additive, mix, add water and be supplemented to 1000ml, stir;
S2, heating: the cleaning fluid that step S1 is prepared is heated to 40 ℃~47 ℃, keep constant temperature;
S3, cleaning: cleaning fluid is poured in supersonic wave cleaning machine rinse bath, kept constant temperature, circuit board to be cleaned is put into described cleaning fluid, start is cleaned, and scavenging period is 5min~20min;
S4, removal cleaning fluid: with deionized water irrigation circuit plate 3min~5min, after taking-up, drying circuit plate;
S5, detection: sample, cook microsection, measure etchback amount, observe cleaning quality.
2. the hole wall of fine-line multilayer circuit board according to claim 1 is removed and is bored dirty technique, it is characterized in that: before cooking microsection, also comprise heavy copper, copper-plated step.
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CN201410473368.XA CN104202910A (en) | 2014-09-16 | 2014-09-16 | Hole wall desmear process for fine-line multilayer circuit boards |
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CN201410473368.XA CN104202910A (en) | 2014-09-16 | 2014-09-16 | Hole wall desmear process for fine-line multilayer circuit boards |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105921459A (en) * | 2016-06-12 | 2016-09-07 | 深圳市微纳集成电路与系统应用研究院 | Ultrasonic cleaning method for printed circuit board |
CN109323948A (en) * | 2018-08-15 | 2019-02-12 | 深圳崇达多层线路板有限公司 | A kind of testing mould and test method that can be improved except glue uniformity and efficiency |
CN113766748A (en) * | 2021-09-14 | 2021-12-07 | 苏州新晶腾光电科技有限公司 | Infrared touch module processing technology |
CN113814224A (en) * | 2021-08-23 | 2021-12-21 | 中国电子科技集团公司第十五研究所 | Printed board hole wall drilling dirt treatment method |
CN114018373A (en) * | 2021-10-28 | 2022-02-08 | 广州兴森快捷电路科技有限公司 | Glue removal amount measuring method and glue removal amount measuring system |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2005294323A (en) * | 2004-03-31 | 2005-10-20 | Ngk Spark Plug Co Ltd | Method of manufacturing wiring board |
CN101074407A (en) * | 2006-05-18 | 2007-11-21 | 施汉忠 | Method for removing circuit-board drilling foul |
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民航无损检测人员资格鉴定与认证委员会: "《航空器渗透检测》", 31 March 2014, 北京:中国民航出版社 * |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105921459A (en) * | 2016-06-12 | 2016-09-07 | 深圳市微纳集成电路与系统应用研究院 | Ultrasonic cleaning method for printed circuit board |
CN109323948A (en) * | 2018-08-15 | 2019-02-12 | 深圳崇达多层线路板有限公司 | A kind of testing mould and test method that can be improved except glue uniformity and efficiency |
CN113814224A (en) * | 2021-08-23 | 2021-12-21 | 中国电子科技集团公司第十五研究所 | Printed board hole wall drilling dirt treatment method |
CN113766748A (en) * | 2021-09-14 | 2021-12-07 | 苏州新晶腾光电科技有限公司 | Infrared touch module processing technology |
CN114018373A (en) * | 2021-10-28 | 2022-02-08 | 广州兴森快捷电路科技有限公司 | Glue removal amount measuring method and glue removal amount measuring system |
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Application publication date: 20141210 |