CN104201101A - Production method for double-contact-hole etching stop layer - Google Patents
Production method for double-contact-hole etching stop layer Download PDFInfo
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- CN104201101A CN104201101A CN201410428687.9A CN201410428687A CN104201101A CN 104201101 A CN104201101 A CN 104201101A CN 201410428687 A CN201410428687 A CN 201410428687A CN 104201101 A CN104201101 A CN 104201101A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
Abstract
The invention discloses a production method for a double-contact-hole etching stop layer. According to the production method, on a high-tensile-stress silicon nitride layer taking an MOS device as a contact-hole etching stop layer, a multilayer laminate composed of the silicon nitride layer and a silicon oxide layer in an alternating manner is used as an ultraviolet light barrier layer in a PMOS area, selective ultraviolet light curing treatment is carried out on the high-tensile-stress silicon nitride layer of the PMOS area and an NMOS area, a high-tensile-stress silicon nitride layer with a relatively low tensile stress covers the PMOS area, a high-tensile-stress silicon nitride layer with a relatively high tensile stress covers the NMOS area, so as to realize the silicon nitride double-contact-hole etching stop layer with different high tensile stresses on the PMOS area and the NMOS area, thus avoiding the negative influence of single-step high-tensile-stress silicon nitride deposition on the hole mobility of a PMOS device, avoiding the complexity of a process of forming the double-contact-hole etching stop layer by virtue of two-step silicon nitride deposition, realizing improvement for the electric performances of a device with a low cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, more specifically, relate to a kind of manufacture method of the dual contact etching stop layer based on strained silicon technology.
Background technology
Along with the development of CMOS integrated circuit fabrication process and dwindling of critical size, a lot of new methods are applied in device fabrication, in order to improve device performance.Heavily stressed silicon nitride film is owing to can effectively improving metal-oxide-semiconductor carrier mobility, and then the raising device speed of service, is therefore introduced in integrated circuit fabrication process.Compression on PMOS channel direction can improve PMOS device hole mobility, and tensile stress on NMOS channel direction can improve electron mobility in nmos device.
Refer to Fig. 1, Fig. 1 is the existing device architecture schematic diagram that forms heavily stressed silicon nitride film contact hole etching stop-layer on MOS device.As shown in the figure, on MOS device 1, be formed with heavily stressed silicon nitride film 2 as contact hole etching stop-layer.From the performance of device, on PMOS device, need the silicon nitride contact hole etching stop-layer that compression is high, and on nmos device, need the silicon nitride contact hole etching stop-layer that tensile stress is high.This just requires to apply Dual CESL technique (dual contact etching stopping layer process).
Traditional Dual CESL technique need to be carried out two step silicon nitride depositions, and its main flow process is the high pressure stress silicon nitride layer in the territory, high tensile stress silicon nitride layer → high pressure stress silicon nitride deposition → photoetching → removal nmos area in high tensile stress silicon nitride deposition (comprising UV-curing metallization processes) → silicon oxide masking film layer deposition → photoetching → removal PMOS region.Owing to needing to carry out two step photoetching in the Dual CESL technique traditional, to remove the high tensile stress silicon nitride in PMOS region and the high pressure stress silicon nitride in territory, nmos area, therefore, this technique has greatly increased process costs and process complexity.So the still Single CESL technique extensively adopting at present, adopts single step silicon nitride deposition process to form CESL layer (contact hole etching stop-layer).Generally speaking, because the electron mobility index in nmos device seems more crucial, so general Single CESL technique is exactly to adopt high tensile stress silicon nitride to form contact hole etching stop-layer in PMOS region and territory, nmos area simultaneously.
High tensile stress silicon nitride film (High Tensile Stress SiN) deposits and obtains in PECVD (plasma reinforced chemical vapor deposition system), and reactant is silane (SiH
4) and ammonia (NH
3), need to utilize radio-frequency excited plasma to maintain the carrying out of reaction.In the silicon nitride film forming due to this method, contain a large amount of H (hydrogen atom), its short texture, so that stress do not reach requirement, and 0.7Gpa only has an appointment.So, next also need film to carry out UV cure (ultraviolet light polymerization), utilize the hydrogen bond in broken up with UV light film, make hydrogen atom form hydrogen and separate out, and the dangling bonds Si-staying and N-can form Si-N key.Like this, the spacial framework of silicon nitride film changes, thereby can form the high tensile stress silicon nitride film that stress meets the demands.At present, the limiting range of stress that deposits the tensile stress silicon nitride film obtaining by PECVD is 1.7Gpa left and right (after ultraviolet light polymerization), can significantly improve the performance of NMOS.So, conventionally using this silicon nitride film as contact hole etching barrier layer, its thickness is generally 300～600A.
But, adopt Single CESL technique to form high tensile stress silicon nitride contact hole etching stop-layer in PMOS region and territory, nmos area simultaneously, and the existence of high tensile stress silicon nitride has adverse effect to the electrical property of PMOS device, therefore Single CESL technique is to sacrifice a kind of compromise algorithm that the hole mobility in PMOS device is cost after all.Therefore, how to avoid the negative influence of the high tensile stress silicon nitride deposition of single step to PMOS device, and avoid two step silicon nitrides to deposit the complexity that forms dual contact etching stopping layer process, become an important topic of current industry.
Summary of the invention
The object of the invention is to overcome the above-mentioned defect that prior art exists, a kind of manufacture method of dual contact etching stop layer is provided, by depositing high tensile stress silicon nitride layer as contact hole etching stop-layer on MOS device, deposited amorphous carbon-coating is as the protective layer of high tensile stress silicon nitride layer, and using the multilayer laminated ultraviolet light barrier layer as MOS device PMOS region alternately being formed by silicon nitride layer and silicon oxide layer, to MOS device PMOS, the high tensile stress silicon nitride layer in territory, nmos area carries out optionally ultraviolet light polymerization to be processed, realization is at PMOS, territory, nmos area has the high tensile stress silicon nitride dual contact etching stop layer of different tensile stresss, can avoid the negative influence of the high tensile stress silicon nitride deposition of single step to PMOS device hole mobility, can avoid again two step silicon nitride depositions to form the complexity of dual contact etching stopping layer process.
For achieving the above object, technical scheme of the present invention is as follows:
A manufacture method for dual contact etching stop layer, comprises the following steps:
Step 1: a MOS device is provided, deposits a floor height tensile stress silicon nitride layer as contact hole etching stop-layer on described MOS device;
Step 2: deposit one deck amorphous carbon layer as the protective layer of described high tensile stress silicon nitride layer on described high tensile stress silicon nitride layer;
Step 3: alternating deposit silicon nitride layer, silicon oxide layer successively on described amorphous carbon layer, form be comprised of described silicon nitride layer and described silicon oxide layer multilayer laminated, as ultraviolet light barrier layer;
Step 4: the described lamination in territory, described MOS device nmos area is removed;
Step 5: described high tensile stress silicon nitride layer is carried out to ultraviolet light polymerization processing;
Step 6: the described lamination in described MOS device PMOS region is removed, then, removed described amorphous carbon layer, to form the silicon nitride dual contact etching stop layer with different high tensile stresss on described MOS device.
In technique scheme, because PMOS region is still retaining be alternately comprised of silicon nitride layer and silicon oxide layer multilayer laminated in the process of ultraviolet light polymerization, and this multilayer laminated can be by thering is the medium interface of air, silicon nitride layer and the silicon oxide layer of different refractivity, ultraviolet light is reflected, light intensity in the process of the high tensile stress silicon nitride layer of ultraviolet light below arriving by multilayer laminated, amorphous carbon layer is progressively decayed.The number of repetition of silicon nitride layer and silicon oxide layer alternating deposit, has determined the ultraviolet light intensity of the high tensile stress silicon nitride layer of final arrival.So after ultraviolet light polymerization, the raising degree of the tensile stress of the high tensile stress silicon nitride layer in PMOS region will be subject to obvious impact.This relatively low tensile stress state has obviously reduced the adverse effect to PMOS device electrical performance.And for the high tensile stress silicon nitride layer in territory, nmos area, reason silicon nitride layer and silicon oxide layer alternately the multilayer laminated of composition are removed, so its ultraviolet light polymerization process can not be affected, after UV-curing metallization processes, the high tensile stress silicon nitride layer in this region can reach the ultimate tensile stress of 1.7Gpa left and right, can significantly improve the electron mobility in nmos device.
The present invention passes through the multilayer laminated ultraviolet light barrier layer as PMOS region being alternately comprised of silicon nitride layer and silicon oxide layer, high tensile stress silicon nitride layer to PMOS, territory, nmos area carries out optionally ultraviolet light polymerization process, realization has the silicon nitride dual contact etching stop layer of different high tensile stresss in PMOS, territory, nmos area, can on PMOS region, cover the relatively low high tensile stress silicon nitride layer of tensile stress, on territory, nmos area, cover the high tensile stress silicon nitride layer that tensile stress is relatively high.Therefore, the present invention can avoid the negative influence of the high tensile stress silicon nitride deposition of single step to PMOS device, can avoid again two step silicon nitride depositions to form the complexity of dual contact etching stopping layer process.And the dual contact etching stopping layer process that process of the present invention is relatively traditional is simpler, cost is lower.
Preferably, in step 1, the deposit thickness of described high tensile stress silicon nitride layer is 300～1000A.
Preferably, in step 2, the deposit thickness of described amorphous carbon layer is 1000～5000A.
Preferably, in step 3, the number of plies of the described silicon nitride layer in described lamination be 3 layers and more than, the number of plies of described silicon oxide layer be 2 layers and more than.
Preferably, in step 3, the superiors in described lamination are described silicon nitride layer.
Preferably, in step 3, the thickness of every layer of described silicon nitride layer is 100～300A.
Preferably, in step 3, the thickness of every layer of described silicon oxide layer is 100～300A.
Preferably, in step 4, adopt photoetching process, cover with photoresist the PMOS region of described MOS device, then, adopt dry etch process to remove the described lamination in territory, described MOS device nmos area.
Preferably, in step 5, adopt the ultraviolet light that wavelength is 190～400nm to carry out ultraviolet light polymerization processing to described high tensile stress silicon nitride layer.
Preferably, in step 6, first adopt plasma oxygen metallization processes to remove the described photoresist in described MOS device PMOS region, then adopt dry etch process to remove the described lamination in described MOS device PMOS region, finally adopt plasma oxygen metallization processes to remove described amorphous carbon layer.
From technique scheme, can find out, the present invention by depositing high tensile stress silicon nitride layer as contact hole etching stop-layer on MOS device, deposited amorphous carbon-coating is as the protective layer of high tensile stress silicon nitride layer, and on amorphous carbon layer, using the multilayer laminated ultraviolet light barrier layer as MOS device PMOS region alternately being formed by silicon nitride layer and silicon oxide layer, to MOS device PMOS, the high tensile stress silicon nitride layer in territory, nmos area carries out optionally ultraviolet light polymerization to be processed, obtain covering the relatively low high tensile stress silicon nitride layer of tensile stress on PMOS region, on territory, nmos area, cover the high tensile stress silicon nitride layer that tensile stress is relatively high, realization is at PMOS, territory, nmos area has the silicon nitride dual contact etching stop layer of different high tensile stresss, both can avoid the negative influence of the high tensile stress silicon nitride deposition of single step to PMOS device hole mobility, can avoid again two step silicon nitride depositions to form the complexity of dual contact etching stopping layer process.And the dual contact etching stopping layer process that process of the present invention is relatively traditional is simpler, cost is lower, thereby has the marked improvement that has promoted device electrical performance with lower cost.
Accompanying drawing explanation
Fig. 1 is the existing device architecture schematic diagram that forms heavily stressed silicon nitride film contact hole etching stop-layer on MOS device;
Fig. 2 is the flow chart of the manufacture method of a kind of dual contact etching stop layer of the present invention;
Fig. 3～Figure 11 makes the device architecture schematic diagram of dual contact etching stop layer according to the manufacture method of Fig. 2 in one embodiment of the invention;
Figure 12 is multilayer laminated partial structurtes enlarged diagram.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.Certainly the present invention is not limited to following specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
It should be noted that, in following embodiment, utilize the schematic diagram of Fig. 3～Figure 12 to carry out detailed statement to the device architecture of the manufacture method formation by dual contact etching stop layer of the present invention.When embodiments of the present invention are described in detail in detail, for convenience of explanation, each schematic diagram is not according to general scale and carried out local amplification and omission processing, therefore, should avoid usining this as limitation of the invention.
Refer to Fig. 2, Fig. 2 is the flow chart of the manufacture method of a kind of dual contact etching stop layer of the present invention.Meanwhile, ask control reference Fig. 3～Figure 11 and Figure 12, Fig. 3～Figure 11 makes the device architecture schematic diagram of dual contact etching stop layer according to the manufacture method of Fig. 2 in one embodiment of the invention; Figure 12 is as the multilayer laminated partial structurtes enlarged diagram of the silicon-nitride and silicon oxide on ultraviolet light barrier layer.The device architecture of illustrating in Fig. 3～Figure 11, corresponding with each making step in Fig. 2 respectively, so that the understanding to the inventive method.
As shown in Figure 2, the invention provides a kind of manufacture method of dual contact etching stop layer, comprising:
As shown in frame 1, step 1: a MOS device is provided, deposits a floor height tensile stress silicon nitride layer as contact hole etching stop-layer on described MOS device.
Please refer to Fig. 3, on the MOS device 3 having completed, deposit a floor height tensile stress silicon nitride layer 4 as contact hole etching stop-layer.The manufacture craft of MOS device 3 is identical with existing technique, and MOS device 3 has territory, nmos area 9 and PMOS region 8.Silicon nitride layer 4 can strengthen the formation of chemical vapour deposition (CVD) (PECVD) method deposition by using plasma, and reacting gas can comprise SiH
4(silane) and NH
3(ammonia), but be not limited to this.Deposit thickness is 300～1000A.Course of reaction need to utilize radio-frequency excited plasma to maintain the carrying out of reaction.As an example, the deposit thickness of silicon nitride layer 4 can be 600A, and now the stress of silicon nitride layer 4 is probably 0.7Gpa left and right.
As shown in frame 2, step 2: deposit one deck amorphous carbon layer as the protective layer of described high tensile stress silicon nitride layer on described high tensile stress silicon nitride layer.
Please refer to Fig. 4, on high tensile stress silicon nitride layer 4, deposit one deck amorphous carbon layer 5, as the protective layer of high tensile stress silicon nitride layer.In follow-up step; due to the ultraviolet light barrier layer (referring to hereinafter explanation) that need to remove on amorphous carbon layer; during for fear of removal ultraviolet light barrier layer, high tensile stress silicon nitride layer is damaged; thereby deposit this amorphous carbon layer 5; etching barrier layer as high tensile stress silicon nitride layer when removing ultraviolet light barrier layer, protects high tensile stress silicon nitride layer 4 films below.The thickness of amorphous carbon layer 5 can be 1000～5000A, can adopt existing process to generate.As an example, amorphous carbon layer 5 that can deposit thickness is 3000A on high tensile stress silicon nitride layer 4.
As shown in frame 3, step 3: alternating deposit silicon nitride layer, silicon oxide layer successively on described amorphous carbon layer, form be comprised of described silicon nitride layer and described silicon oxide layer multilayer laminated, as ultraviolet light barrier layer.
Please refer to Fig. 5, on amorphous carbon layer 5, deposition forms a lamination 6, the effect of this lamination 6 is while high tensile stress silicon nitride layer 4 being carried out to ultraviolet light polymerization processing in subsequent step, as the ultraviolet light barrier layer in PMOS region 8, to weaken ultraviolet light to the radiation light intensity of the high tensile stress silicon nitride layer 4 in PMOS region 8 (referring to hereinafter explanation).
Please refer to Figure 12, the lamination 6 in Fig. 5 is by silicon nitride layer and the silicon oxide layer of alternating deposit form successively.As a preferred embodiment of the present invention, lamination 6 is by amorphous carbon layer 5,3 of alternating deposit layers of silicon nitride layer 10-1,10-2,10-3 and 2 layers of silicon oxide layer 11-1,11-2 form multilayer laminated successively.The superiors in lamination 6 are silicon nitride layer 10-3.The thickness of every layer of silicon nitride layer is 100～300A; The thickness of every layer of silicon oxide layer is 100～300A.It should be noted that, in theory, in lamination 6, the alternately number of plies of silicon nitride layer and silicon oxide layer is more, to the blocking effect of ultraviolet light larger (it stops that mechanism will describe in detail later), but need to decide in conjunction with the designing requirement of device.Therefore,, as other optional embodiment of the present invention, lamination can form multilayer laminated by 3 layers of above silicon nitride layer and 2 layers of above silicon oxide layer; And the number of plies of silicon nitride layer and silicon oxide layer can be identical, the superiors in lamination now will become silicon oxide layer.
As shown in frame 4, step 4: the described lamination in territory, described MOS device nmos area is removed.
Please refer to Fig. 6, adopt photoetching process, on whole MOS device 3, carry out photoresist 7 coatings, above whole MOS device 3, the lamination 6 in territory, nmos area 9 and PMOS region 8 is covered.
Please refer to Fig. 7, by exposure imaging, the photoresist in territory, nmos area 97 is removed to (photoresist 7 that is illustrated as territory, nmos area 9 has been removed state), the lamination 6 in territory, nmos area 9 is come out, and 8 tops, PMOS region are still covered by photoresist 7.
Please refer to Fig. 8, adopt dry etch process, utilize fluorine-containing plasma gas etching to remove the lamination 6 (lamination 6 that is illustrated as territory, nmos area 9 has been removed state) in territory, nmos area 9.
As shown in frame 5, step 5: described high tensile stress silicon nitride layer is carried out to ultraviolet light polymerization processing.
Please refer to Fig. 9, under device state as shown in Figure 9, adopt the ultraviolet light that wavelength is 190～400nm, the ultraviolet light that for example wavelength is 193nm, carries out ultraviolet light polymerization processing (in figure, downward hollow arrow represents the direction of illumination of ultraviolet light) to high tensile stress silicon nitride layer.
Using plasma strengthens in the silicon nitride film that chemical gaseous phase depositing process forms and contains a large amount of H (hydrogen atom), its short texture, so that stress do not reach requirement, and 0.7Gpa only has an appointment.So, also need film to carry out UV cure (ultraviolet light polymerization), utilize the hydrogen bond in broken up with UV light film, make hydrogen atom form hydrogen and separate out, and the dangling bonds Si-staying and N-can form Si-N key.Like this, the spacial framework of silicon nitride film changes, thereby can form the silicon nitride film that the limiting range of stress is 1.7Gpa left and right, can significantly improve the performance of NMOS.
Because PMOS region 8 is still retaining be alternately comprised of silicon nitride layer and silicon oxide layer multilayer laminated 6 in the process of ultraviolet light polymerization, and this multilayer laminated 6 can by have different refractivity air,
The medium interface of silicon nitride layer and silicon oxide layer, reflects ultraviolet light, and light intensity in the process of the high tensile stress silicon nitride layer 4 of ultraviolet light below arriving by multilayer laminated 6, amorphous carbon layer 5 is progressively decayed.The number of repetition of silicon nitride layer and silicon oxide layer alternating deposit, has determined the ultraviolet light intensity of the high tensile stress silicon nitride layer of final arrival.
According to reflection of light principle, light can reflect in the interface of the different medium of two kinds of refractive indexes.When light beam approaches normal incidence (incidence angle approximates 90 degree), reflectivity calculates formula and is:
R＝(n1-n2)
2/(n1+n2)
2
Wherein, R represents reflectivity, and n1, n2 are respectively the true refractive indexes refractive index of vacuum (with respect to) of two media.
The have three layers lamination of silicon nitride layer 10-1,10-2,10-3 and 2 layers of silicon oxide layer 11-1,11-2 of the above-mentioned tool as shown in figure 12 of take is example, according to data with existing, under the ultraviolet light of 193nm wavelength, the refractive index of silicon nitride film is 2.7 left and right, silica is 1.5 left and right, amorphous carbon-film is 1.5 left and right, and air is 1.The above-mentioned reflectivity of data substitution is calculated to formula, can obtain the total transmitance of ultraviolet light when the transmitance (being 1-reflectivity) of each layer and ultraviolet light arrive at high tensile stress silicon nitride layer 4, as shown in the table:
As can be known from the table data, the ultraviolet light that finally can see through amorphous carbon-film only have 50% left and right of initial incident light, therefore arrive at the light intensity of the ultraviolet light in PMOS region 8, will decay closely half.So after ultraviolet light polymerization, the raising degree of the tensile stress of the high tensile stress silicon nitride layer 4 in PMOS region will be subject to obvious impact, can not reach the ultimate tensile stress state of 1.7Gpa.This relatively low tensile stress state has obviously reduced the adverse effect to PMOS device electrical performance.And for the high tensile stress silicon nitride layer in territory, nmos area, reason silicon nitride layer and silicon oxide layer alternately the multilayer laminated of composition are removed, so its ultraviolet light polymerization process can not be affected, after UV-curing metallization processes, the high tensile stress silicon nitride layer in this region (is used 4-1 mark herein by being converted into the high tensile stress silicon nitride layer 4-1 that can reach 1.7Gpa Derivative limit on the left or on the right tensile stress, with the high tensile stress silicon nitride layer 4 that there is relatively low tensile stress with PMOS region, distinguish), can significantly improve the electron mobility in nmos device.
As shown in frame 6, step 6: the described lamination in described MOS device PMOS region is removed, then, removed described amorphous carbon layer, to form the silicon nitride dual contact etching stop layer with different high tensile stresss on described MOS device.
Please refer to Figure 10, first adopt plasma oxygen metallization processes, utilize oxidizing gas for example oxygen excite the oxygen plasma gas of formation to remove the photoresist 7 (photoresist 7 that is illustrated as PMOS region 8 has been removed state) in MOS device PMOS region 8; Then, adopt dry etch process, utilize fluorine-containing plasma gas etching to remove the lamination 6 (lamination 6 that is illustrated as PMOS region 8 has been removed state) in PMOS region 8.
Finally, please refer to Figure 11, adopt plasma oxygen metallization processes, utilize oxidizing gas for example oxygen excite the oxygen plasma gas of formation to remove whole amorphous carbon layer 5 (be illustrated as amorphous carbon layer 5 and removed state), thereby on the territory, nmos area 9 of MOS device 3 and PMOS region 8 the final different silicon nitride dual contact etching stop layer of high tensile stress that has being formed with the high tensile stress silicon nitride layer 4-1 of tensile stress relatively high (can reach the limiting condition of about 1.7Gpa) and the high tensile stress silicon nitride layer 4 of tensile stress relatively low (being significantly less than 1.7Gpa) that forms.
In sum, the present invention passes through the multilayer laminated ultraviolet light barrier layer as MOS device PMOS region being alternately comprised of silicon nitride layer and silicon oxide layer, to MOS device PMOS, the high tensile stress silicon nitride layer in territory, nmos area carries out optionally ultraviolet light polymerization to be processed, obtain covering the relatively low high tensile stress silicon nitride layer of tensile stress on PMOS region, on territory, nmos area, cover the high tensile stress silicon nitride layer that tensile stress is relatively high, realization is at PMOS, territory, nmos area has the silicon nitride dual contact etching stop layer of different high tensile stresss, thereby both can avoid the negative influence of the high tensile stress silicon nitride deposition process of existing single step to PMOS device hole mobility, can avoid again two step silicon nitride depositions to form the complexity of dual contact etching stopping layer process.And the dual contact etching stopping layer process that process of the present invention is relatively traditional is simpler, cost is lower, the final electrical property that has promoted device with lower cost of realizing.
Above-described is only the preferred embodiments of the present invention; described embodiment is not in order to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. a manufacture method for dual contact etching stop layer, is characterized in that, comprises the following steps:
Step 1: a MOS device is provided, deposits a floor height tensile stress silicon nitride layer as contact hole etching stop-layer on described MOS device;
Step 2: deposit one deck amorphous carbon layer as the protective layer of described high tensile stress silicon nitride layer on described high tensile stress silicon nitride layer;
Step 3: alternating deposit silicon nitride layer, silicon oxide layer successively on described amorphous carbon layer, form be comprised of described silicon nitride layer and described silicon oxide layer multilayer laminated, as ultraviolet light barrier layer;
Step 4: the described lamination in territory, described MOS device nmos area is removed;
Step 5: described high tensile stress silicon nitride layer is carried out to ultraviolet light polymerization processing;
Step 6: the described lamination in described MOS device PMOS region is removed, then, removed described amorphous carbon layer, to form the silicon nitride dual contact etching stop layer with different high tensile stresss on described MOS device.
2. the manufacture method of dual contact etching stop layer according to claim 1, is characterized in that, in step 1, the deposit thickness of described high tensile stress silicon nitride layer is 300～1000A.
3. the manufacture method of dual contact etching stop layer according to claim 1, is characterized in that, in step 2, the deposit thickness of described amorphous carbon layer is 1000～5000A.
4. the manufacture method of dual contact etching stop layer according to claim 1, is characterized in that, in step 3, the number of plies of the described silicon nitride layer in described lamination be 3 layers and more than, the number of plies of described silicon oxide layer be 2 layers and more than.
5. according to the manufacture method of the dual contact etching stop layer described in claim 1 or 4, it is characterized in that, in step 3, the superiors in described lamination are described silicon nitride layer.
6. according to the manufacture method of the dual contact etching stop layer described in claim 1 or 4, it is characterized in that, in step 3, the thickness of every layer of described silicon nitride layer is 100～300A.
7. according to the manufacture method of the dual contact etching stop layer described in claim 1 or 4, it is characterized in that, in step 3, the thickness of every layer of described silicon oxide layer is 100～300A.
8. the manufacture method of dual contact etching stop layer according to claim 1, is characterized in that, in step 4, adopt photoetching process, cover with photoresist the PMOS region of described MOS device, then, adopt dry etch process to remove the described lamination in territory, described MOS device nmos area.
9. the manufacture method of dual contact etching stop layer according to claim 1, is characterized in that, in step 5, adopts the ultraviolet light that wavelength is 190～400nm to carry out ultraviolet light polymerization processing to described high tensile stress silicon nitride layer.
10. the manufacture method of dual contact etching stop layer according to claim 1, it is characterized in that, in step 6, first adopt plasma oxygen metallization processes to remove the described photoresist in described MOS device PMOS region, then adopt dry etch process to remove the described lamination in described MOS device PMOS region, finally adopt plasma oxygen metallization processes to remove described amorphous carbon layer.
Priority Applications (1)
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Cited By (3)
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| CN105118805A (en) * | 2015-07-30 | 2015-12-02 | 上海华力微电子有限公司 | Technical method for manufacturing dual contact etch stop layer |
| CN106706172A (en) * | 2015-11-12 | 2017-05-24 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
| CN107895724A (en) * | 2017-11-13 | 2018-04-10 | 中国科学院微电子研究所 | A kind of three-dimensional storage and preparation method thereof |
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| CN102664150A (en) * | 2012-05-28 | 2012-09-12 | 上海华力微电子有限公司 | Method for improving PMOS (P-channel Metal Oxide Semiconductor) performance in contact etch stop layer process |
| US20130175634A1 (en) * | 2010-10-28 | 2013-07-11 | International Business Machines Corporation | Structure and method for using high-k material as an etch stop layer in dual stress layer process |
| CN103579357A (en) * | 2012-07-18 | 2014-02-12 | 元太科技工业股份有限公司 | Semiconductor structure |
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| US20130175634A1 (en) * | 2010-10-28 | 2013-07-11 | International Business Machines Corporation | Structure and method for using high-k material as an etch stop layer in dual stress layer process |
| CN102664150A (en) * | 2012-05-28 | 2012-09-12 | 上海华力微电子有限公司 | Method for improving PMOS (P-channel Metal Oxide Semiconductor) performance in contact etch stop layer process |
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| CN105118805A (en) * | 2015-07-30 | 2015-12-02 | 上海华力微电子有限公司 | Technical method for manufacturing dual contact etch stop layer |
| CN106706172A (en) * | 2015-11-12 | 2017-05-24 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
| CN106706172B (en) * | 2015-11-12 | 2021-04-02 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
| CN107895724A (en) * | 2017-11-13 | 2018-04-10 | 中国科学院微电子研究所 | A kind of three-dimensional storage and preparation method thereof |
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| CN104201101B (en) | 2020-02-21 |
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