CN104184441A - Clock data recovery circuit - Google Patents
Clock data recovery circuit Download PDFInfo
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- CN104184441A CN104184441A CN201410423912.XA CN201410423912A CN104184441A CN 104184441 A CN104184441 A CN 104184441A CN 201410423912 A CN201410423912 A CN 201410423912A CN 104184441 A CN104184441 A CN 104184441A
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Abstract
A clock data recovery circuit achieves the clock data recovery function through a phase-locked loop or a delay locked loop. The clock data recovery circuit comprises a control voltage adjusting module, wherein the control voltage adjusting module is coupled to a clock frame selecting module in the phase-locked loop or the delay locked loop and is used for adjusting the control voltage in a preset voltage range. Through the clock data recovery circuit disclosed by the invention, whether the control voltage for controlling the delay time or the oscillation frequency is lower than the lower limit of the preset voltage range is judged by using the control voltage adjusting module, so that the 'locking' state can be avoided.
Description
Technical field
The present invention relates to a kind of clock-data recovery circuit, relate in particular to a kind of clock-data recovery circuit with anti-locking mechanism.
Background technology
Clock-data recovery circuit (Clock and Data Recovery circuit, CDR) is widely used on the device that various transfer of data are relevant.In clock-data recovery circuit, often by phase-locked loop (Phase-Locked Loop, PLL) or delay-locked loop (Delay-Locked Loop, DLL), reach the function of clock-data recovery.Yet phase-locked loop or delay-locked loop all the state of " locked " may occur in running, thereby and even cause stopping or mistake of the whole data transmission device of whole clock-data recovery circuit.Therefore, how avoiding " locked " state occurs, is a problem urgently to be resolved hurrily.
Summary of the invention
Because above problem, the present invention proposes a kind of clock-data recovery circuit, and when locked in judgement loop wherein, the whole clock-data recovery circuit of resetting, to attempt to allow loop wherein normally lock.
According to the disclosed a kind of clock-data recovery circuit of the one or more embodiment of the present invention, comprise clock pulse Postponement module, phase detecting module, clock pulse frame modeling piece and control voltage regulator module.Clock pulse Postponement module, in order to receive with reference to clock pulse and to postpone after the time of delay, produces the first clock pulse.Phase detecting module is coupled to clock pulse Postponement module, in order to compare with reference to the phase difference between clock pulse and the first clock pulse.Clock pulse frame modeling piece is coupled to phase detecting module and clock pulse Postponement module, according to phase difference, to produce, controls voltage, and described control voltage is in order to control aforementioned time of delay.Control voltage regulator module and be coupled to clock pulse frame modeling piece and clock pulse Postponement module, in order to adjust, control voltage in a predeterminated voltage scope.In one embodiment of the invention, when being less than the lower of predeterminated voltage scope, control voltage prescribes a time limit, and control voltage regulator module and at least promote control voltage to the upper limit of predeterminated voltage scope.In another embodiment of the present invention, when being greater than the upper of predeterminated voltage scope, control voltage prescribes a time limit, and control voltage regulator module and at least reduce control voltage to the lower limit of predeterminated voltage scope.
According to the disclosed another kind of clock-data recovery circuit of the one or more embodiment of the present invention, comprise oscillation module, phase frequency detection module, clock pulse frame modeling piece and control voltage regulator module.Oscillation module is controlled by control voltage, to produce the second clock pulse.Phase frequency detection module is coupled to oscillation module, in order to compare one with reference to phase difference and difference on the frequency between clock pulse and the second clock pulse.Clock pulse frame modeling piece is coupled to phase frequency detection module and oscillation module, according to phase difference and difference on the frequency to produce aforementioned control voltage.Control voltage regulator module and be coupled to clock pulse frame modeling piece and oscillation module, in order to adjust, control voltage in a predeterminated voltage scope.Wherein when control voltage is less than the lower of predeterminated voltage scope, prescribe a time limit, control voltage regulator module lifting and control voltage to the upper limit of predeterminated voltage scope.
By clock-data recovery circuit disclosed in this invention, utilize to control voltage regulator module judgement and be used for the control voltage of control lag time or frequency of oscillation whether lower than the lower limit of predeterminated voltage scope.And when controlling voltage, lower than the lower of predeterminated voltage scope, prescribe a time limit, by controlling voltage, be increased to the upper limit of predeterminated voltage scope, and attempt thus to allow loop again reach locking.Can avoid thus occurring " locked " state.
The explanation of the above explanation about content of the present invention and following execution mode is in order to demonstration and explain spirit of the present invention and principle, and provides claim scope of the present invention further to explain.
Accompanying drawing explanation
Fig. 1 is the clock-data recovery circuit function calcspar according to one embodiment of the invention.
Fig. 2 is the clock pulse Postponement module circuit diagram according to one embodiment of the invention.
Fig. 3 is the control voltage regulator module circuit diagram according to one embodiment of the invention.
Fig. 4 is the clock-data recovery circuit function calcspar according to one embodiment of the invention.
Fig. 5 is the sequential chart according to each signal in the clock-data recovery circuit of one embodiment of the invention.
1,4 clock-data recovery circuit
11 clock pulse Postponement modules
13 phase detecting module
15,45 clock pulse frame modeling pieces
17,47 control voltage regulator module
171 switch elements
173,175 comparators
177 latchs
178,179,182 inverters
180,181 NAND gate
183 transistors
185 temperature compensation units
41 oscillation modules
43 phase frequency detection modules
G
nDearth terminal
LOCK locking signal
R
17resistance
T
1very first time point
T
2the second time point
T3 the 3rd time point
V
ctrlcontrol voltage
V
dDhigh voltage end points
V
rEFHthe first reference voltage
V
rEFLthe second reference voltage
V
xLOCKlocked index signal
V
lOCKlock indication signal
Q output
S, R input
Mode1, mode2 mode signal
Embodiment
In execution mode, describe below detailed features of the present invention and advantage in detail, its content is enough to make any those skilled in the art understand technology contents of the present invention and implement according to this, and according to the disclosed content of this specification, claim and accompanying drawing, any those skilled in the art can understand object and the advantage that the present invention is relevant easily.Following embodiment further describes viewpoint of the present invention, but non-to limit anyways category of the present invention.
About please refer to Fig. 1 according to the disclosed a kind of clock-data recovery circuit of one embodiment of the invention (clock-data recovery circuit, DCR), it is the clock-data recovery circuit function calcspar according to one embodiment of the invention.As shown in Figure 1, clock-data recovery circuit 1 can comprise clock pulse Postponement module 11, phase detecting module 13, clock pulse frame modeling piece 15 and control voltage regulator module 17.Wherein phase detecting module 13 is coupled to clock pulse Postponement module 11, and clock pulse frame modeling piece 15 is coupled to phase detecting module 13 and clock pulse Postponement module 11, controls voltage regulator module 17 and is coupled to clock pulse frame modeling piece 15 and clock pulse Postponement module 11.
Clock pulse Postponement module 11, in order to receive with reference to clock pulse and to postpone after the time of delay, produces the first clock pulse.In realization, please refer to Fig. 2, it is the clock pulse Postponement module circuit diagram according to one embodiment of the invention.As shown in Figure 2, clock pulse Postponement module 11 can comprise the voltage-controlled delay unit (voltage control delay cell) 111 to 115 of three series connection.With voltage-controlled delay unit 111 for instance, the transmission delay of voltage-controlled delay unit 111 (propagation delay) can according to one control voltage and 0.1 how second (nano-second) change between how second with 0.5.Therefore how second how second clock pulse Postponement module 11 can be controlled by control voltage, and provide 0.3 to 1.5 time of delays.How second that is to say, when clock pulse Postponement module 11 is controlled by, controls voltage and how second 1.0 time of delays were provided, clock pulse Postponement module 11 produces the first clock pulse after receiving with reference to clock pulse, and send the first clock pulse in 1.0 after.
Phase detecting module 13 in order to relatively with reference to clock pulse and the first clock pulse to obtain with reference to the phase difference between clock pulse and the first clock pulse.In one implementation, phase detecting module 13 can comprise an XOR gate (exclusive-or gate), and two inputs of this XOR gate are used for respectively receiving with reference to clock pulse and the first clock pulse.And when different with the logic current potential of the first clock pulse with reference to the logic current potential (logic level) of clock pulse time, the logic current potential of the output signal of this XOR gate is high, when the logic current potential of the logic current potential with reference to clock pulse and the first clock pulse is identical, the logic current potential of the output signal of this XOR gate is low.Thus, can be the length of high time interval by the logic current potential of this output signal, judge and calculate the first clock pulse and with reference to the phase difference between clock pulse.
Clock pulse frame modeling piece 15 is controlled voltage according to phase difference to produce, and described control voltage is transferred to clock pulse Postponement module 11 by being coupled to a voltage node of clock pulse Postponement module 11, to control the time of delay of clock pulse Postponement module 11.In one embodiment, clock pulse frame modeling piece 15 can comprise a charge pump (charge pump) and a loop filter (loop filter).Charge pump is electrically connected to phase detecting module 13 to decide the time length of loop filter being injected or being extracted out electric charge (electric current) according to phase difference, loop filter is corresponding adjustment on one of them voltage node therefore, pass to the control voltage of clock pulse Postponement module 11.
Control voltage regulator module 17 and control voltage in a predeterminated voltage scope in order to adjust.In an embodiment, when being less than the lower of this predeterminated voltage scope, this control voltage prescribes a time limit, and this control voltage regulator module at least promotes this control voltage to the upper limit of this predeterminated voltage scope.Particularly, in this embodiment, control voltage regulator module 17 by will controlling voltage and be promoted to the upper limit of predeterminated voltage scope by being used in clock pulse frame modeling piece 15 that voltage node of controlling voltage and sending to clock pulse Postponement module 11 is couple to a high voltage end points.In another embodiment, when being greater than the upper of this predeterminated voltage scope, this control voltage prescribes a time limit, and this control voltage regulator module at least reduces this control voltage to the lower limit of this predeterminated voltage scope.Particularly, in this embodiment, control voltage regulator module 17 by will controlling voltage and be promoted to the upper limit of predeterminated voltage scope by being used in clock pulse frame modeling piece 15 that voltage node of controlling voltage and sending to clock pulse Postponement module 11 is couple to a low-voltage end points.
To control voltage regulator module 17, that voltage node being used in clock pulse frame modeling piece 15 controlling voltage and send to clock pulse Postponement module 11 is couple to a high voltage end points below, the embodiment that controls voltage and be promoted to the upper limit of predeterminated voltage scope is illustrated to its function mode.Specifically, please refer to Fig. 3, it is the control voltage regulator module circuit diagram according to one embodiment of the invention.As shown in Figure 3, control voltage regulator module 17 and can comprise switch element 171, comparator 173, comparator 175 and latch (latch) 177.Wherein the first end 171a of switch element 171 is coupled to high voltage end points V
dD, the second end 171b of switch element 171 is coupled to aforesaid voltage node to be used for optionally controlling voltage V
ctrland between high voltage end points, set up electrical path, make to control voltage V
ctrldrawn high.The negative input end of comparator 173 is connected to aforesaid voltage node, and the positive input terminal of comparator 173 is connected to a voltage source to receive the first reference voltage V
rEFH.The positive input terminal of comparator 175 is connected to aforesaid voltage node, and the negative input end of comparator 175 is connected to a voltage source to receive the second reference voltage V
rEFL.
Comparator 173 is used for comparison the first reference voltage V
rEFHwith control voltage V
ctrl.And comparator 175 is used for comparison the second reference voltage V
rEFLwith control voltage V
ctrl.Thus, can obtain altogether two comparative results from comparator 173 and comparator 175, from these two comparative results, learn and control voltage V
ctrlmagnitude of voltage whether between the first reference voltage V
rEFHmagnitude of voltage and the second reference voltage V
rEFLmagnitude of voltage between.That is to say, if the first reference voltage V
rEFHmagnitude of voltage be greater than the second reference voltage V
rEFLmagnitude of voltage, the upper limit of described predeterminated voltage scope can be the first reference voltage V
rEFHand lower limit can be the second reference voltage V
rEFL.Clearer and more definite, when controlling voltage V
ctrlbe greater than the first reference voltage V
rEFHthe logic current potential of the output voltage of comparator 173 is low-voltage, and simultaneously because control voltage V
ctrlbe greater than the second reference voltage V
rEFLtherefore the output voltage logic current potential of comparator 175 is high voltage.When controlling voltage V
ctrlbetween the first reference voltage V
rEFHwith the second reference voltage V
rEFLbetween, the logic current potential of the output voltage of comparator 173 is high voltage, and the output voltage logic current potential of comparator 175 is high voltage.When controlling voltage V
ctrlbe less than the second reference voltage V
rEFLthe logic current potential of the output voltage of comparator 173 is high voltage, and the output voltage logic current potential of comparator 175 is low-voltage.The logic current potential of the voltage that therefore can export by two comparators, judges and controls voltage V
ctrlwhether between two reference voltages.
The input S of latch (Latch) 177 receives aforementioned comparator 173 comparative results, and the input R of latch 177 receives the comparative result of aforementioned comparator 175, the output Q of the namely logic current potential of the output voltage of two comparators, and latch 177 is coupled to the control end 171c of switch element 171.Thus, latch 177 according to the comparative result of aforementioned comparator 173 comparative results and comparator 175 optionally control switch unit 177 conducting whether.In a specific embodiment, please with reference to Fig. 3 and following table one, wherein table one is the input and output truth table according to the latch of one embodiment of the invention.
| S | R | Q n+1 |
| 0 | 0 | Undefined (can not occur) |
| 0 | 1 | 0 |
| 1 | 1 | Q n |
| 1 | 0 | 1 |
Table one
By as the truth table of table one, as shown in Figure 3 the input S of latch 177 is couple to the output of comparator 173, the input R of latch 177 is couple to the output of comparator 175, the output Q of latch 177 also can be coupled to the input of an inverter (inverter) 178, and the output of inverter 178 is coupled to the control end 171c of switch element 171.If when switch element 171 is a P type metal oxide field-effect transistor as shown in Figure 3, when controlling voltage V
ctrlbe less than the second reference voltage V
rEFLtime because the logic current potential of the output of inverter 178 can be low-voltage, so switch element 171 can be switched at high voltage end points V
dDand between described voltage node, form electrical path, thereby will control voltage V
ctrlmagnitude of voltage be pulled to and high voltage end points V
dDmagnitude of voltage approach.Then, when controlling voltage V
ctrlmagnitude of voltage drawn high less times greater than the first reference voltage V
rEFHmagnitude of voltage time, as above-mentioned table one, can know that the voltage potential of the output Q of latch 177 can be low-voltage, thereby the logic current potential of the output of the inverter making 178 can be high voltage.Therefore switch element 171 can be cut off (cut-off), therefore from high voltage end points V
dDelectrical path to aforesaid voltage node is interrupted, the control voltage V on aforesaid voltage node
ctrlmagnitude of voltage be therefore maintained at a little higher than the first reference voltage V
rEFHmagnitude of voltage, equal thus whole clock-data recovery circuit 1 and be reset.Afterwards when phase detecting module 13 and clock pulse frame modeling piece 15 restart according to adjusting control voltage V with reference to clock pulse and the first clock pulse
ctrltime, control voltage V
ctrlmagnitude of voltage can be dragged down, and between the first reference voltage V
rEFHwith the second reference voltage V
rEFLbetween, now according to the truth table of table one, because the voltage potential of the output Q of latch 177 can continue previous voltage potential, so the voltage potential of the output of inverter 178 can remain on high voltage, therefore switch element 171 can not be switched in this " normal lock-in range ".In another embodiment, also can directly the output Q ' (not illustrating) of bolt lock device 177 be used for controlling aforementioned switches unit 171.
In one embodiment of the invention, control inverter 179, NAND gate 180, NAND gate 181, inverter 182, transistor 183 and resistance R that voltage regulator module 17 can also comprise the output that is coupled to inverter 178
17.The output that wherein NAND gate 180 input is coupled to inverter 179 is to receive lock indication signal V
lOCK, and another input is coupled to a mode signal mode1.An input of NAND gate 181 is coupled to the output of NAND gate 180, and another input is coupled to a mode signal mode2.The input of inverter 182 is coupled to the output of NAND gate 181, and the output of inverter 182 is coupled to the control end of transistor 183.One end of transistor 183 is coupled to earth terminal G
nD, and the other end of transistor 183 and high voltage end points V
dDbetween coupled resistance R
17, export thus locking signal LOCK.When clock pulse data recovery circuit 1 occur locked, according to lock indication signal V
lOCK, mode signal mode1 and mode signal mode2 can adjust locking signal LOCK, sends the reference clock pulse that is easy to locking with the device request to outside.
In yet another embodiment of the invention, as shown in Figure 3, control voltage regulator module 17 and can also comprise that is used to provide a first reference voltage V
rEFHwith the second reference voltage V
rEFLtemperature compensation unit 185.More particularly, in this embodiment, the first reference voltage V
rEFHwith the second reference voltage V
rEFLnot definite value, and can change with temperature.In a kind of implementation, temperature compensation unit 185 is an energy gap reference voltage circuit (bandgap reference), and the relation of its output voltage values and temperature can be curve or conic section.In another kind of implementation, temperature compensation unit 185 can comprise temperature sensor, a control circuit, a digital analog converter and a memory element.Wherein temperature sensor, memory element and digital analog converter are all electrically connected with control circuit.Temperature sensor is in order to the temperature of the environment at sensing clock-data recovery circuit place.In memory element, can store the first reference voltage V
rEFHthe table of comparisons and the second reference voltage V with the relation of temperature
rEFLthe table of comparisons with the relation of temperature.Two described tables of comparisons can be designed and store according to actual amount plan result in advance by the designer of clock-data recovery circuit.
Control circuit receives after the temperature that temperature sensor senses, and finds the first corresponding reference voltage V from memory element
rEFHmagnitude of voltage and the second reference voltage V
rEFLmagnitude of voltage, then control circuit accordingly control figure analog converter export the first reference voltage V
rEFHwith the second reference voltage V
rEFL.In this embodiment, because the first reference voltage V
rEFHwith the second reference voltage V
rEFLcan change with temperature, so predeterminated voltage scope also can change with temperature.So clock-data recovery circuit is under the environment of high temperature or low temperature, the change that predeterminated voltage scope also can be corresponding, thus more can adapt to hot environment or low temperature environment.
According to the disclosed another kind of clock-data recovery circuit of one embodiment of the invention, please refer to Fig. 4, it is the clock-data recovery circuit function calcspar according to one embodiment of the invention.As shown in Figure 4, clock-data recovery circuit 4 can comprise oscillation module 41, phase frequency detection module 43, clock pulse frame modeling piece 45 and control voltage regulator module 47.Phase frequency detection module 43 is coupled to oscillation module 41, and clock pulse frame modeling piece 45 is coupled to phase frequency detection module 43 and oscillation module 41, controls voltage regulator module 47 and is coupled to clock pulse frame modeling piece 45 and oscillation module 41.
Oscillation module 41 is controlled by control voltage, to produce the second clock pulse.Particularly, oscillation module 41 can be a voltage controlled oscillator (voltage control oscillator, VCO).Ins and outs about voltage controlled oscillator (VCO) repeat no more in this.
Phase frequency detection module 43 is in order to compare one with reference to phase difference and difference on the frequency between clock pulse and the second clock pulse.In the general practice, between the output of oscillation module 41 and phase frequency detection module 43, can also couple a frequency eliminator (frequency divider), be used for the second clock pulse frequency elimination, and phase frequency detection module 43 is relatively by the clock pulse after frequency elimination and with reference to the phase difference between clock pulse and difference on the frequency, implementation method is roughly similar to aforementioned phase detecting module 13, in this, repeats no more.
Clock pulse frame modeling piece 45 according to phase difference and difference on the frequency to produce aforementioned control voltage.Control voltage regulator module 47 and control voltage in a predeterminated voltage scope in order to adjust.Wherein when control voltage is less than the lower of predeterminated voltage scope, prescribe a time limit, control voltage regulator module lifting and control voltage to the upper limit of predeterminated voltage scope.Implementation method is similar to respectively aforementioned clock pulse frame modeling piece 15 and aforementioned control voltage regulator module 17, therefore repeats no more.
Next, please with reference to Fig. 1, Fig. 3 and Fig. 5, with the effect in explanation the present invention realization, wherein Fig. 5 is the sequential chart according to each signal in the clock-data recovery circuit of one embodiment of the invention.As shown in Figure 5, at very first time point T
1time, owing to being interfered in system with reference to clock pulse CLKREF and the first clock pulse CLK1, cause phase detecting module 13 normal phase difference can not be detected, therefore cause controlling voltage V
ctrlmagnitude of voltage since the abnormal decline of very first time point, finally at the second time point T
2time, control voltage V
ctrl-magnitude of voltage drop to lower than the second reference voltage V
rEFLmagnitude of voltage.Therefore, at the second time point T
2start, control the output signal of the output Q of the latch 177 in voltage regulator module 17, namely " locked index signal V
xLOCK" logic current potential become high voltage, represent that now whole clock-data recovery circuit 1 has occurred locked.Therefore the switch element 171 of controlling in voltage regulator module 17 is switched on, and in clock pulse frame modeling piece 15, is used for being coupled to voltage node and the high voltage end points V of clock pulse Postponement module 11
dDbetween form electrical path, therefore can from Fig. 5, see and control voltage V
ctrlmagnitude of voltage from the second time point T
2left and right starts to rise.And to during the 3rd time point T3, control voltage V
ctrlmagnitude of voltage be just greater than the first reference voltage V
rEFHmagnitude of voltage, locked index signal V now
xLOCKlogic current potential become low-voltage, so switch element 171 is cut off, and makes from high voltage end points V
dDto controlling voltage V
ctrlelectrical path between the voltage node at place is interrupted, and namely controls voltage regulator module 17 and stops " replacement " control voltage V
ctrl, and again attempt to adjust control voltage V by phase detecting module 13 and clock pulse frame modeling piece 15
ctrlso that whole clock-data recovery circuit 1 relocks.
By clock-data recovery circuit disclosed in this invention, utilize to control voltage regulator module judgement and be used for the control voltage of control lag time or frequency of oscillation whether lower than the lower limit of predeterminated voltage scope.And when controlling voltage, lower than the lower of predeterminated voltage scope, prescribe a time limit, by controlling voltage, be increased to the upper limit of predeterminated voltage scope, and attempt thus to allow loop again reach locking.
Although the present invention with aforesaid embodiment openly as above, yet it is not in order to limit the present invention.Without departing from the spirit and scope of the present invention, the change of doing and retouching, all belong to scope of patent protection of the present invention.The protection range defining about the present invention please refer to appended claim.
Claims (18)
1. a clock-data recovery circuit, comprising:
One clock pulse Postponement module, in order to receive one with reference to clock pulse and to postpone after the time of delay, produces one first clock pulse;
One phase detecting module, couples this clock pulse Postponement module, in order to relatively this with reference to the phase difference between clock pulse and this first clock pulse;
One clock pulse frame modeling piece, couples this phase detecting module and this clock pulse Postponement module, and according to this phase difference, to produce a control voltage, this control voltage is in order to control this time of delay; And
One controls voltage regulator module, couples this clock pulse frame modeling piece and this clock pulse Postponement module, in order to adjust this control voltage in a predeterminated voltage scope.
2. clock-data recovery circuit as claimed in claim 1, wherein between this clock pulse Postponement module and this clock pulse frame modeling piece, definition has a voltage node, this clock pulse frame modeling piece transmits this control voltage to this clock pulse Postponement module through this voltage node, and this control voltage regulator module couples this voltage node.
3. clock-data recovery circuit as claimed in claim 2, wherein this control voltage regulator module is optionally coupled to this voltage node one high voltage end points.
4. clock-data recovery circuit as claimed in claim 3, wherein this control voltage regulator module comprises:
One switch element, has a control end, a first end and one second end, and this first end is coupled to this high voltage end points, and this second end couples this voltage node;
One first comparator, in order to receive and to compare one first reference voltage and this control voltage;
One second comparator, in order to receive and to compare one second reference voltage and this control voltage; And
One latch, couples this control end, this first comparator and this second comparator, receives respectively the comparative result of this first comparator and this second comparator, according to this this switch element of conducting optionally;
Wherein this predeterminated voltage scope on be limited to this first reference voltage, under this predeterminated voltage scope, be limited to this second reference voltage.
5. clock-data recovery circuit as claimed in claim 4, wherein when this control voltage is less than this first reference voltage and this second reference voltage, this this switch element of latch conducting.
6. clock-data recovery circuit as claimed in claim 4, wherein, when this control voltage is greater than this first reference voltage and this second reference voltage, this latch ends this switch element.
7. clock-data recovery circuit as claimed in claim 4, wherein this control voltage regulator module also comprises a temperature compensation unit, this temperature compensation unit is electrically coupled to this first comparator and this second comparator, this temperature compensation unit, in order to according to an ambient temperature, is adjusted this first reference voltage and this second reference voltage.
8. clock-data recovery circuit as claimed in claim 1, wherein prescribes a time limit when this control voltage is less than the lower of this predeterminated voltage scope, and this control voltage regulator module at least promotes this control voltage to the upper limit of this predeterminated voltage scope.
9. clock-data recovery circuit as claimed in claim 1, wherein prescribes a time limit when this control voltage is greater than the upper of this predeterminated voltage scope, and this control voltage regulator module at least reduces this control voltage to the lower limit of this predeterminated voltage scope.
10. a clock-data recovery circuit, comprising:
One oscillation module, is controlled by a control voltage, to produce one second clock pulse;
One phase frequency detection module, couples this oscillation module, in order to compare one with reference to a phase difference and a difference on the frequency between clock pulse and this second clock pulse;
One clock pulse frame modeling piece, couples this phase frequency detection module and this oscillation module, according to this phase difference and this difference on the frequency to produce this control voltage; And
One controls voltage regulator module, couples this clock pulse frame modeling piece and this oscillation module, in order to adjust this control voltage in a predeterminated voltage scope.
11. clock-data recovery circuit as claimed in claim 10, wherein between this oscillation module and this clock pulse frame modeling piece, definition has a voltage node, this clock pulse frame modeling piece transmits this control voltage to this oscillation module through this voltage node, and this control voltage regulator module couples this voltage node.
12. clock-data recovery circuit as claimed in claim 11, wherein this control voltage regulator module is optionally coupled to this voltage node one high voltage end points.
13. clock-data recovery circuit as claimed in claim 12, wherein this control voltage regulator module comprises:
One switch element, has a control end, a first end and one second end, and this first end is coupled to this high voltage end points, and this second end couples this voltage node;
One first comparator, in order to receive and to compare one first reference voltage and this control voltage;
One second comparator, in order to receive and to compare one second reference voltage and this control voltage; And
One latch, couples this control end, this first comparator and this second comparator, receives respectively the comparative result of this first comparator and this second comparator, according to this this switch element of conducting optionally;
Wherein this predeterminated voltage scope on be limited to this first reference voltage, under this predeterminated voltage scope, be limited to this second reference voltage.
14. clock-data recovery circuit as claimed in claim 13, wherein when this control voltage is less than this first reference voltage and this second reference voltage, this this switch element of latch conducting.
15. clock-data recovery circuit as claimed in claim 13, wherein, when this control voltage is greater than this first reference voltage and this second reference voltage, this latch ends this switch element.
16. clock-data recovery circuit as claimed in claim 13, wherein this control voltage regulator module also comprises a temperature compensation unit, this temperature compensation unit is electrically coupled to this first comparator and this second comparator, this temperature compensation unit, in order to according to an ambient temperature, is adjusted this first reference voltage and this second reference voltage.
17. clock-data recovery circuit as claimed in claim 10, wherein prescribe a time limit when this control voltage is less than the lower of this predeterminated voltage scope, and this control voltage regulator module at least promotes this control voltage to the upper limit of this predeterminated voltage scope.
18. clock-data recovery circuit as claimed in claim 10, wherein prescribe a time limit when this control voltage is greater than the upper of this predeterminated voltage scope, and this control voltage regulator module at least reduces this control voltage to the lower limit of this predeterminated voltage scope.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103119768A TWI542157B (en) | 2014-06-06 | 2014-06-06 | Clock and data recovery circuit |
| TW103119768 | 2014-06-06 |
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| Publication Number | Publication Date |
|---|---|
| CN104184441A true CN104184441A (en) | 2014-12-03 |
| CN104184441B CN104184441B (en) | 2017-07-18 |
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| CN106685202A (en) * | 2015-11-09 | 2017-05-17 | 智原科技股份有限公司 | Anti-locking circuit of voltage regulator and related power supply system thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI699989B (en) * | 2019-07-22 | 2020-07-21 | 創意電子股份有限公司 | Clock data recovery device and method |
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| CN101527567A (en) * | 2008-03-06 | 2009-09-09 | 瑞昱半导体股份有限公司 | Clock and data recovery circuit |
| CN101777911A (en) * | 2010-01-08 | 2010-07-14 | 智原科技股份有限公司 | Clock data restorer |
| CN102655402A (en) * | 2011-03-01 | 2012-09-05 | 瑞昱半导体股份有限公司 | Transmitter-receiver device, voltage control oscillator and control method thereof |
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| US6928128B1 (en) * | 1999-05-03 | 2005-08-09 | Rambus Inc. | Clock alignment circuit having a self regulating voltage supply |
| CN101527567A (en) * | 2008-03-06 | 2009-09-09 | 瑞昱半导体股份有限公司 | Clock and data recovery circuit |
| CN101777911A (en) * | 2010-01-08 | 2010-07-14 | 智原科技股份有限公司 | Clock data restorer |
| CN102655402A (en) * | 2011-03-01 | 2012-09-05 | 瑞昱半导体股份有限公司 | Transmitter-receiver device, voltage control oscillator and control method thereof |
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| CN106685202A (en) * | 2015-11-09 | 2017-05-17 | 智原科技股份有限公司 | Anti-locking circuit of voltage regulator and related power supply system thereof |
| CN106685202B (en) * | 2015-11-09 | 2019-03-12 | 智原科技股份有限公司 | Anti-locking circuit of voltage regulator and related power supply system thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201547209A (en) | 2015-12-16 |
| CN104184441B (en) | 2017-07-18 |
| TWI542157B (en) | 2016-07-11 |
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