CN104183595B - Gate dielectric layer protection - Google Patents
Gate dielectric layer protection Download PDFInfo
- Publication number
- CN104183595B CN104183595B CN201310189992.2A CN201310189992A CN104183595B CN 104183595 B CN104183595 B CN 104183595B CN 201310189992 A CN201310189992 A CN 201310189992A CN 104183595 B CN104183595 B CN 104183595B
- Authority
- CN
- China
- Prior art keywords
- transistor
- coupled
- biasing
- path
- gate dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses gate dielectric layer protection. A gate dielectric layer protection circuit is used to be coupled onto a risk transistor for realizing gate dielectric layer protection. The protection circuit is started to enable voltage VDIFF across two ends of the gate dielectric layer to be reduced to be lower than breakdown voltage VBD. When an electrostatic discharge event is detected, the protection circuit is started. The protection circuit provides protection or electrostatic discharge bias to enable VDIFF to be reduced to be lower than VBD.
Description
Technical field
The present invention is on a kind of protection of gate dielectric.
Background technology
High pressure accumulation betides static discharge（electrostatic discharge；ESD）Integrated circuit during event
（integrated circuit；IC）Input and output（input/output；I/O）Pad.High pressure accumulation can cause input stage
The gate dielectric of transistor is damaged.If for example, the grid of the input stage transistor to underlayer voltage is more than the gate dielectric
Breakdown voltage（VBD）, then the transistor may be made to produce defect.
Protecting the conventional art of gate dielectric includes using clamp circuit（clamping circuit）To limit the grid
The voltage at pole dielectric layer two ends.But, protection of the conventional art to the gate dielectric of more recent technology is not very effective.Its reason
It is the breakdown voltage V of the trigger voltage more than the gate dielectric of the clamp circuitBD.For example, opening (switch on) pincers
During the circuit of position, the voltage at the gate dielectric two ends has been more than VBD。
It is higher than V with the voltage for fully avoiding the gate dielectric two ends it is therefore desirable to provide gate dielectric protectionBD。
The content of the invention
The method that embodiments of the invention are usually directed to semiconductor device and forming apparatus.In one embodiment, disclose
A kind of device.The device includes transistor, and it has the grid on substrate.The grid includes being located at gate dielectric top
Gate electrode.The device also includes being coupled to the gate dielectric protection module of the transistor.The gate dielectric protects mould
Block provides protection biasing (bias) when starting, by the voltage difference between the grid and substrate（VDIFF）It is brought down below the grid
The breakdown voltage of dielectric layer（VBD）.
In another embodiment, there is provided a kind of method of forming apparatus.The method includes forming transistor, the crystal pipe
There is the grid on substrate.The grid includes the gate electrode above gate dielectric.The method also includes forming coupling
It is connected to the gate dielectric protection module of the transistor.The gate dielectric protection module provides protection biasing when starting, with
By the voltage difference between the grid and substrate（VDIFF）It is brought down below the breakdown voltage of the gate dielectric（VBD）.
In another embodiment, a kind of method for protecting gate dielectric is disclosed.The method includes providing risk transistor
(transistor at risk).Formation is coupled to the protection module of the risk transistor.Start the protection module to provide guarantor
Shield biasing, so as to by the voltage difference between the grid and substrate of the risk transistor（VDIFF）It is brought down below the risk transistor
The breakdown voltage of gate dielectric（VBD）.
After with reference to following explanation and accompanying drawing, the above-mentioned and other advantages and features of embodiment disclosed herein will
Become more fully apparent.Furthermore, it is to be understood that the feature of different embodiments described here and not having to be mutually exclusive, but can make various
Combination and arrangement.
Brief description of the drawings
The reference being similar in accompanying drawing typically represents the same components in different views.In addition, those accompanying drawings and differing
Fixed drawn to scale, it focuses on illustrating principle of the invention.In the following description, referring to the drawings to difference of the invention
Embodiment is described, wherein：
Fig. 1 shows the block diagram of the part of the embodiment of a device；
Fig. 2 a to Fig. 2 b show the embodiment of gate dielectric protection module；And
Fig. 3 a to Fig. 3 d show the different embodiments of esd protection circuit.
Specific embodiment
Embodiments of the invention are usually directed to semiconductor device.In one embodiment, those devices include protection module.Example
Such as, the gate dielectric that the protection module is started during esd event to protect risk transistor exempts from esd event damage.
For example, those devices can be any type of semiconductor device, such as integrated circuit（IC）.Those integrated circuits may be included in example
Such as electronic product, computer, mobile phone and personal digital assistant（personal digital assistant；PDA）In or and its
It is used together.Those devices also may be included in other types of product.
The part of the embodiment of Fig. 1 display devices 100.As illustrated, the part includes internal circuit or unit 120.Should
Unit is coupled between first and second power path 102,104.The first power path can be VDD（Operating voltage）And this
Two power paths can be VSS（Ground connection）.It is also possible to use the power path of other configurations.The unit is coupled to the weld pad of the device
110.In one embodiment, the weld pad is I/O pads.The I/O receives I/O signals.For example, the I/O signals can for input signal or
Two-way signaling.It is also possible to use other types of weld pad.
In one embodiment, the unit includes phase inverter, and it has first of coupled in series between those power paths
And transistor seconds 130,140.It is also possible to use other types of unit.Those transistors can be metal-oxide semiconductor（metal
oxide semiconductor；MOS）Transistor.In one embodiment, the first transistor is p-type transistor and second crystalline substance
Body pipe is n-type transistor.The first terminal of the first transistor is coupled to the first power path, and the of the first transistor
Two-terminal is coupled to the Second terminal of the transistor seconds.The first terminal of the transistor seconds is coupled to second power rail
Line.The body (body) of the first transistor be coupled to the first power path and the transistor seconds body be coupled to this
Two power paths.
The input 134 of the phase inverter is commonly coupled to the grid of those transistors.The output 136 of the phase inverter is coupled jointly
To the Second terminal of those transistors.In one embodiment, the phase inverter is configured to receiver.For example, the weld pad is coupled to
The input of the phase inverter.The output is coupled to other internal circuits（It is not shown）.The phase inverter can also have other configurations.
Esd event can betide the weld pad.The esd event for example can be ESD or the triggering stimulation for being provided in the weld pad
The result of (trigger stimulus) such as ESD or energy pulse.It is also possible to use the other types of triggering for triggering esd event
Stimulate.The ESD stimulates can be not intended to or unexpectedly be provided in the weld pad.Or, the ESD stimulates and can intentionally be provided in the weld pad, example
Such as in the case where ESD is tested.
The esd event makes the transistor of the unit be in desperate situation.For example, the esd event can damage the risk crystal
The gate dielectric of pipe, so that the unit produces defect.In one embodiment, the esd event makes the second crystalline substance of the phase inverter
Body pipe is in desperate situation.For example, the esd event makes the n-type MOS transistor be in desperate situation.In other cases, should
ESD can make other types of transistor be in desperate situation.
In one embodiment, there is provided gate dielectric protection module 150.The protection module includes being coupled to the guarantor of the unit
Shield output 156.In one embodiment, protection output is coupled to the body of the risk transistor.In the case of phase inverter, should
Protection output is coupled to the body of transistor seconds.For example, protection output is coupled to the body of the n-type transistor.
In one embodiment, the protection module is in normal condition（Without esd event）Under produce invalid guarantor in protection output
Shield signal (inactive protection signal).The invalid protection signal makes the unit can operate at the normal condition
Under.For example, the invalid protection signal does not influence the normal bias voltage of the body for putting on the risk transistor.In an embodiment
In, the invalid protection signal provides normal bias voltage for the body of the risk transistor.In one embodiment, the invalid protection
Signal provides the normal bias of 0V or ground connection.May also provide other normal bias voltages.For example, the normal bias voltage can depend on
In the type of risk transistor.
In the case of an esd event, the protection module produces effective protection signal (active protection
signal).Effective protection signal provides ESD and biases to the body of the risk transistor.ESD biasings reduce the risk crystal
Voltage difference between the grid and substrate of pipe（VDIFF）.For example, ESD biasings reduce the risk transistor grid and body it
Between VDIFF.In one embodiment, ESD biasings are enough to ensure that VDIFFGate dielectric less than the risk transistor punctures
Voltage（VBD）.In one embodiment, VDIFFLess than VBDAt least 5% to 10%.If for example, VBDAbout 3.7V, then VDIFFShould be less than
3.5V。
In one embodiment, ESD biasings increase underlayer voltage（VSUB）Or the body of the transistor.Increase VSUBMake VDIFF
Less than VBD.For example, ESD biasings are about 0.5V to 1V.May also provide other ESD bias voltages biasing VSUB。
As described above, the risk transistor is n-type transistor.In other embodiments, the risk transistor can be brilliant for p-type
Body pipe.For p-type transistor, normal bias are VDD.For example, ESD biasings can be less than VDDAbout 0.5V to 1V.In an embodiment
In, the protection module is used for the drop-down 0.5V to 1V of n trap potentials of p-type transistor.It is also possible to use other types of normal bias
And ESD biasings.
In one embodiment, the protection module includes ESD sensing circuits 170 and biasing circuit 160.The ESD sensing circuits
Including sensing output 176, the biasing input 164 that it is coupled to the biasing circuit.The biasing circuit includes biasing output 166,
In one embodiment, biasing output 166 is exported for the protection.It is also possible to use the biasing output and protection output of other configurations.Should
Protection output provides signal, is used to bias the body of the risk transistor.
The function of the ESD sensing circuits is used to sense the generation of esd event.At nominal conditions（Without esd event）, should
ESD sensing circuits produce invalid esd event signal in sensing output.In one embodiment, the invalid esd event signal is to patrol
Collect 1 signal.On the other hand, when esd event is sensed, the ESD sensing circuits produce effective esd event letter in sensing output
Number.In one embodiment, effective esd event signal is logic zero signal.It is also possible to use other types of effective and invalid ESD
Event signal.
The biasing circuit provides ESD and biases when starting to the substrate, to reduce VDIFF.For example, the biasing of the startup
Circuit provides ESD and biases to the body of the transistor, to reduce VDIFF.The biasing circuit is not influenceing the unit just when disabling
Often work.For example, the biasing circuit of the deactivation provides normal bias to the body of the risk transistor.
In one embodiment, the invalid esd event signal in biasing input makes the biasing circuit invalid.This causes this inclined
Circuits produce inactive bias signal in biasing output.The inactive bias signal is provided in protection output.Implement one
In example, the inactive bias signal does not influence the normal bias voltage of the body for putting on the risk transistor.In one embodiment,
The inactive bias signal is logic zero signal or ground connection.The inactive bias signal provides 0V and biases to the body of the risk transistor.
It is also possible to use other types of inactive bias signal.
Effectively the esd event signal enabling biasing circuit, effective offset signal is produced with biasing output.Implement one
In example, effective offset signal is provided in protection output.In one embodiment, effective offset signal is ESD biasings,
To reduce VDIFF.In one embodiment, ESD biasings are provided in the body of the risk transistor.ESD biasings are enough to ensure that
V during esd eventDIFFLess than VBD.For example, ESD biasings can be approximately equal to VDD.Other ESD bias voltages be may also provide with inclined
Put VSUB。
The part of the device may also include esd protection circuit（It is not shown）.The esd protection circuit is coupled to the weld pad.
Various types of esd protection circuits can be used.In certain embodiments, the esd protection circuit may be coupled to those power paths
（Such as VDDAnd VSS）And weld pad.In other embodiments, the esd protection circuit may be coupled to the second power path（For example
VSS）.When an esd event occurs, the esd protection circuit is provided from the weld pad to the current path being grounded, with the ESD electric currents that dissipate.
As described above, the unit includes a risk transistor.It should be understood, however, that the unit may include more than one wind
Dangerous transistor.Furthermore, it is to be understood that can have other units in this has the device of risk transistor.Risk crystal pipe
There is ESD to bias.In one embodiment, a biasing circuit can be used for each risk transistor.Those biasing circuits can be shared
One common sensing circuit.The ESD biasings of risk transistor can be identical.Can also provide different for different types of transistor
ESD is biased.It is also possible to use the biasing and sensing circuit and ESD biasings of other configurations.
The embodiment of Fig. 2 a display gate dielectrics protection module 150.The protection module includes protection output 156.One
In embodiment, protection output is coupled to the body of risk transistor（It is not shown）.For example, protection output to may be coupled to one anti-
The body of the n-type transistor of phase device, as shown in Figure 1.
In one embodiment, the protection module includes ESD sensing circuits 170 and biasing circuit 160.In an embodiment
In, the ESD sensing circuits and biasing circuit coupled in parallel are between first and second power path 102,104.First power
Path can be VDD（Operating voltage）And the second power path can be VSS（Ground connection）.It is also possible to use the power path of other configurations.
The ESD sensing circuits include sensing output 176, the biasing input 164 that it is coupled to the biasing circuit.The biasing circuit includes inclined
Output 166 is put, in one embodiment, biasing output 166 is exported for the protection.It is also possible to use the biasing output of other configurations and protect
Shield output.Protection output provides signal to bias the body of the risk transistor.
The function of the ESD sensing circuits is used to sense the generation of esd event.In one embodiment, the sensing circuit includes
Resistor assembly of the coupled in series between first and second power path（RS）273 and capacitance component（CS）277.First work(
Rate path is coupled to RSAnd CSIt is coupled to the second power path.In one embodiment, RSThe first terminal be coupled to first work(
Rate path and CSThe first terminal be coupled to the second power path.RSAnd CSSecond terminal be coupled to each other, formed common joint
275 or node N1.Sensing output 176 is coupled to node N1.The RC timeconstantτs of the sensing circuit are selected to sense esd event.
For example, the RC time constants should sense ESD electric currents.In one embodiment, τ is about 1.0-2.0 μ s.τ can also be other
Value.
In one embodiment, the biasing circuit includes the first transistor 220 of the coupled in series between those power paths
And transistor seconds 230.The first transistor is p-type MOS transistor（MPB）And the transistor seconds is n-type MOS transistor
（MNB）.The first terminal of the first transistor is coupled to the first power path, and the Second terminal of the first transistor is coupled
To the Second terminal of the transistor seconds.The first terminal of the transistor seconds is coupled to the second power path.First crystalline substance
The body of body pipe is coupled to the first power path and the body of the transistor seconds is coupled to the second power path.
The grid of those transistors is commonly coupled to biasing input 164.Biasing input is coupled to the sense of the sensing circuit
Survey output.Biasing output 166 is commonly coupled to the Second terminal of first and second transistor.In one embodiment, the biasing
It is output into or is coupled to protection module output.
At nominal conditions（Without esd event）, the sensing circuit is in the sensing output invalid esd event signal of generation.
In one embodiment, CSIt is non-conductive at nominal conditions.This causes node N1In logic 1 or high potential（Such as first power rail
The current potential of line or about VDD）.N1The invalid esd event signal that the signal of logic 1 at place is exported as the sensing.The invalid ESD
Event signal is provided in biasing input.The signal of logic 1 makes MPBClose (switch off), MNBOpen, so that this is inclined
Output is put in logical zero or low potential（Such as current potential or V of the second power pathSS）.The logic zero signal is believed for inactive bias
Number.The logic zero signal is the normal bias of the risk transistor, and its work is not influenceed.
When esd event is sensed, the sensing circuit produces effective esd event signal in sensing output.Implement one
In example, when an esd event occurs, electric current flows through CS.This causes node N1In logical zero or low potential（Such as second power rail
The current potential of line or about VSS）.N1Effective esd event signal that the logic zero signal at place is exported as the sensing.Effective ESD
Event signal is provided in biasing input.The logic zero signal makes MPBUnlatching, MNBClose.With MPBOpen and MNBClose,
Export the biasing and be coupled to the first power path, so as to produce logic 1 or high potential in biasing output（For example this first
The current potential or V of power pathDD）Signal.The signal of logic 1 is effective offset signal, and it is provided to the body of the risk transistor
ESD is biased.
ESD biasings reduce VDIFF.In one embodiment, ESD biasings are by increasing VSUBAnd reduce VDIFF.For example, working as
MPBDuring unlatching, electric current flows into the body of the risk transistor from the first power path.The electric current increases the risk transistor
VSUB.In one embodiment, the current value about 1mA of the body of the risk transistor is flowed into.May also provide other current values.
Another embodiment of Fig. 2 b display gate dielectrics protection module 150.Mould described in the similar Fig. 2 a of the protection module
Block.Therefore, common component may no longer be described or describe in detail.As illustrated, providing resistance in protection output 156
（Rext）240.The resistance can be formed for example by polysilicon.It is also possible to use other types of resistance.In one embodiment, RextCoupling
Between protection output and the second power path.For example, RextIt is coupled to protection output and VSSBetween.In an embodiment
In, protection output is coupled to the body of risk transistor（It is not shown）.For example, protection output may be coupled to the n of phase inverter
The body of transistor npn npn, as shown in Figure 1.
At nominal conditions, MPBClose and MNBOpen, the biasing is output as logical zero.Because the biasing is output as logic
0, therefore no current flows through Rext.Due to RextTwo ends absence of voltage, thus put on the risk transistor body it is normal partially
Put unaffected.On the other hand, when the biasing is output as logic 1, electric current flows through Rext.This is in RextTwo ends produce voltage.Should
RextThe voltage at two ends increases VSUB, so as to reduce VDIFF.The RextThe magnitude of voltage at two ends depends on current value and resistance RextIt is big
It is small.The RextThe voltage at two ends is by VDIFFIt is down to and is sufficiently below VBD.In one embodiment, the RextThe voltage at two ends be about 0.5 to
1V.From MPBThe biasing output electric current be about 1mA.Therefore, RextAbout 10 to 50k Ω.May also provide other electric currents and
Resistance.
The part of the embodiment of Fig. 3 a to Fig. 3 d display devices 300.As illustrated, the part includes internal circuit or unit
120.The unit is coupled between first and second power path 102,104.The first power path can be VDD（Operating voltage）
And the second power path can be VSS（Ground connection）.The unit is coupled to the weld pad 110 of the device.The weld pad can for example be believed for I/O
Number I/O pads.
In one embodiment, the unit includes phase inverter, and it has first of coupled in series between those power paths
And transistor seconds 130,140.It is also possible to use other types of unit.The first transistor is p-type transistor and second crystalline substance
Body pipe is n-type transistor.The first terminal of the first transistor is coupled to the first power path, and the of the first transistor
Two-terminal is coupled to the Second terminal of the transistor seconds.The first terminal of the transistor seconds is coupled to second power rail
Line.The body of the first transistor is coupled to the first power path and the body of the transistor seconds is coupled to second power
Path.The input 134 of the phase inverter is commonly coupled to the grid of those transistors.The output 326 of the phase inverter is commonly coupled to
The Second terminal of those transistors.
As illustrated, the weld pad is coupled to the input of the phase inverter.The output is coupled to the internal circuit of the device（Do not scheme
Show）.In other embodiments, the weld pad is coupled to the output of the phase inverter.The input of the phase inverter is coupled to the interior of the device
Portion's circuit（It is not shown）.
In one embodiment, the body of the transistor seconds is coupled to the output of gate dielectric protection module, such as Fig. 1 and
Described in Fig. 2 a to Fig. 2 b.When esd event is detected, start the protection module and provide ESD with to the body of the transistor seconds
Biasing.This reduces VDIFFTo ensure that it is less than VBD。
In one embodiment, there is provided esd protection circuit 390.The esd protection circuit is coupled to the weld pad.Difference can be used
The esd protection circuit of type.In certain embodiments, the esd protection circuit may be coupled to those power paths（Such as VDDAnd
VSS）And weld pad.In other embodiments, the esd protection circuit may be coupled to the second power path（Such as VSS）.When ESD things
When part occurs, the esd protection circuit is provided from the weld pad to the electric current pad being grounded, with the ESD electric currents that dissipate.
As shown in Figure 3 a, the esd protection circuit includes the n-type MOS transistor MN of grounded-gridP350, its drain terminal DPCoupling
To the weld pad, source SPAnd grid GPIt is commonly coupled to VSS.Transistor MNPParasitic bipolar junction transistor is formed in the substrate
（bipolar junction transistor；BJT）.The BJT is NPN BJT, by DP, substrate（P-well）With SPKnot
(junction) formed.Such as DP- substrate interface forms first p-n junction and S of the NPN BJTP- substrate forms the NPN BJT's
Second p-n junction.
Under normal operating conditions（For example without esd event）, because first and second p-n junction of the BJT is reversed partially
Put, therefore the earth grid ensures MNPClose.The signal of the weld pad does not receive MNPThe influence of closing, so that the unit being capable of work
Make under normal condition.Esd event increases DP（VDP）Voltage, make current flow through, so as to increase substrate electric potential（For example it is parasitic
The base stage or V of BJTB）.Work as VBWhen sufficiently high, parasitic BJT is opened.For example, working as VBMore than trigger voltage VTPWhen, MNPOpen.It draws
Play MNPAvalanche breakdown, so as to be formed from the weld pad to VSSCurrent path 316 with the ESD electric currents that dissipate.
Fig. 3 b show another embodiment of esd protection circuit 390.The similar ESD protections as described in Fig. 3 a of the protection circuit
Circuit.Therefore, similar component may be not described or describe in detail.The esd protection circuit includes coupled in parallel in the weld pad
110 and second power path or ground connection（VSS）Between first grid ground connection n-type MOS transistor（MNP）350 and second grid connect
Ground n-type MOS transistor（MNS）360.
In one embodiment, MNPDrain terminal D including being coupled to the weld padPAnd it is commonly coupled to VSSSource SPAnd grid
GP.Similarly, MNSDrain terminal DPIt is coupled to the weld pad, source SSAnd grid GSIt is commonly coupled to VSS.Resistance Rsec370 are coupled to
MNPAnd MNSDrain terminal between.The resistance can for example be formed by polysilicon.In one embodiment, the resistance is formed by unsilicided silicon.
Under normal operating conditions（For example without esd event）, those earth grids ensure MNPAnd MNSClose.This be because
For first and second p-n junction of BJT is reverse biased.Due to MNPAnd MNSClose, the signal of the weld pad is unaffected, so as to
Enough make the cell operation under normal condition.
In the case where there is esd event, DPVoltage（VDP）And DSVoltage（VDS）Increase, make current flow through, so that
Increase substrate electric potential（The base stage or V of such as parasitism BJTBPAnd VBS）.Work as VBPAnd VBSWhen sufficiently high, parasitism those BJT unlatchings.Example
Such as, V is worked asBPAnd VBSMore than MNPAnd MNSTrigger voltage VTWhen, those transistors are opened.It causes those transistor snowslides to be hit
Wear, formed from the weld pad to VSSFirst and second current path 316 and 318 with the ESD electric currents that dissipate.In second current path
In, flow through RsecElectric current produce voltage drop VRsec.The voltage drop is by the input voltage clamper of the risk transistor in VRsec。
Fig. 3 c are refer to, the alternate embodiment of its display esd protection circuit 390.The esd protection circuit is coupled to weld pad
110 and first and second power path 102,104.The esd protection circuit is included by the first diode（D1）320 and the 2nd 2
Pole pipe（D2）The diode pair 314 of 330 compositions.First diode（D1）320 and second diode（D2）330 coupled in series in
Between those power paths.In one embodiment, D1Negative electrode C1It is coupled to the first power path（VDD）And D2Anode A2Coupling
It is connected to the second power path（VSS）.D1Anode A1And D2Negative electrode C2It is commonly coupled to the weld pad.Esd protection circuit example
Such as it is the esd protection circuit based on path.
In one embodiment, there is provided clamp circuit 375.The clamp circuit be coupled to first and second power path it
Between.The clamp circuit is invalid under normal condition.When being started by esd event, current path is formed between those power paths.
The clamp current can be controlled by ESD triggers circuits.For example, the triggers circuit produces invalid triggering output at nominal conditions, and
Effective trigger output signal is produced when esd event occurs.
In one embodiment, the clamp circuit includes clamp transistor, such as n-type MOS transistor.When esd event occurs
When, started by triggers circuit or opened the clamp transistor.Open the clamp transistor and electricity is formed between those power paths
Flow path.For example, the triggers circuit can be the sensing circuit of the protection module, as described in Fig. 2 a to Fig. 2 b.May also provide other
The triggers circuit of type.
Under normal operating conditions, those diodes are reverse biased.In addition, the clamp circuit is invalid.Due to those
Diode reverse biased, the signal of the weld pad is unaffected, so that the unit can be operated under normal condition.
In one embodiment, esd event makes D1Or D2Forward bias, forms to a wherein power rail of those power paths
The current path of line.For negative pulse esd event, D2Forward bias and D1Reverse bias.It is formed to VSSCurrent path
327, with the ESD electric currents that dissipate.For positive pulse esd event, D2Reverse bias and D1Forward bias.Further, since the esd event phase
Between the clamp circuit be activated, therefore between those power paths formed by the clamp circuit current path.Such shape
Into through VDDTo VSSCurrent path 326, with the ESD electric currents that dissipate.
Fig. 3 d show another embodiment of esd protection circuit 390.The esd protection circuit similar Fig. 3 c based on path
Esd protection circuit.Therefore, common component may be not described or describe in detail.The esd protection circuit be coupled to this first and
Second power path 102,104 and weld pad 110.In one embodiment, the esd protection circuit includes first and second diode
To 314,316.First and second diode pair coupled in parallel is between first and second power path.This first and second
Diode pair is further coupled to the weld pad 110.
In one embodiment, first diode pair has first diode of the coupled in series between those power paths
（D1）320 and second diode（D2）330.D1Negative electrode C1It is coupled to the first power path（VDD）And D2Anode A2It is coupled to
The second power path（VSS）.D1Anode A1And D2Negative electrode C2It is commonly coupled to the weld pad.Similarly, second diode
To the first diode with coupled in series between those power paths（D3）340 and second diode（D4）350.D3The moon
Pole C3It is coupled to the first power path（VDD）And D4Anode A4It is coupled to the second power path（VSS）.D3Anode A3And
D4Negative electrode C4It is commonly coupled to the weld pad.Resistance（Rsec）370 are coupled to D1And D2Common terminal and D3And D4Common terminal
Between.The resistance can for example be formed by polysilicon.In one embodiment, the resistance can be formed by non-silicon SiClx.
In one embodiment, there is provided clamp circuit 375.The clamp circuit be coupled to first and second power path it
Between.The clamp circuit is invalid under normal condition.When the clamper is started by esd event, electricity is formed between those power paths
Flow path.The clamp circuit can be controlled by ESD triggers circuits.For example, the triggers circuit produces invalid triggering at nominal conditions
Output, and effective trigger output signal is produced when an esd event occurs.
Under normal operating conditions, the diode of the esd protection circuit is reverse biased.In addition, the clamp circuit without
Effect.Because those diodes are reverse biased, the signal of the weld pad is unaffected such that it is able to make the cell operation in normal shape
Under condition.
In one embodiment, esd event makes D1And D3Or D2And D4Forward bias, forms to those power paths wherein
The current path of one power path.For negative pulse esd event, D2And D4Forward bias and D1And D3Reverse bias.It is formed extremely
VSSCurrent path 327 and 329 with the ESD electric currents that dissipate.For positive pulse esd event, D2And D4Reverse bias and D1And D3It is positive
Biasing.The clamp circuit is activated during being additionally, since esd event, therefore is formed by the pincers between those power paths
The current path of position circuit.So formed through VDDTo VSSFirst and second current path 326,328, with the ESD electric currents that dissipate.
In second current path, R is flowed throughsecElectric current produce voltage drop VRsec.The voltage drop is electric by the input of the risk transistor
Pressing tongs is located at VRsec。
The present invention can be implemented without departing from spirit or essential attributes of the invention in other specific forms.Therefore, above-mentioned reality
Example only illustrative is applied, is not intended to limit the present invention.The scope of the present invention is represented by appended claims, rather than described above,
Whole changes in the equivalent meaning and scope of claim are intended to be incorporated herein.
Claims (18)
1. a kind of semiconductor device, including：
Transistor, with the grid on substrate, the grid includes the gate electrode above gate dielectric；
Gate dielectric protection module, is coupled to the transistor, wherein, the gate dielectric protection module provides guarantor when starting
Shield biasing, by the voltage difference V between the grid and substrateDIFFIt is brought down below the breakdown voltage V of the gate dielectricBD,
Wherein, the gate dielectric protection module includes：
Sensing circuit, with detection electrostatic electric discharge event；And
Biasing circuit, is coupled to the transistor,
Wherein, when electrostatic discharge event is detected, the sensing circuit starts the biasing circuit, to provide protection biasing, with
And
Wherein：
The transistor is the part of the I/O units for being coupled to I/O pads；
The I/O units include I/O transistors, and the I/O transistor AND gates transistor series connection is coupled between first and second path,
The first terminal of the I/O transistors is coupled to first path and the first terminal of the transistor is coupled to second path；
The input of I/O units couples the I/O pads to the I/O transistors and the grid of the transistor；And
The output of I/O units is coupled to the I/O transistors and the common Second terminal of the transistor.
2. semiconductor device as claimed in claim 1, wherein：
The transistor includes the transistor body in the substrate；And
The gate dielectric protection module is coupled to the transistor body.
3. semiconductor device as claimed in claim 2, wherein, the gate dielectric protection module is provided to the transistor body
The protection is biased, to increase underlayer voltage VSUB, so as to by VDIFFIt is brought down below VBDAt least 5%.
4. semiconductor device as claimed in claim 1, wherein, the gate dielectric protection module provides protection biasing, with
Increase underlayer voltage VSUB, so as to by VDIFFIt is brought down below VBD。
5. semiconductor device as claimed in claim 1, wherein, the gate dielectric protection module provides protection biasing, with
By VDIFFIt is brought down below VBDAt least 5%.
6. semiconductor device as claimed in claim 1, wherein, the sensing circuit includes：
Sensing resistance, with sense capacitance coupled in series between first and second path, wherein, the sensing resistance be coupled to this
The one path and sense capacitance is coupled to second path；And
Sensing circuit is exported, and is coupled to the biasing circuit, sensing circuit output being total to located at the sensing resistance and sense capacitance
With between terminal, wherein, when electrostatic discharge event is not detected, the sensing circuit produces invalid sense in sensing circuit output
Output signal is surveyed, and when electrostatic discharge event is detected, the sensing circuit produces effectively sensing output signal inclined to start this
Circuits.
7. semiconductor device as claimed in claim 6, wherein, the biasing circuit includes：
First and second transistor, coupled in series between first and second path, the first terminal coupling of the first transistor
The first terminal for being connected to first path and the transistor seconds is coupled to second path；
Biasing input, is coupled to the grid of first and second transistor；And
Biasing output, is coupled to the common Second terminal of first and second transistor.
8. semiconductor device as claimed in claim 7, wherein：
First path is high power path；
Second path is ground connection path；
The first transistor is p-type transistor；
The transistor seconds is n-type transistor；And
When the protection circuit is started, open the first transistor and close the transistor seconds, so that electric current is from first rail
Line flows to the biasing and exports through the first transistor.
9. semiconductor device as claimed in claim 8, wherein, the body of the current direction of the biasing output transistor,
To produce the protection to bias, so as to reduce VDIFF。
10. semiconductor device as claimed in claim 8, including：
Biasing output resistance, is coupled to biasing output and second path, wherein, the electric current of biasing output flows through the electricity
Resistance, to produce the protection to bias, so as to reduce VDIFF。
11. semiconductor devices as claimed in claim 1, wherein：
The I/O transistors are p-type transistor；
The transistor is n-type transistor；
First path is high power path；And
Second path is ground connection path.
12. semiconductor devices as claimed in claim 1, including the ESD protection circuit based on path, it is coupled to this
Transistor.
13. semiconductor devices as claimed in claim 1, including the ESD protection circuit based on weld pad, it is coupled to this
Transistor.
A kind of 14. methods for forming semiconductor device, including：
Transistor is formed, it has the grid on substrate, the grid includes the gate electrode above gate dielectric；
And
Formation is coupled to the gate dielectric protection module of the transistor, wherein, the gate dielectric protection module is when starting
Protection biasing is provided, by the voltage difference V between the grid and substrateDIFFIt is brought down below the breakdown voltage of the gate dielectric
VBD；
Wherein, forming the gate dielectric protection module includes：
Sensing circuit is formed, with detection electrostatic electric discharge event；And
Biasing circuit is formed, the transistor is coupled to,
Wherein, when electrostatic discharge event is detected, the sensing circuit starts the biasing circuit, to provide protection biasing, with
And
Wherein：
The transistor is the part of the I/O units for being coupled to I/O pads；
The I/O units include I/O transistors, and the I/O transistor AND gates transistor series connection is coupled between first and second path,
The first terminal of the I/O transistors is coupled to first path and the first terminal of the transistor is coupled to second path；
The input of I/O units couples the I/O pads to the I/O transistors and the grid of the transistor；And
The output of I/O units is coupled to the I/O transistors and the common Second terminal of the transistor.
15. methods as claimed in claim 14, wherein, the transistor includes the transistor body in the substrate；And
Including coupling the gate dielectric protection module to the transistor body.
16. methods as claimed in claim 15, wherein, the gate dielectric protection module provides the guarantor to the transistor body
Shield biasing, to increase underlayer voltage VSUB, so as to by VDIFFIt is brought down below VBDAt least 5%.
17. methods as claimed in claim 14, wherein, the gate dielectric protection module provides protection biasing, to increase
Underlayer voltage VSUB, so as to by VDIFFIt is brought down below VBD。
A kind of 18. methods for protecting gate dielectric, including：
Risk transistor is provided；
Offer is coupled to the protection module of the risk transistor；
Start the protection module to provide protection biasing, so as to by the voltage difference between the grid and substrate of the risk transistor
VDIFFIt is brought down below the breakdown voltage V of the gate dielectric of the risk transistorBD；
Wherein, there is provided the protection module includes：
Sensing circuit is provided, with detection electrostatic electric discharge event；And
Biasing circuit is provided, the risk transistor is coupled to,
Wherein, when electrostatic discharge event is detected, the sensing circuit starts the biasing circuit, to provide protection biasing, with
And
Wherein：
The risk transistor is the part of the I/O units for being coupled to I/O pads；
The I/O units include I/O transistors, and I/O transistor AND gates risk transistor series connection is coupled to first and second path
Between, the first terminal of the I/O transistors be coupled to first path and the risk transistor the first terminal be coupled to this
Two paths；
The input of I/O units couples the I/O pads to the I/O transistors and the grid of the risk transistor；And
The output of I/O units is coupled to the I/O transistors and the common Second terminal of the risk transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310189992.2A CN104183595B (en) | 2013-05-21 | 2013-05-21 | Gate dielectric layer protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310189992.2A CN104183595B (en) | 2013-05-21 | 2013-05-21 | Gate dielectric layer protection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104183595A CN104183595A (en) | 2014-12-03 |
| CN104183595B true CN104183595B (en) | 2017-05-24 |
Family
ID=51964525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310189992.2A Expired - Fee Related CN104183595B (en) | 2013-05-21 | 2013-05-21 | Gate dielectric layer protection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104183595B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297580A (en) * | 1999-01-19 | 2001-05-30 | 精工爱普生株式会社 | Circuit for protection against static electricity, and semiconductor integrated circuit using same |
| US6411480B1 (en) * | 1999-03-01 | 2002-06-25 | International Business Machines Corporation | Substrate pumped ESD network with trench structure |
| US6873017B2 (en) * | 2003-05-14 | 2005-03-29 | Fairchild Semiconductor Corporation | ESD protection for semiconductor products |
| US7579881B2 (en) * | 2007-11-14 | 2009-08-25 | Infineon Technologies Ag | Write driver circuit |
| US7719813B2 (en) * | 2005-10-20 | 2010-05-18 | United Microelectronics Corp. | Gate-coupled substrate-triggered ESD protection circuit and integrated circuit therewith |
-
2013
- 2013-05-21 CN CN201310189992.2A patent/CN104183595B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297580A (en) * | 1999-01-19 | 2001-05-30 | 精工爱普生株式会社 | Circuit for protection against static electricity, and semiconductor integrated circuit using same |
| US6411480B1 (en) * | 1999-03-01 | 2002-06-25 | International Business Machines Corporation | Substrate pumped ESD network with trench structure |
| US6873017B2 (en) * | 2003-05-14 | 2005-03-29 | Fairchild Semiconductor Corporation | ESD protection for semiconductor products |
| US7719813B2 (en) * | 2005-10-20 | 2010-05-18 | United Microelectronics Corp. | Gate-coupled substrate-triggered ESD protection circuit and integrated circuit therewith |
| US7579881B2 (en) * | 2007-11-14 | 2009-08-25 | Infineon Technologies Ag | Write driver circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104183595A (en) | 2014-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103001206B (en) | Electrostatic discharge (ESD) power clamp for clamping high-voltage power supply in mixed-voltage chip by means of low-voltage transistor | |
| CN106505066B (en) | ESD protection circuit | |
| US8611058B2 (en) | Combination ESD protection circuits and methods | |
| US7705404B2 (en) | Electrostatic discharge protection device and layout thereof | |
| US8315024B2 (en) | Electrostatic discharge protection circuit, integrated circuit and method of protecting circuitry from an electrostatic discharge voltage | |
| US8830640B2 (en) | Electrostatic discharge protection circuit | |
| US20150245546A1 (en) | Electrostatic discharge protection circuit | |
| JP2007531284A (en) | Method and apparatus for protecting gate oxide using source / bulk pumping | |
| US20050045952A1 (en) | Pfet-based esd protection strategy for improved external latch-up robustness | |
| CN107230673A (en) | Use the electrostatic discharge (ESD) protection of zone of protection | |
| CN108155636A (en) | There is source interface resistance modulation switch | |
| TWI524495B (en) | Gate dielectric protection | |
| US20120236447A1 (en) | Input-output esd protection | |
| US10879232B2 (en) | Circuit, system and method for electrostatic discharge (ESD) protection | |
| US10181721B2 (en) | Area-efficient active-FET ESD protection circuit | |
| US20150342098A1 (en) | I/o device, method for providing esd protection for an i/o device and esd protection device for an i/o device | |
| CN108695301A (en) | Static discharge(ESD)The method of protective device and operation Esd protection device | |
| CN106653736A (en) | ESD protection circuit and semiconductor device thereof | |
| CN104867922B (en) | Conductor integrated circuit device and the electronic equipment for using the device | |
| TWI431753B (en) | Esd protection circuit with eos immunity | |
| US5910873A (en) | Field oxide transistor based feedback circuit for electrical overstress protection | |
| JP3901549B2 (en) | Semiconductor integrated circuit device | |
| CN104183595B (en) | Gate dielectric layer protection | |
| US20180182749A1 (en) | Dynamically triggered electrostatic discharge cell | |
| CN102543995B (en) | Electrostatic discharge protection circuit of negative power supply integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170524 Termination date: 20200521 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |