CN104183546A - Method for forming seed crystal layers in silicon through hole technology - Google Patents
Method for forming seed crystal layers in silicon through hole technology Download PDFInfo
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- CN104183546A CN104183546A CN201410428614.XA CN201410428614A CN104183546A CN 104183546 A CN104183546 A CN 104183546A CN 201410428614 A CN201410428614 A CN 201410428614A CN 104183546 A CN104183546 A CN 104183546A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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Abstract
The invention provides a method for forming seed crystal layers in a silicon through hole technology. The method comprises the steps that a first-time seed crystal layer deposition process is conducted in a silicon through hole, and first seed crystal layers are formed in the silicon through hole and on the outer surface of the top of the silicon through hole; a backflow process is conducted on the first seed crystal layers, and the first seed crystal layers with the smooth surfaces are formed; a second-time seed crystal layer deposition process is conducted in the silicon through hole, and second seed crystal layers are formed on the surfaces of the first seed crystal layers. Due to the fact that the prepared seed crystal layers are provided with the smooth surfaces, advantageous conditions are provided for the subsequent copper electroplating, the detect that holes are generated inside the padded copper is effectively overcome, the technological quality of copper electroplating is improved, and the reliability of the silicon through hole is ensured.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of inculating crystal layer in silicon via process.
Background technology
In the technological development of very lagre scale integrated circuit (VLSIC), along with further developing of Moore's Law, part technological parameter has approached physics limit, as the barrier layer thickness etc. in the dielectric thickness in the grid technique in resolution, device in photoetching process, interconnection.Silicon via process can reduce the usable floor area of silicon chip, silicon utilance is provided and shortens interconnection length, thereby can further extend and expand Moore's Law, and silicon through hole (Through Silicon Via:TSV) has become the focus of research.Silicon through hole technology has 2.5D, 3D etc., wherein 2.5D is silicon (Si) keyset (interposer), the chip of difference in functionality is integrated on the silicon keyset of silicon through hole as CPU (central processing unit), Memory (memory) etc., now silicon through hole is applied at imageing sensor, MEMS, radio frequency/discrete device, is applied from now on by being applied in the different application such as imageing sensor, logical AND memory integrated and realizing memory by silicon through hole technology at silicon chip aspect the memory capacity increase on longitudinally.
Silicon via process method has: via-first, and through hole is placed in the middle, and through hole is last.Via-first is before device forms, first carry out photoetching, etching, the liner deposit of through hole, then carry out the filling of conductor, this is the metallic pollution in order to prevent subsequent technique, many is to adopt polysilicon to fill, due to metal filled the wanting greatly of resistance ratio that polysilicon is filled, current chip factory adopts in this way and is few.Through hole Shi Qian placed in the middle road device completes and after contact hole completes, carries out silicon via process, the deposit that it comprises etching, dielectric insert material, the techniques such as barrier layer deposition, metal filled and cmp subsequently, after silicon via process, be the technique of interconnecting metal, what industry generally adopted at present is copper wiring technique.The technique that through hole is last, normally completes at encapsulation factory, is after chip completes, and carries out photoetching, the etching of through hole, and this kind of method, need to overcome the etching to different Membranes, requires higher to etching technics.In above-mentioned three kinds of silicon via process, through hole technique placed in the middle becomes the silicon via process of industry main flow.
In through hole silicon via process placed in the middle, copper electroplating technology is one of critical process step, the object of copper electroplating technology is in silicon through hole, to fill copper, before electroplating, copper to carry out inculating crystal layer deposit, the smoothness of the inculating crystal layer of institute's deposit will have influence on the filling effect of copper in silicon through hole, and for example, inculating crystal layer is assembled and formed wedge angle in silicon through hole corner, will reduce the copper electroplating technology window of silicon through hole, cause the copper inside of filling to occur cavity blemish; Seed crystal surface is uneven even not continuous, and will cause copper to fill and there is different fill rates, thus also can be at the inner cavity blemish that produces of the copper of filling, cavity blemish not only can affect silicon through hole resistance, and can badly influence the reliability of silicon through hole.
And, because silicon through hole characteristic size is at 5um-10um, the degree of depth of silicon through hole is in 50-100um left and right, its depth-to-width ratio in about 5-10 even up to 20, therefore, in so high depth-to-width ratio silicon through hole, carry out thin film deposition and usually cause silicon via top corner aggregation to form projection or wedge angle, thereby reduced the process window that subsequent copper is filled, had a strong impact on the filling quality of copper.
In addition; silicon via etch adopts Bosch (Bosch) technique conventionally; comprise: first utilize etching gas to etch silicon through hole, then adopt passivation technology to protect the through-silicon via sidewall of etching; next repeat hocket etching and the passivation technology of silicon through hole, thereby complete the etching of the silicon through hole of high-aspect-ratio.During actual process is produced, due to the restriction of Bosch etching technics itself, often there is the rough phenomenon of through-silicon via sidewall, this will cause follow-up film deposition art to be difficult to form good sidewall coverage, further cause the seed crystal surface of follow-up formation uneven or discontinuous, thereby have a strong impact on the effect that copper is filled, occur cavity blemish in the copper inside of filling.
Summary of the invention
In order to overcome above problem, the present invention is intended to improve existing inculating crystal layer depositing technics, to forming the inculating crystal layer with smooth surface.
In order to achieve the above object, the invention provides the formation method of inculating crystal layer in a kind of silicon via process, employing one has the Semiconductor substrate of silicon through hole, and it comprises:
Step S01: in described silicon through hole, carry out inculating crystal layer deposition process for the first time, in described silicon through hole and outer surface of cupular part form the first inculating crystal layer;
Step S02: described the first inculating crystal layer is carried out to reflux course, form first inculating crystal layer with smooth surface;
Step S03: carry out inculating crystal layer deposition process for the second time in described silicon through hole, form the second inculating crystal layer in described the first seed crystal surface.
Preferably, the deposition process of described inculating crystal layer for the first time carries out in a reaction chamber, and described reflux course adopts the backflow cavity with electrostatic chuck, and described step S02 specifically comprises:
Step L01: under vacuum environment, the Semiconductor substrate that completes described step S01 is transferred on the electrostatic chuck of described backflow cavity from described reaction chamber;
Step L02: pass into reacting gas in described backflow cavity;
Step L03: at a certain temperature, start to carry out described reflux course.
Further, in described reflux course, the gas of employing is H
2, He and NH
3; Further, described He is passed in described backflow cavity from described electrostatic chuck.Further, the flow of described He is 5-10sccm.
Preferably, in described reflux course, the temperature of employing is 200-500 DEG C.
Preferably, in the described deposition process of inculating crystal layer for the first time and the described deposition process of inculating crystal layer for the second time, adopt the physical gas-phase deposition with bias voltage.
Preferably, the deposition time of the described deposition process of inculating crystal layer be for the first time greater than described in the deposition time of inculating crystal layer deposition process for the second time.
Preferably, the parameter of the described deposition process of inculating crystal layer for the first time comprises: direct current power is 40-90KW, substrate bias power 500-2000W, and deposition time is 10-90sec.
Preferably, the parameter of the described deposition process of inculating crystal layer for the second time comprises: direct current power is 40-90KW, substrate bias power 0-500W, and deposition time is 10-30sec.
The formation method of inculating crystal layer in silicon via process of the present invention, by improving existing inculating crystal layer depositing technics, being divided into three processes completes: inculating crystal layer deposition process, reflux course, inculating crystal layer deposition process for the second time for the first time, utilize reflux course that the first inculating crystal layer that inculating crystal layer deposition process forms is for the first time carried out to smooth treatment, turning sphering and the smooth surface of the first inculating crystal layer after smooth treatment, thereby for follow-up copper electroplating technology provides advantage, avoid the inner cavity blemish that produces of copper of filling, improved the reliability of silicon through hole.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the inculating crystal layer formation method of a preferred embodiment of the present invention
Fig. 2-5 are the corresponding structural representation of each preparation process of the inculating crystal layer formation method of a preferred embodiment of the present invention
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
As previously mentioned, in the preparation of silicon through hole, the smoothness of the inculating crystal layer of institute's deposit will badly influence the quality of subsequent copper plating, if the seed crystal surface of institute's deposit is rough or discontinuous or occur around the corner wedge angle, the copper inside that causes filling in silicon through hole is had to cavity, have a strong impact on resistance and the reliability of silicon through hole.Therefore, the present invention overcomes the above-mentioned defect that existing inculating crystal layer deposit occurs, depositing technics to inculating crystal layer improves, being divided into three processes carries out, comprise: the deposition process of inculating crystal layer for the first time, the deposition process of reflux course and for the second time inculating crystal layer, in inculating crystal layer deposition process for the first time, form the first inculating crystal layer, then through reflux course, because making the first seed crystal surface form molten state and produce, reflux course flows, thereby make to be positioned at the part of silicon via top corner, the surface of the first inculating crystal layer of through-silicon via sidewall part and silicon via bottoms part is tending towards smooth, final first inculating crystal layer with smooth surface that forms, finally, then the deposition process that carries out inculating crystal layer is for the second time to repair the first inculating crystal layer problem that thickness reduces after refluxing, and reaches needed thickness to the gross thickness that makes the first inculating crystal layer and the second inculating crystal layer.
Below with reference to accompanying drawing 1-5 and specific embodiment, the formation method of inculating crystal layer in silicon via process of the present invention is further described.Wherein, Fig. 2-5 are the corresponding structural representation of each preparation process of the inculating crystal layer formation method of a preferred embodiment of the present invention.It should be noted that, accompanying drawing all adopts very the form simplified, uses non-ratio accurately, and only in order to object convenient, that clearly reach aid illustration the present embodiment.
Referring to Fig. 1, is the schematic flow sheet of the inculating crystal layer formation method of a preferred embodiment of the present invention, and the inculating crystal layer formation method of the present embodiment can be, but not limited to carry out the deposition process of inculating crystal layer in a reaction chamber, carries out reflux course in backflow cavity; It specifically comprises the following steps:
Step S01: refer to Fig. 3, in silicon through hole 2, carry out inculating crystal layer deposition process for the first time, in silicon through hole 2 and outer surface of cupular part form the first inculating crystal layer 3;
Concrete, before carrying out for the first time inculating crystal layer deposition process, refer to Fig. 2, first, in semi-conductive substrate 1, carry out silicon via etch, film deposition art;
Here,, in the present embodiment, in Semiconductor substrate 1, form silicon through hole 2 and in silicon through hole 2, form the thin layer (not shown) such as laying and barrier layer.Can adopt existing silicon via etch process such as Bosch technique is carried out the etching of silicon through hole 2, film deposition art can be, but not limited to comprise laying deposit, barrier layer deposition etc., laying can adopt the dielectric materials such as silica, silicon nitride, nitrogen-oxygen-silicon, and barrier layer can adopt the materials such as tantalum, tantalum nitride, titanium, titanium nitride; The diameter of silicon through hole 2 can be, but not limited to as 2-10um, and the degree of depth of silicon through hole 2 can be, but not limited to as 10-100um; It should be noted that, that before the deposition process of inculating crystal layer for the first time of the present invention carries out, carries out anyly all can adopt existing method to complete about silicon via etch and film deposition art, and the present invention is not restricted this.
It should be noted that, after silicon via etch, conventionally can cause the out-of-flatness of silicon through hole 2 inwalls, thereby cause subsequent thin film deposition also to occur out-of-flatness problem, in Fig. 2, illustrated the inwall of irregular silicon through hole 2.
Then, refer to Fig. 3, in a reaction chamber, carry out inculating crystal layer deposition process for the first time, above-mentioned Semiconductor substrate 1 is placed in to this reaction chamber, can be, but not limited to adopt physical gas-phase deposition with bias voltage to the deposit of carrying out the first inculating crystal layer 3 in silicon through hole 2, concrete technological parameter can require to set according to actual process, in the present embodiment, the parameter that inculating crystal layer deposition process adopts is for the first time as follows: direct current power is 40-90KW, is preferably 50KW, 70KW or 90KW; Substrate bias power 500-2000W, the time is 10-90sec; Can be, but not limited to adopt argon gas as reacting gas, the gas flow of argon gas can be 1-10sccm, is preferably 3sccm, 5sccm or 7sccm.But this is not limited to scope of the present invention.After having reacted, in silicon through hole 2 and the outer surface of cupular part of silicon through hole 2 be all coated with the first inculating crystal layer 3, as shown in Figure 3.
Step S02: refer to Fig. 4, the first inculating crystal layer 3 is carried out to reflux course, form first inculating crystal layer 3 ' with smooth surface;
Concrete, in the present embodiment, reflux course carries out in backflow cavity, and backflow cavity has electrostatic chuck for adsorbing Semiconductor substrate 1; This step S02 specifically comprises:
Step L01: the Semiconductor substrate of completing steps S01 1 is moved in backflow cavity, and be placed on electrostatic chuck, in this moving process, Semiconductor substrate 1 is all the time under vacuum environment;
Step L02: pass into reacting gas in backflow cavity, wherein partly or entirely reacting gas enters backflow cavity from electrostatic chuck, and preferably, the reacting gas of employing is H
2, He and NH
3, wherein, He is passed in backflow cavity from electrostatic chuck; The flow of helium can be, but not limited to as 5-10sccm, is preferably 7sccm, 8sccm, or 9sccm.
Step L03: carry out at a certain temperature reflux course; The temperature adopting can be, but not limited to as 200-500 DEG C, is preferably 280 DEG C, 300 DEG C, 350 DEG C or 450 DEG C; In this reflux course, by the first inculating crystal layer 3 melt surfaces, utilize the principle of reflux technique, flow in the first inculating crystal layer 3 surfaces of melting, thereby elimination the first inculating crystal layer 3 is positioned at projection or the wedge angle of silicon through hole 2 corners, and the first inculating crystal layer 3 surf zones that make to be positioned at silicon through hole 2 sidewalls and bottom are smooth, thereby form first inculating crystal layer 3 ' with smooth surface.
Step S03: refer to Fig. 5, carry out inculating crystal layer deposition process for the second time in silicon through hole 2, form the second inculating crystal layer 4 on the first inculating crystal layer 3 ' surface.
Concrete, in a reaction chamber, carry out inculating crystal layer deposition process for the second time, the Semiconductor substrate 1 that completes above-mentioned steps S02 is placed in to this reaction chamber under vacuum environment, can be, but not limited to adopt the physical gas-phase deposition with bias voltage to carry out the second inculating crystal layer 4 depositing technics, concrete technological parameter can require to set according to actual process, the parameter adopting in the present embodiment is as follows: direct current power is 40-90KW, is preferably 50KW, 60KW or 70KW; Substrate bias power 0-500W, deposition time is 10-30sec; Can be, but not limited to adopt argon gas as reacting gas, the gas flow of argon gas can be 1-10sccm, is preferably 3sccm, 5sccm or 7sccm.But this is not limited to scope of the present invention.
It should be noted that, after completing reflux course, the first inculating crystal layer 3 ' has had smooth surface, and the good condition that provides is provided for this deposit for follow-up the second inculating crystal layer 4 and copper; The second inculating crystal layer 4 is the problems such as thickness or composition variation that reduce because of backflow in order to repair the first inculating crystal layer 3 ', therefore, the thickness of the second inculating crystal layer 4 does not need very thick, only need be at the continuous cover layer of the upper formation of the first inculating crystal layer 3 ', so in the situation that other inculating crystal layer depositing technics condition is constant, the time of inculating crystal layer deposition process can be greater than the time of inculating crystal layer deposition process for the second time for the first time, or the substrate bias power of inculating crystal layer deposition process can be greater than the substrate bias power of inculating crystal layer deposition process for the second time for the first time; Then in other preferred embodiment of the present invention, inculating crystal layer deposit for the first time and the parameter that inculating crystal layer deposition process adopts for the second time also can be identical, the present invention is not restricted this, under the smooth prerequisite of the second seed crystal surface, make the gross thickness of the first and second inculating crystal layers reach needed thickness as long as ensure.
It should be noted that, after the second inculating crystal layer forms, also can experience copper electroplating technology and fill copper in silicon through hole, the processes such as the top surface of copper are filled in planarization, because the second inculating crystal layer has the surface of nearly smooth, thereby improve the quality of subsequent copper electroplating technology and can reduce the inner cavity blemish producing of copper of filling.
In sum, the formation method of inculating crystal layer in silicon via process of the present invention, has improved existing inculating crystal layer depositing technics, introduces reflux course, utilizes reflux course to make the melt surface of the first inculating crystal layer and produce to flow, thereby is tending towards smooth; Inculating crystal layer deposition process is repaired the first seed crystal surface for the second time, thereby reaches needed thickness and material composition, guarantees the stability of silicon via process; Because prepared inculating crystal layer has smooth surface, thereby electroplate advantage is provided for follow-up copper, effectively avoided the copper inside of filling to produce cavity blemish, improved copper electroplating technology quality, and ensured the reliability of silicon through hole.
Although the present invention discloses as above with preferred embodiment; right described embodiment only gives an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. a formation method for inculating crystal layer in silicon via process, employing one has the Semiconductor substrate of silicon through hole, it is characterized in that, also comprises:
Step S01: in described silicon through hole, carry out inculating crystal layer deposition process for the first time, in described silicon through hole and outer surface of cupular part form the first inculating crystal layer;
Step S02: described the first inculating crystal layer is carried out to reflux course, form first inculating crystal layer with smooth surface;
Step S03: carry out inculating crystal layer deposition process for the second time in described silicon through hole, form the second inculating crystal layer in described the first seed crystal surface.
2. the formation method of inculating crystal layer in silicon via process according to claim 1, it is characterized in that, the deposition process of described inculating crystal layer for the first time carries out in a reaction chamber, and described reflux course adopts the backflow cavity with electrostatic chuck, and described step S02 specifically comprises:
Step L01: under vacuum environment, the described Semiconductor substrate that completes described step S01 is transferred on the electrostatic chuck of described backflow cavity from described reaction chamber;
Step L02: pass into reacting gas in described backflow cavity;
Step L03: at a certain temperature, start to carry out described reflux course.
3. the formation method of inculating crystal layer in silicon via process according to claim 2, is characterized in that, in described reflux course, the gas of employing is H
2, He and NH
3.
4. the formation method of inculating crystal layer in silicon via process according to claim 3, is characterized in that, described He is passed in described backflow cavity from described electrostatic chuck.
5. the formation method of inculating crystal layer in silicon via process according to claim 3, is characterized in that, the flow of described He is 5-10sccm.
6. the formation method of inculating crystal layer in silicon via process according to claim 1, is characterized in that, in described reflux course, the temperature of employing is 200-500 DEG C.
7. the formation method of inculating crystal layer in silicon via process according to claim 1, is characterized in that, in the described deposition process of inculating crystal layer for the first time and the described deposition process of inculating crystal layer for the second time, adopts the physical gas-phase deposition with bias voltage.
8. the formation method of inculating crystal layer in silicon via process according to claim 1, is characterized in that, the deposition time of inculating crystal layer deposition process for the second time described in the deposition time of the described deposition process of inculating crystal layer is for the first time greater than.
9. the formation method of inculating crystal layer in silicon via process according to claim 1, is characterized in that, the parameter of the described deposition process of inculating crystal layer for the first time comprises: direct current power is 40-90KW, substrate bias power 500-2000W, and deposition time is 10-90sec.
10. the formation method of inculating crystal layer in silicon via process according to claim 1, is characterized in that, the parameter of the described deposition process of inculating crystal layer for the second time comprises: direct current power is 40-90KW, substrate bias power 0-500W, and deposition time is 10-30sec.
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