CN104168684A - Integrated circuit capable eliminating current ripple - Google Patents

Abstract

The invention discloses an integrated circuit capable of eliminating a current ripple of a constant-current source load. The integrated circuit comprises a constant-current source load drive unit of the integrated circuit and an illumination lamp containing the drive unit. According to the invention, the integrated circuit is used for eliminating a current ripple according to a single stage active power factor correction (APFC) constant-current LED driving scheme; and a minimalism requirement of minimum discrete components is met. Moreover, with the circuit, the LED ripple current can be reduced to less than 1.5% substantially.

Description

Current ripples is eliminated integrated circuit

Technical field

The present invention relates to current ripples eliminate circuit, in particular to a kind of for eliminating the integrated circuit of current source loads current ripples, the current source loads drive unit that comprises described integrated circuit, and the lighting that comprises described drive unit.

Background technology

As lighting source of new generation, light-emitting diode (LED) is used widely gradually.At present, as the Switching Power Supply of LED main force driving power, two developing stage have been experienced., there is the LBD constant-current switch power source controller of many moneys specialty in the first stage, ripe drive integrated circult has promoted startup and the growth of LED illumination market greatly gradually on market.This one-phase is the primary stage of LBD illumination, and basic side is to low and middle-end illumination market.Along with LBD lighting is toward the infiltration of high-end illumination market, driving power is had higher requirement, such as requiring, power factor (PF) is greater than 0.9, always harmonic wave (THD) is less than 20%, and LED illumination needs more energy-conservation, more green in a word.Subsequently, occur Active Power Factor Correction APFC (Active Power Factor Correction) LED constant-current driven chip on market, one-level circuit is realized PFC and constant current control simultaneously, and from then on LED drives chip to enter second stage.

APFC is the effective ways that suppress LED lighting harmonic current, improve power factor.Fig. 1 shows existing single-stage APFC constant current LED drive circuit.As shown in Figure 1,50/60Hz AC-input voltage, after rectifier bridge 101 full-wave rectifications, becomes the 100/120Hz fluctuating signal of non-filtered, then by single-stage APFC constant current DC/DC circuit 102, realizes High Power Factor value and constant current output.Due to the input current of single-stage APFC constant current DC/DC circuit 102, output current is current waveform in full-wave rectifier with input voltage and phase place is identical, therefore, the capacitance of output filter capacitor 103 needs very large, with the operating current ripple of guaranteeing LED load 105 in +/-60%.Such as, be the application that 500mA and output voltage are 36V for average output current, for the 100/120Hz current ripples that makes LED is less than +/-40%, the capacitance of filter capacitor 103 need to be up to more than 660uF/50V.

The greatest problem of single-stage APFC constant current LED driving power source is, LED 100/120Hz current ripples is too large, conventionally up to +/-more than 40%.And the current ripples of 100/120Hz+/-40% must cause the brightness of light fixture also to have same light ripple.Although we can not perceive the light ripple that 100/120Hz immediately, long-term under such light, people is easy to fatigue, and easily suffers from the ophthalmology diseases such as myopia.Given this, the common recognition of LED gaffer industry is, for people's health, should reduce as far as possible the LED 100/120Hz current ripples of single-stage APFC illuminator, such as being controlled at +/-below 3% at present.

There are two kinds of methods that are easy to expect, can be used to reduce the LED 100/120Hz current ripples in Fig. 1 scheme.

One method is to strengthen the capacitance of filter capacitor 103.Theoretically, the capacitance of filter capacitor 103 is as enough large in obtained, and just LED current ripples can be controlled to the scope of any needs with interior (such as current ripples is less than +/-2%).But, in real work, the capacitance of filter capacitor 103 that had two effects limit.The one, cost, about 2 yuans of the cost of 660uF/50V electric capacity, the cost of 10000uF/50V electric capacity is just up to 20 yuans; The 2nd, spatial volume, large 10 times than 660uF/50V electric capacity of the volumes that 10000uF/50V electric capacity accounts for, general light fixture can not provide so large space.As can be seen here, strengthen merely the capacitance of filter capacitor 103 often unworkable.

Another kind method is to adopt two-step scheme, as shown in Figure 2.Prime APFC DC/DC circuit 201 is realized PFC function, and rear class PWM constant current DC/DC circuit 202 is realized low ripple constant current output.This is the way of current industrial quarters comparative maturity.Its advantage is can be suitable for various power application, good stability.Shortcoming is, many level switching circuits, and circuit is more complicated, not only needs larger power supply space, and causes cost to increase by 10 yuan to 30 yuans.So high cost increases, and is doomed this method to be only suitable for super high power (such as being greater than 100 watts) and cost not have to the applied environment of sensitivity so.For common commercial and domestic lighting, two-step scheme is difficult to promote.

At present, start to occur a kind of scheme of low cost elimination LED current ripples on market, the cost increasing is less than 5 yuans.This scheme, on the basis of Fig. 1, has increased the 100/120Hz current ripples of connecting with LED load 105 and has eliminated circuit, as shown in Figure 3.Wherein, the core parts of 100/120Hz current ripples elimination circuit 310 are to be managed the Darlington NPN multiple tube forming by two NPN.The operation principle of this ripple elimination circuit has been utilized the saturation curve of NPN pipe, as shown in Figure 4.The saturation curve of this saturation curve and NMOS pipe is about the same.In Fig. 4, X-axis represents the collector emitter voltage VCE (or drain source voltage VDS of NMOS pipe) of NPN pipe, and Y-axis represents the collector current IC (or drain current ID of NMOS pipe) of NPN pipe.Can find out, the IC (or ID) in dotted line left side is substantially linear with VCE (or VDS), therefore cries linear zone.But on dotted line right side, along with VCB (or VDS) continues to increase, IC (or ID) remains unchanged substantially, and this region is saturation region.And two solid line correspondences different NPN pipe base current (or NMOS tube grid voltage).Visible, in saturation region, as long as ensure that the base current (or grid voltage of NMOS pipe) of NPN pipe is stable, the impact that output current IC (or ID) is not just changed by VCB (or VDS) substantially.

In Fig. 3, because current ripples elimination circuit 310 is cascaded with LED load 105, so the voltage that ripple elimination circuit is born is larger, loss will be larger, and efficiency will be lower.Therefore, it is low that the work pressure drop that requires current ripples to eliminate circuit 310 is tried one's best, and is namely operated in as far as possible the critical point of saturation region and linear zone.If design is appropriate, efficiency only can decline 3 to 5 percentage points, substantially suitable with the efficiency of traditional two-step scheme in Fig. 2, even slightly high.But the shortcoming of Fig. 3 scheme also clearly.The first, Fig. 3 scheme is made up of discrete component, and this figure is schematic diagram, and the quantity of actual components reaches more than 10, causes manufacturing and designing, applies and safeguard all cumbersome.The second, owing to being that discrete component forms, Fig. 3 scheme just can not have perfect safeguard measure, such as, do not possess overheat protector, short-circuit protection, the open-circuit-protection of power component.Like this, once certain link is made mistakes, just probably cause system to be burnt, this can cause very large puzzlement in large-scale production and installation process.The 3rd, the cost of Fig. 3 scheme or higher.The 4th, Fig. 3 scheme is open cycle system, very high to application environmental requirement, unfavorable to business promotion.

Summary of the invention

The above-mentioned defect of eliminating circuit for ripple in existing single-stage APFC constant-current LED drive scheme, the object of the invention is to, and a kind of low cost closed-loop system being realized by minimum discrete component is provided, and effectively eliminates the current ripples of LBD load.

Basic thought of the present invention is, based on the above-mentioned analysis to Fig. 3 scheme, overcome above shortcoming, just requires the present invention to meet the following conditions, the one, possess the least possible discrete component; The 2nd, be easy to realize possible safeguard measure; The 3rd, low cost; The 4th, closed-loop system.Correspondingly, solution may be only to adopt integrated circuit to realize.

According to a first aspect of the invention, provide a kind of integrated circuit of eliminating current source loads current ripples, described current source loads, by single-stage APFC constant current DC/DC drives, carries out power factor correction and constant current control; Described integrated circuit is connected with described current source loads, and its inside is provided with voltage compression shaping circuit, error amplifying circuit, low gain inverting amplifier and NMOS pipe; Described integrated circuit has: the first pin being connected with the drain electrode of described NMOS pipe, and this pin is used for connecting described current source loads; The second pin being connected with the source electrode of described NMOS pipe, this pin is for ground connection; And as the three-prong of ic power end, this pin is for connecting the output of described single-stage APFC constant current DC/DC circuit, and wherein, voltage compression shaping circuit, input connects the drain electrode of described NMOS pipe, in order to its drain voltage is carried out to compression shaping, output connects described error amplifying circuit; Error amplifying circuit, receives the NMOS pipe drain voltage of compressed shaping, and the error between itself and a reference voltage is amplified; Low gain inverting amplifier, the error signal through amplifying that described error amplifying circuit is exported is carried out anti-phase, and its output connects the grid of described NMOS pipe.

In first aspect, preferably, described error amplifying circuit comprises error amplifier, integrating resistor and integrating capacitor, wherein, error amplifier, its first input end receives the NMOS pipe drain voltage of compressed shaping through integrating resistor, the second input receives described reference voltage, and its output produces the error signal through amplifying; Integrating capacitor, its one end connects the node between error amplifier first input end and integrating resistor, and the other end connects the output of error amplifier.

Preferably, the frequency of described current ripples is 100 hertz or 120 hertz, and the product of the resistance of described integrating resistor and integrating capacitor capacitance is greater than 0.2.

Preferably, the signal of the NMOS pipe drain voltage of described compressed shaping is, 100 hertz or 120 hertz of voltage signals fluctuating using described reference voltage as mean value.

Preferably, described voltage compression shaping circuit comprises comparator, adder and subtracter, and wherein, comparator, for the size of more described NMOS pipe drain voltage and described reference voltage; Adder, in the situation that described NMOS pipe drain voltage is more than or equal to described reference voltage, is added described reference voltage and NMOS pipe drain voltage divided by the total of constant K 1, generate the NMOS pipe drain voltage of described compressed shaping; Subtracter, in the situation that described NMOS pipe drain voltage is less than described reference voltage, subtracts each other described reference voltage and NMOS pipe drain voltage divided by the total of constant k2, generate the NMOS pipe drain voltage of described compressed shaping; Wherein, K1 is value between 30 to 200, and K2 is value between 1 to 10, and K1 is at the more than 10 times of K2.

Preferably; described integrated circuit also comprises thermal-shutdown circuit; described thermal-shutdown circuit comprises temperature sensor and treatment circuit and a resistance; described temperature sensor and treatment circuit are connected to the node between described resistance one end and voltage compression shaping circuit input end, and the other end of described resistance connects the drain electrode of described NMOS pipe.

Preferably, described three-prong connects the output of described single-stage APFC constant current DC/DC circuit by a current-limiting resistance.

According to second aspect, a kind of integrated circuit of eliminating current source loads current ripples is provided, described current source loads, by single-stage APFC constant current DC/DC drives, carries out power factor correction and constant current control; Described integrated circuit is connected with described current source loads, and its inside is provided with voltage compression shaping circuit, error amplifying circuit, low gain inverting amplifier and NPN pipe; Described integrated circuit has: the first pin being connected with the collector electrode of described NPN pipe, and this pin is used for connecting described current source loads; The second pin being connected with the emitter of described NPN pipe, this pin is for ground connection; And as the three-prong of ic power end, this pin is for connecting the output of described single-stage APFC constant current DC/DC circuit, and wherein, voltage compression shaping circuit, input connects the collector electrode of described NPN pipe, in order to its collector voltage is carried out to compression shaping, output connects described error amplifying circuit; Error amplifying circuit, receives the NPN pipe collector voltage of compressed shaping, and the error between itself and a reference voltage is amplified; Low gain inverting amplifier, the error signal through amplifying that described error amplifying circuit is exported is carried out anti-phase, and its output connects the base stage of described NPN pipe.

According to the third aspect, a kind of device that drives current source loads is provided, comprising: single-stage APFC constant current DC/DC circuit, for driving described current source loads, carries out power factor correction and constant current control; Filter capacitor, is connected in parallel between the output and ground of described single-stage APFC constant current DC/DC circuit; And current ripples elimination integrated circuit, to connect with described current source loads, its inside is provided with voltage compression shaping circuit, error amplifying circuit, low gain inverting amplifier and NMOS pipe; Described integrated circuit has: the first pin being connected with the drain electrode of described NMOS pipe, and this pin is used for connecting described current source loads; The second pin being connected with the source electrode of described NMOS pipe, this pin is for ground connection; And as the three-prong of ic power end, this pin is for connecting the output of described single-stage APFC constant current DC/DC circuit, and wherein, voltage compression shaping circuit, input connects the drain electrode of described NMOS pipe, in order to its drain voltage is carried out to compression shaping, output connects described error amplifying circuit; Error amplifying circuit, receives the NMOS pipe drain voltage of compressed shaping, and the error between itself and a reference voltage is amplified; Low gain inverting amplifier, the error signal through amplifying that described error amplifying circuit is exported is carried out anti-phase, and its output connects the grid of described NMOS pipe.

According to fourth aspect, a kind of lighting is provided, it is characterized in that, comprise the device described in the above-mentioned third aspect and LED load.

According to the present invention, eliminate the current ripples in single-stage APFC constant-current LED drive scheme by an integrated circuit, realize extremely briefly asking of minimum discrete component.And the cost of this integrated circuit can be controlled at below 2 yuans completely.In some low power applications, cost even can be controlled in below 0.5 yuan.Meanwhile, apply current ripples of the present invention and eliminate circuit, can make LED ripple current decline to a great extent to less than 1.5%.

Brief description of the drawings

For understanding better the present invention, below with embodiment, the invention will be further described by reference to the accompanying drawings.In accompanying drawing:

Fig. 1 shows existing single-stage APFC constant current LED drive circuit;

Fig. 2 shows existing for reducing the two-step scheme of Fig. 1 LED current ripples;

Fig. 3 shows the existing single-stage APFC constant current LED drive circuit with current ripples elimination circuit;

Fig. 4 shows the saturation curve of NPN pipe (NMOS pipe);

Fig. 5 shows the LED drive unit of one embodiment of the invention;

Fig. 6 shows LED electric current and the OUT voltage waveform before ripple;

Fig. 7 shows the waveform that removes LED electric current, OUT voltage and LEDN voltage after ripple through integrated circuit 510;

Fig. 8 is a kind of exemplary circuit structure of voltage compression shaping circuit 516;

The complete procedure that Fig. 9 shows integrated circuit 510 and enters steady-working state from starting shooting to;

Figure 10 shows the current ripples that comprises thermal-shutdown circuit and eliminates integrated circuit 550;

Figure 11 shows the operation principle of thermal-shutdown circuit;

Figure 12 shows the LED drive unit of another embodiment of the present invention.

Embodiment

With reference to Fig. 5, Fig. 5 shows the LED drive unit of one embodiment of the invention.In this device, LED load 105 is driven by single-stage APFC constant current DC/DC circuit 102, independent power factor correction (PFC) and the constant current control of implementing whole device of single-stage APFC constant current DC/DC circuit 102.Current ripples is eliminated integrated circuit 510 and is connected with LED load 105, then receives together the two ends of filter capacitor 103.The effect of integrated circuit 510 is, eliminates the 100/120Hz current ripples that prime single-stage APFC constant current DC/DC circuit 102 produces.

In the inside of integrated circuit 510, be provided with voltage compression shaping circuit 516, error amplifying circuit 530, low gain inverting amplifier 517 and NMOS pipe 518.Integrated circuit 510 has three pins, and wherein, the first pin LBDN is connected with the drain electrode of inner NMOS pipe 518, and this pin is used for connecting LED load 105; The second pin is connected with the source electrode of NMOS pipe 518, and this pin is for ground connection GND; Three-prong is as the power end VCC of integrated circuit 510, and this pin is for connecting the output OUT of single-stage APFC constant current DC/DC circuit 102.

Three foot rest structures by all means of this innovation, in the art, are the technical minimum pins that can accomplish at present, and it is extremely brief to realize application.Meanwhile, the technique of integrated circuit packaging of three pins is also quite ripe, has very large packaging cost advantage.The integrated antenna package of three pins, from low power SOT89-3L, to TO252-3L and the TO251-3L of middle power, and powerful TO220-3L and TO263-3L, is all that industrial quarters is common, with low cost and in the encapsulation of large-scale application.

With reference to Fig. 6, Fig. 6 shows LED electric current and the OUT voltage waveform before ripple.Can find out, although the voltage ripple of the output OUT of single-stage APFC constant current DC/DC circuit 102 only has 5%,, go LED current ripples before ripple up to 48%, this is the cause more much smaller than D.C. resistance due to LED AC resistance.Fig. 7 shows the waveform that removes LED electric current, OUT voltage and LEDN voltage after ripple through integrated circuit 510.Here the namely drain voltage of NMOS pipe 518 of LEDN voltage.As shown in Figure 7, go after ripple through integrated circuit 510, LED current ripples only has about 2%, OUT voltage ripple or 5% left and right, the 1.5V left and right but OUT mean value has risen, LBDN voltage is also operated in 1V between 2.5V, and this can cause system effectiveness about 4% left and right that declines, and additional loss is all born by integrated circuit 510.Generally speaking, depending on varying in size of LED operating current, the power consumption that integrated circuit 510 need to be born is at 0.2W between 2W, and this has just proposed higher heat radiation requirement to the encapsulation of integrated circuit 510.As mentioned before, the power-type encapsulation technology of three pins is very ripe, with low cost and stable, and this is also the considerable advantage that integrated circuit 510 adopts three-prong framework.

Below, labor current ripples is eliminated the operation principle of integrated circuit 510.

Referring again to Fig. 5, while normally work, the voltage on filter capacitor 103 may be higher, and preferably, the VCC pin of integrated circuit 510 is received OUT node by a current-limiting resistance 511.VCC clamp circuit 512 cooperatings of current-limiting resistance 511 and integrated circuit 510 inside, for integrated circuit 510 provides the electric current and voltage of safety and stability.The function class of VCC clamp circuit 512 is similar to voltage-stabiliser tube.And under the situation lower than the maximum withstand voltage of VCC pin, just do not need current-limiting resistance 511 at OUT node maximum voltage, VCC pin can be directly connected to OUT node.

Because NMOS pipe 518 is series relationship with LED load 105, by managing to reduce the current ripples of NMOS pipe 518, also just equal to reduce the current ripples of LED load 105.As can be seen from Figure 4, meet following two conditions, just can making to flow through NMOS, to manage 518 drain current substantially constant simultaneously, and the one, keep its gate-source voltage VGS to stablize constant; The 2nd, guarantee that NMOS pipe 518 is operated in saturation region.NMOS pipe 518 is driven by voltage, and its gate source voltage VGS has directly determined the size of NMOS pipe 518 drain currents in saturation region.Therefore, need to first ensure that NMOS pipe gate source voltage VGS stablizes constant.Except ensureing that drain current is substantially constant, also need to take into account system effectiveness.To take into account current ripples and efficiency simultaneously, just need to make NMOS pipe 518 be operated in as far as possible the left side of saturation region, that is to say, make the drain voltage VDS of NMOS pipe 518 as far as possible near the dotted line in Fig. 4.As shown in Figure 7, LEDN voltage fluctuates between peak value 2.5V at valley 1V, and this fluctuation range must, in NMOS manages 518 saturation region, be considered efficiency in addition, and the valley of LEDN voltage just can not be too high.Therefore, require minimum LEDN voltage (be called for short valley point voltage, lower with) to be operated in the minimum Near The Critical Point of saturation region, that is, and near the dotted line right side in Fig. 4.

Based on above analysis, the present invention adopts a closed loop negative feedback system to realize integrated circuit 510.As shown in Figure 5, this closed loop negative feedback system comprises voltage compression shaping circuit 516, error amplifying circuit 530, low gain inverting amplifier 517 and NMOS pipe 518.Wherein, the input of voltage compression shaping circuit 516 connects the drain electrode of NMOS pipe 518, and for drain voltage (, LEDN pin voltage) is carried out to compression shaping, its output connects error amplifying circuit 530; Error amplifying circuit 530 receives the NMOS pipe drain voltage of compressed shaping, and the error between itself and a fixed reference potential REF is amplified; The signal that low gain inverting amplifier 517 is exported error amplifying circuit 530 carries out anti-phase, and its output connects the grid of NMOS pipe 518.

The gain k value of low gain inverting amplifier 517 is in 1 left and right; Negative sign '-' represents anti-phase, guarantees that whole loop forms degeneration factor.The gain amplifier of loop is mainly from the error amplifier 513 in error amplifying circuit 530, and enough large closed loop gain is the guarantee that system realizes enough high control precisions.In error amplifying circuit 530, integrating resistor 515, integrating capacitor 514 form loop frequency compensation network together with error amplifier 513.In this network, the negative input end of error amplifier 513 receives DCMP voltage (, the NMOS pipe drain voltage of compressed shaping) through integrating resistor 515, and positive input terminal receives reference voltage RBF, and output produces the error signal through amplifying; One end of integrating capacitor 514, connects the node between error amplifier 513 negative input ends and integrating resistor 515, and the other end connects the output of error amplifier 513.

Because the frequency of current ripples only has 100/120Hz, so preferably, require the bandwidth of loop below 1/20th of 100/120Hz, below 5Hz.Bandwidth is lower, and loop offers NMOS, and to manage the voltage fluctuation of 518 grids just less, and 100/120Hz current ripples is also just less.Bandwidth below 5Hz means, integrating resistor 515 is greater than 0.2 second with the integration time constant that integrating capacitor 514 forms, as formula 1, if C ₅₁₄value 1nF, R ₅₁₅minimum resistance be 200 megohms.

τ＝R ₅₁₅C ₅₁₄＞0.2 (1)

With modern semiconductor microelectronics technique, the resistance of manufacturing 200 megohms is no problem, and area is also not too large; The needed silicon area of 1nF electric capacity can not be greater than 0.5mm yet ², therefore feasible.So the common way of low frequency band (5Hz) is that frequency compensation element is placed in to integrated circuit outside.According to the present invention, in order to realize ic pin minimum number and to control packaging cost, innovation ground is placed in said frequencies compensating element, the inside of integrated circuit, is also practicable.

The output signal DCMP of voltage compression shaping circuit 516, for example, the 100/120Hz voltage signal fluctuating up and down as mean value using described reference voltage RBF.Preferably, voltage compression shaping circuit 516 can adopt algorithm as shown in Equation 2.

$V\left(\mathrm{DCMP}\right)=\left\{\begin{array}{ccc}V\left(\mathrm{REF}\right)+V\left(\mathrm{LEDN}\right)/K1,& \mathrm{if}& V\left(\mathrm{LEDN}\right)\&GreaterEqual;V\left(\mathrm{REF}\right)\\ V\left(\mathrm{REF}\right)-V\left(\mathrm{LEDN}\right)/K2,& \mathrm{if}& V\left(\mathrm{LEDN}\right)<V\left(\mathrm{REF}\right)\end{array}\right.---\left(2\right)$

Fig. 8 is a kind of exemplary circuit structure of voltage compression shaping circuit 516, for realizing above-mentioned algorithm.In Fig. 8, NMOS pipe 804,806 is equivalent to common little current switch, and the 805th, General Logic inverter, reference voltage RBF is identical with reference voltage RBF in Fig. 5.Voltage compression shaping circuit 516 comprises comparator 803, adder 802 and subtracter 801.Shaping circuit 516 carries out segment processing to LBDN voltage (being NMOS pipe drain voltage).Wherein, comparator 803 is for comparing the size of LBDN voltage and reference voltage RBF.In the time that LBDN voltage is more than or equal to reference voltage REF, adder 802 is for being added LBDN voltage divided by total and the reference voltage REF of constant K 1; In the time that LBDN voltage is less than reference voltage RBF, subtracter 801 is for subtracting each other divided by the total of constant k2 with reference to voltage RBF and LEDN voltage.

The final purpose of above-mentioned algorithm is, the valley point voltage of LBDN is stabilized in to suitable value, both ensured enough low LED ripple, can take into account again system effectiveness.The size of shaping circuit 516 specific algorithms and reference voltage RBF determines that NMOS pipe 518 is operated in the degree of depth of saturation region.Reference voltage RBF value is larger, and overall LBDN valley point voltage is higher, and saturation depth is also just larger; Otherwise LBDN valley point voltage is lower, saturation depth is less.In order to take into account current ripples size and system effectiveness, need the saturation depth of NMOS pipe 518 to be done lower as far as possible.General reference voltage RBF is taken at 1.2V left and right, therefore, and the saturation depth when constant K 1 in formula 2, K2 have just determined 518 work of NMOS pipe.Wherein, K1 determines the compression degree at the above part LEDN voltage of reference voltage RBF, and K1 is larger, and compression is more severe; K2 determines the compression degree of part LBDN voltage below reference voltage RBF.Preferably, K1 value is between 30 to 200, and K2 value is between 1 to 10, and K1 is at the more than 10 times of K2.This explanation, the Partial shrinkage that LBDN voltage is greater than reference voltage RBF obtains terribly, and it is many to compress slightly lower than the part LEDN voltage of reference voltage REF.

After processing through compression algorithm, obviously become large near the part LEDN voltage weight of voltage valley.Fixing K1 is constant, and K2 value is larger, and LEDN valley point voltage weight is less, can make the valley point voltage of LBDN lower, and efficiency is higher, but 100/120Hz current ripples has larger trend.Fixing K2 is constant, K1 value is larger, and LBDN valley point voltage weight is larger, also will make the valley point voltage (being the minimum drain voltage of NMOS pipe 518) of LBDN more approach reference voltage RBF, efficiency is lower simultaneously, but 100/120Hz current ripples can be less.In general, after steady operation, the valley point voltage of LEDN is than the lower slightly 0.1V of reference voltage to 0.7V left and right, and as can be seen from Figure 7, LEDN valley point voltage is 0.9V, than the low 0.3V of 1.2V reference voltage RBF.As can be seen here, efficiency and 100/120Hz current ripples size are contradiction, so the value of reference voltage RBF and constant K 1, K2 needs Comprehensive to consider.The average current that no matter flows through LBD is much, and the closed loop negative feedback system of integrated circuit 510 all can be by LBDN valley point voltage automatic stabilisation at suitable height.In other words, this closed loop negative feedback system can be from the average output current of motion tracking prime APFC constant current DC/DC circuit 102.

The complete procedure that Fig. 9 shows integrated circuit 510 and enters steady-working state from starting shooting to.Can find out, the moment count from start, integrated circuit 510 use nearly just LBD current ripples is lowered for 1 second, this is because the low-down reason of feedback loop bandwidth of integrated circuit 510 causes.LBDN voltage is almost nil at the beginning, LBD ripple current maximum at this time, and after 1 second, along with LEDN voltage rises to normal value, LBD ripple current declines to a great extent to less than 1.5%.

Further, Figure 10 shows the current ripples that comprises thermal-shutdown circuit and eliminates integrated circuit 550.Thermal-shutdown circuit is made up of temperature sensor and treatment circuit 519 and resistance 520; temperature sensor and treatment circuit 519 are connected to the node between resistance 520 one end and voltage compression shaping circuit 516 inputs, and the other end of resistance 520 connects the drain electrode of NMOS pipe 518.

Figure 11 shows the operation principle of thermal-shutdown circuit.Before the t1 moment, the working temperature of integrated circuit 550 is below 130 degrees Celsius, and the output current of temperature sensor and treatment circuit 519 is zero, and the voltage drop of resistance 520 is just also zero, and thermal-shutdown circuit cuts little ice.From the t1 moment; integrated circuit 550 reaches 130 degrees Celsius of critical points of overheat protector; the output current of temperature sensor and treatment circuit 519 starts to increase from zero working temperature along with integrated circuit 550 is linear; the voltage drop of resistance 520 also increases along with linearity, and this can cause the valley point voltage of LBDN to decline thereupon.Under LBDN valley point voltage, general who has surrendered brings two results, and the one, system effectiveness raises, and integrated circuit 550 power consumptions decline, and namely caloric value declines; It is large that the 2nd, LED current ripples becomes, but LED average current can not change.By the time after the t2 moment, the temperature rise to 150 degree Celsius of integrated circuit 550, now system reaches equalized temperature, and temperature no longer rises, and the valley point voltage of LBDN no longer declines, and LED current ripples rate is stabilized in 18% and no longer increases.Numeral in Figure 11 is example.

Other protective circuits such as load open circuit protection, load short circuits protection, on basis of the present invention, can realize in the usual way.

Figure 12 shows the LED drive unit of another embodiment of the present invention.Consider that NPN pipe is extremely similar with the principle of NMOS pipe elimination current ripples, in this embodiment, substituted the NMOS pipe 518 in Fig. 5 with NPN pipe 521, other are constant.In some application scenario, NPN pipe has cost advantage.

In description above, although the present invention is taking driving LED load as example,, those skilled in the art are understandable, and the present invention can be used for driving any current source loads.

Obviously, the present invention described here can have many variations, and this variation can not be thought and departs from the spirit and scope of the present invention.Therefore, all changes that it will be apparent to those skilled in the art, within being all included in the covering scope of appended claims.

Claims (10)

1. eliminate an integrated circuit for current source loads current ripples, described current source loads, by single-stage APFC constant current DC/DC drives, carries out power factor correction and constant current control; Described integrated circuit is connected with described current source loads, and its inside is provided with voltage compression shaping circuit, error amplifying circuit, low gain inverting amplifier and NMOS pipe; Described integrated circuit has:

The first pin being connected with the drain electrode of described NMOS pipe, this pin is used for connecting described current source loads;

The second pin being connected with the source electrode of described NMOS pipe, this pin is for ground connection; And

As the three-prong of ic power end, this pin is used for connecting the output of described single-stage APFC constant current DC/DC circuit, and wherein,

Voltage compression shaping circuit, input connects the drain electrode of described NMOS pipe, and in order to its drain voltage is carried out to compression shaping, output connects described error amplifying circuit;

Error amplifying circuit, receives the NMOS pipe drain voltage of compressed shaping, and the error between itself and a reference voltage is amplified;

Low gain inverting amplifier, the error signal through amplifying that described error amplifying circuit is exported is carried out anti-phase, and its output connects the grid of described NMOS pipe.

2. integrated circuit as claimed in claim 1, is characterized in that, described error amplifying circuit comprises error amplifier, integrating resistor and integrating capacitor, wherein,

Error amplifier, its first input end receives the NMOS pipe drain voltage of compressed shaping through integrating resistor, and the second input receives described reference voltage, and its output produces the error signal through amplifying,

Integrating capacitor, its one end connects the node between error amplifier first input end and integrating resistor, and the other end connects the output of error amplifier.

3. integrated circuit as claimed in claim 2, is characterized in that, the frequency of described current ripples is 100 hertz or 120 hertz, and the product of the resistance of described integrating resistor and integrating capacitor capacitance is greater than 0.2.

4. integrated circuit as claimed in claim 1, is characterized in that, the signal of the NMOS pipe drain voltage of described compressed shaping is, 100 hertz or 120 hertz of voltage signals fluctuating using described reference voltage as mean value.

5. integrated circuit as claimed in claim 4, is characterized in that, described voltage compression shaping circuit comprises comparator, adder and subtracter, wherein,

Comparator, for the size of more described NMOS pipe drain voltage and described reference voltage;

Adder, in the situation that described NMOS pipe drain voltage is more than or equal to described reference voltage, is added described reference voltage and NMOS pipe drain voltage divided by the total of constant K 1, generate the NMOS pipe drain voltage of described compressed shaping;

Subtracter, in the situation that described NMOS pipe drain voltage is less than described reference voltage, subtracts each other described reference voltage and NMOS pipe drain voltage divided by the total of constant k2, generate the NMOS pipe drain voltage of described compressed shaping;

Wherein, K1 is value between 30 to 200, and K2 is value between 1 to 10, and K1 is at the more than 10 times of K2.

6. the integrated circuit as described in any one in claim 1 to 5; it is characterized in that; described integrated circuit also comprises thermal-shutdown circuit; described thermal-shutdown circuit comprises temperature sensor and treatment circuit and a resistance; described temperature sensor and treatment circuit are connected to the node between described resistance one end and voltage compression shaping circuit input end, and the other end of described resistance connects the drain electrode of described NMOS pipe.

7. the integrated circuit as described in any one in claim 1 to 5, is characterized in that, described three-prong connects the output of described single-stage APFC constant current DC/DC circuit by a current-limiting resistance.

8. eliminate an integrated circuit for current source loads current ripples, described current source loads, by single-stage APFC constant current DC/DC drives, carries out power factor correction and constant current control; Described integrated circuit is connected with described current source loads, and its inside is provided with voltage compression shaping circuit, error amplifying circuit, low gain inverting amplifier and NPN pipe; Described integrated circuit has:

The first pin being connected with the collector electrode of described NPN pipe, this pin is used for connecting described current source loads;

The second pin being connected with the emitter of described NPN pipe, this pin is for ground connection; And

As the three-prong of ic power end, this pin is used for connecting the output of described single-stage APFC constant current DC/DC circuit, and wherein,

Voltage compression shaping circuit, input connects the collector electrode of described NPN pipe, and in order to its collector voltage is carried out to compression shaping, output connects described error amplifying circuit;

Error amplifying circuit, receives the NPN pipe collector voltage of compressed shaping, and the error between itself and a reference voltage is amplified;

Low gain inverting amplifier, the error signal through amplifying that described error amplifying circuit is exported is carried out anti-phase, and its output connects the base stage of described NPN pipe.

9. a device that drives current source loads, comprising:

Single-stage APFC constant current DC/DC circuit, for driving described current source loads, carries out power factor correction and constant current control;

Filter capacitor, is connected in parallel between the output and ground of described single-stage APFC constant current DC/DC circuit; And

Current ripples is eliminated integrated circuit, connects with described current source loads, and its inside is provided with voltage compression shaping circuit, error amplifying circuit, low gain inverting amplifier and NMOS pipe; Described integrated circuit has:

The first pin being connected with the drain electrode of described NMOS pipe, this pin is used for connecting described current source loads;

The second pin being connected with the source electrode of described NMOS pipe, this pin is for ground connection; And

As the three-prong of ic power end, this pin is used for connecting the output of described single-stage APFC constant current DC/DC circuit, and wherein,

Voltage compression shaping circuit, input connects the drain electrode of described NMOS pipe, and in order to its drain voltage is carried out to compression shaping, output connects described error amplifying circuit;

Error amplifying circuit, receives the NMOS pipe drain voltage of compressed shaping, and the error between itself and a reference voltage is amplified;

Low gain inverting amplifier, the error signal through amplifying that described error amplifying circuit is exported is carried out anti-phase, and its output connects the grid of described NMOS pipe.

10. a lighting, is characterized in that, comprises device claimed in claim 9 and LED load.