CN104168013A - Automatic identification system based on serial port electrical level - Google Patents
Automatic identification system based on serial port electrical level Download PDFInfo
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- CN104168013A CN104168013A CN201410313797.0A CN201410313797A CN104168013A CN 104168013 A CN104168013 A CN 104168013A CN 201410313797 A CN201410313797 A CN 201410313797A CN 104168013 A CN104168013 A CN 104168013A
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Abstract
The invention discloses an automatic identification system based on a serial port electrical level, consisting of a control chip AX, an exclusive-OR gate integrated chip U1 which is connected to the control chip AX, and an electric level sampling protection circuit which is connected to the exclusive-OR gate integrated chip U1. The automatic identification system based on serial port electrical level is characterized in that a control switch alarm circuit which is connected to the exclusive-OR gate integrated chip U1, the electric sampling protection circuit and the control chip AX is positioned, and that the control switch alarm circuit is connected to the input terminal of the exclusive-OR gate through a base electrode. The invention can automatically sample and identify the electric level of the terminal device of the supporting device and can automatically connect to the communication between the safety payment device and the supporting terminal device, so that the defect caused by the mismatching of the safety payment device and the supporting terminal device can be effectively avoided.
Description
Technical field
The present invention relates to serial communication and control field, specifically refer to a kind of automatic recognition system based on serial ports level.
Background technology
At present; the payment equipment of using due to people need to be used in conjunction with supporting terminal equipment; and that the level of supporting terminal equipment is each is skimble-scamble; therefore in the serial communication process of payment equipment and supporting terminal equipment, often can run into the unmatched situation of level, thereby can cause the situation of a lot of Communications failures.For this reason, people conventionally adopt and add the method for toggle switch to process, but before carrying out dial-up, what the level state that but must know supporting terminal equipment is, bring great inconvenience so just to the use of supporting terminal, equally also caused a lot of concurrent problems.Meanwhile, whether traditional payment equipment is no matter successful with supporting terminal equipment communication, all can not well provide relevant warning, therefore virtually also can increase the difficulty of judgement.
Summary of the invention
When the object of the invention is to overcome current people and using payment equipment and supporting terminal equipment to carry out communication, the defect that must first obtain the level state of supporting terminal equipment and cannot warn whether successful connection, provide a kind of not only simple in structure, and can also omit this level state completely and obtain state, and a kind of automatic recognition system based on serial ports level that can warn communication success or not.
The present invention is achieved through the following technical solutions: a kind of automatic recognition system based on serial ports level, mainly by control chip AX, the XOR gate integrated chip U1 being connected with this control chip AX, and the level sampling protective circuit being connected with this XOR gate integrated chip U1 forms, meanwhile, be also provided with the control switch warning circuit being connected with XOR gate integrated chip U1, level sampling protective circuit and control chip AX respectively, described control switch warning circuit is connected with an input of XOR gate integrated chip U1 by base stage, collector electrode is connected with the FB pin of control chip AX after resistance R 4, the triode Q1 that emitter is connected with the output of XOR gate integrated chip U1 after resistance R 5, base stage is connected with the collector electrode of triode Q1, its collector electrode is directly connected with the FB pin of control chip AX, the triode Q2 that its emitter is connected with the positive pole of alarm HA after resistance R 6, and base stage is connected with level sampling protective circuit after resistance R 8, its collector electrode is connected with the positive pole of alarm HA after diode D1, the triode Q3 that its emitter is connected with the SW pin of control chip AX after resistance R 7 forms, the output of described XOR gate integrated chip U1 is also connected with the negative pole of alarm HA and the EN pin of control chip AX respectively.
Further, described level sampling protective circuit is by the resistance R 2 of mutually connecting and resistance R 1, the diode D1 and the diode D2 that are mutually connected in series, and the resistance R 3 that one end is connected with another input of XOR gate integrated chip U1, the other end is connected with the P utmost point of diode D2 forms; The tie point of described diode D2 and diode D1, and resistance R 2 is also all connected with the base stage of triode Q1 with the tie point of resistance R 1, and the P utmost point of diode D2 is also connected with the other end of resistance R 2.
In order to ensure result of use, the model of this control chip preferentially adopts AX2003 type, and the model of XOR gate integrated chip U1 preferentially adopts 74HC86 type.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) not only overall structure is very simple in the present invention, and its cost of manufacture and maintenance cost are very cheap, and the present invention can also thoroughly solve the defect that traditional level configuration ubiquity need to preset level value.
(2) the present invention can gather and identify the level state of supporting terminal equipment automatically, the communication of be certainly dynamically connected payment equipment and supporting terminal equipment, thus effectively avoid not mating with supporting terminal equipment level the defect of bringing because of payment equipment.
(3) the present invention can adopt intelligent processing method by the varying level mode of supporting terminal equipment, thereby does not need artificial treatment and parameters completely, realizes automation and controls, and can not only improve identification and operational efficiency, and operation is also very convenient.
(4) the present invention is provided with special alarm, when payment equipment and supporting terminal equipment communication just can give the alarm when unsuccessful.
Accompanying drawing explanation
Fig. 1 is electrical block diagram of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment
As shown in Figure 1; the present invention mainly includes control chip AX; the XOR gate integrated chip U1 being connected with this control chip AX; the level sampling protective circuit being connected with this XOR gate integrated chip U1, and the control switch warning circuit being connected with XOR gate integrated chip U1, level sampling protective circuit and control chip AX respectively forms.Wherein, this control chip AX adopts the AX2003 type of high-performance low-power-consumption to realize.
Described control chip AX, for controlling and process the signal after level sampling protective circuit and XOR gate integrated chip U1 process, can accurately receive with the level that scans supporting terminal equipment and change, and the Communication Control of maintenance and supporting terminal equipment.Level sampling protective circuit, for taking accurately the level of supporting terminal equipment, is carried out data processing for XOR gate integrated chip U1 and control chip.
Control switch warning circuit is for carrying out disconnection and the warning with control chip AX according to the Output rusults of control level sampling protective circuit and XOR gate integrated chip U1.As shown in the figure; this XOR gate integrated chip U1 includes two inputs (i.e. No. 12 ends and No. 13 ends) and an output (i.e. No. 11 ends); level sampling protective circuit is by the resistance R 2 of mutually connecting and resistance R 1; the diode D1 and the diode D2 that are mutually connected in series, and one end forms with the resistance R 3 that an input (No. 13 ends) is connected, the other end is connected with the P utmost point of diode D2 of XOR gate integrated chip U1.In order to ensure result of use, the preferential value of the resistance of this resistance R 1 is 8K Ω, and the preferential value of resistance of resistance R 2 is 4.7 K Ω, and the value of resistance R 3 is 4.7 K Ω.
During connection, the tie point of diode D2 and diode D1, and resistance R 2 is also all connected with the base stage of triode Q1 with the tie point of resistance R 1.Meanwhile, the P utmost point of diode D2 is also connected with the other end of resistance R 2, and the P utmost point of diode D2,, one end of one end of resistance R 2 and resistance R 3 links together jointly, forms an equipotentiality point.
Described control switch warning circuit includes transistor Q1, transistor Q2, transistor Q3, resistance R 4, resistance R 5, resistance R 6, resistance R 7, resistance R 8, diode D1 and alarm HA.Wherein, the base stage of described triode Q1 is connected with an input (No. 12 ends) of XOR gate integrated chip U1, its collector electrode is connected with the FB pin of control chip AX after resistance R 4, and its emitter is connected with the output (No. 11 ends) of XOR gate integrated chip U1 after resistance R 5.The base stage of triode Q2 is connected with the collector electrode of triode Q1, and its collector electrode is directly connected with the FB pin of control chip AX, and its emitter is connected with the positive pole of alarm HA after resistance R 6.The base stage of triode Q3 is connected with resistance R 1 in level sampling protective circuit after resistance R 8, and its collector electrode is connected with the positive pole of alarm HA after diode D1, and its emitter is connected with the SW pin of control chip AX after resistance R 7.
Meanwhile, the output of described XOR gate integrated chip U1 is also connected with the negative pole of alarm HA and the EN pin of control chip AX respectively.
During operation, the present invention is by the clamped excessive components and parts that damage of incoming level signal that prevent input of amplitude limit of diode D1 and diode D2, and the level state of supporting terminal equipment is input to 12 pin of XOR gate integrated chip U1 by sampling resistor R1.Simultaneously, the level state of this supporting terminal equipment also triggers transistor Q1 and transistor Q2 conducting, and then by associated level status signal after the processing of XOR gate integrated chip U1 output signal to the reception pin of control chip AX, by receiving the level of pin, change to judge and belong to which kind of level again, finally, after obtaining level state, through the comparative level of control chip, complete the automatic configuration of level.
In order to ensure result of use, this XOR gate integrated chip U1 and XOR gate integrated chip U2 all preferentially adopt 74HC86 type to realize.
As mentioned above, just can realize preferably the present invention.
Claims (4)
1. the automatic recognition system based on serial ports level, mainly by control chip AX, the XOR gate integrated chip U1 being connected with this control chip AX, and the level sampling protective circuit being connected with this XOR gate integrated chip U1 composition, it is characterized in that: be also provided with the control switch warning circuit being connected with XOR gate integrated chip U1, level sampling protective circuit and control chip AX respectively, described control switch warning circuit is connected with an input of XOR gate integrated chip U1 by base stage, collector electrode is connected with the FB pin of control chip AX after resistance R 4, the triode Q1 that emitter is connected with the output of XOR gate integrated chip U1 after resistance R 5, base stage is connected with the collector electrode of triode Q1, its collector electrode is directly connected with the FB pin of control chip AX, the triode Q2 that its emitter is connected with the positive pole of alarm HA after resistance R 6, and base stage is connected with level sampling protective circuit after resistance R 8, its collector electrode is connected with the positive pole of alarm HA after diode D1, the triode Q3 that its emitter is connected with the SW pin of control chip AX after resistance R 7 forms, the output of described XOR gate integrated chip U1 is also connected with the negative pole of alarm HA and the EN pin of control chip AX respectively.
2. a kind of automatic recognition system based on serial ports level according to claim 1, it is characterized in that: described level sampling protective circuit is by the resistance R 2 of mutually connecting and resistance R 1, the diode D1 and the diode D2 that are mutually connected in series, and the resistance R 3 that one end is connected with another input of XOR gate integrated chip U1, the other end is connected with the P utmost point of diode D2 forms; The tie point of described diode D2 and diode D1, and resistance R 2 is also all connected with the base stage of triode Q1 with the tie point of resistance R 1, and the P utmost point of diode D2 is also connected with the other end of resistance R 2.
3. a kind of automatic recognition system based on serial ports level according to claim 1 and 2, is characterized in that: the model of described control chip is AX2003 type.
4. a kind of automatic recognition system based on serial ports level according to claim 3, is characterized in that: the model of described XOR gate integrated chip U1 is 74HC86 type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410313797.0A CN104168013A (en) | 2014-07-03 | 2014-07-03 | Automatic identification system based on serial port electrical level |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410313797.0A CN104168013A (en) | 2014-07-03 | 2014-07-03 | Automatic identification system based on serial port electrical level |
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| CN104168013A true CN104168013A (en) | 2014-11-26 |
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| CN201410313797.0A Pending CN104168013A (en) | 2014-07-03 | 2014-07-03 | Automatic identification system based on serial port electrical level |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2252601Y (en) * | 1996-08-28 | 1997-04-23 | 郑明德 | Digital display diagnosis and treatment instrument |
| US20080211537A1 (en) * | 2007-03-02 | 2008-09-04 | Nec Electronics Corporation | Open drain output circuit |
| CN202586926U (en) * | 2012-05-16 | 2012-12-05 | 深圳市凯明杨科技有限公司 | Automatic identification and communication system based on serial port electrical level |
-
2014
- 2014-07-03 CN CN201410313797.0A patent/CN104168013A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2252601Y (en) * | 1996-08-28 | 1997-04-23 | 郑明德 | Digital display diagnosis and treatment instrument |
| US20080211537A1 (en) * | 2007-03-02 | 2008-09-04 | Nec Electronics Corporation | Open drain output circuit |
| CN202586926U (en) * | 2012-05-16 | 2012-12-05 | 深圳市凯明杨科技有限公司 | Automatic identification and communication system based on serial port electrical level |
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Application publication date: 20141126 |
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| RJ01 | Rejection of invention patent application after publication |