CN104167388B - A kind of forming method of subsequent interconnection technique hollow air-gap - Google Patents
A kind of forming method of subsequent interconnection technique hollow air-gap Download PDFInfo
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- CN104167388B CN104167388B CN201410428612.0A CN201410428612A CN104167388B CN 104167388 B CN104167388 B CN 104167388B CN 201410428612 A CN201410428612 A CN 201410428612A CN 104167388 B CN104167388 B CN 104167388B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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Abstract
The present invention provides a kind of forming methods of subsequent interconnection technique hollow air-gap comprising：One semiconductor substrate with post-channel interconnection film layer structure is provided；Post-channel interconnection film layer structure is followed successively by low K dielectric layer and hard mask layer from bottom to top；Through lithography and etching technique, through-hole structure is etched in low K dielectric layer and hard mask layer；It is etched, the side wall of the through-hole structure in low K dielectric layer is modified, class oxidation membrane material is formed it into；Seed layer is deposited in through-hole structure, and fills metallic copper；Planarization process is filled at the top of metallic copper；Thinned hard mask layer downwards；Removal is located at the hard mask layer at the top of class oxidation membrane material, exposes the top of class oxidation membrane material；It removes class and aoxidizes membrane material；Hard mask layer after removal is thinned.To which during removing class oxidation film, low K dielectric layer will not be damaged, and avoid the damage to through-hole structure, and further reduced the K values of the device subsequently prepared.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of forming method of subsequent interconnection technique hollow air-gap.
Background technology
With the continuous development and progress of integrated circuit technology, the critical size of manufacture of semiconductor constantly reduces, on chip
The sectional area and wire spacing of interconnection line continue to decline, this causes interconnection resistance R and parasitic capacitance C to increase, increased interconnection
Line resistance R and parasitic capacitance C makes the time constant RC of interconnection line increase substantially.Then the time constant RC of interconnection line is to integrated
The influence of circuit delay is increasing, becomes the main reason for limiting interconnection speed.More than 0.13um processing procedures, semiconductor is logical
Metal material frequently with aluminium as rear road line.And when entering 90nm and its following processing procedure, with the interconnection line number of plies and length
Degree increase sharply and the reduction of interconnection width, the resistance of Al lines increase, lead to interconnection time delay, signal decaying and string
Increase, while electromigration and stress effect aggravation are disturbed, the reliability of circuit has been seriously affected.And metallic copper has smaller resistance
Rate and electromobility, therefore, copper become the preferred metal material of the rear road metal of deep sub-micron era.In addition, selection K values are relatively low
Dielectric material can also effectively reduce RC, the parameters such as response speed to improve device.
In general, oxidation film prepared by CVD is commonly used, K values are about 3.9~4.2, can meet 0.13um and its above skill
Art is for technological requirement.It is often used low k dielectric fluorine doped silica glass (FSG) when 90nm technique post-channel interconnections, k values are about 3.5~
3.8.65nm and its it is following when common low k dielectric materials be black brill (BD) and black brill II (BDII), k values are 2.5~
3.3, wherein BDII are the optimization versions of BD, have lower k values.With the continuous development of semiconductor technology, BDII cannot expire
Foot such as 32nm, the technological requirement in the technologies generation such as 28nm.Therefore, the concept of air-gap is come into being.Since the k values of air are 1, energy
RC is reduced well, but its mechanical strength can not support total.Then, by low k dielectric materials partial air gap, from
And whole k values is made to reduce.
Currently, there are no the methods of ripe formation air-gap, during many methods are further studied and verified.
In general, the method for forming air-gap, please refers to Fig.1 the flow that -7, Fig. 1 is the existing method for forming air-gap and shows
It is intended to, Fig. 2-7 is the corresponding schematic diagram of each preparation process of the existing method for forming air-gap；It includes the following steps：
Step L01：Referring to Fig. 2, providing a semiconductor substrate with the mutual film layer structure in rear road；Post-channel interconnection film layer
Structure is followed successively by low K dielectric layer 01 and hard mask layer from bottom to top；Hard mask layer includes silicon oxynitride layer 02 and titanium nitride layer 03.
Step L02：Referring to Fig. 3, through lithography and etching technique, etched in low K dielectric layer 01 and hard mask layer logical
Pore structure；
Step L03：Referring to Fig. 4, it is etched, the side wall of the through-hole structure in low K dielectric layer 01 is modified, it is made
It forms class and aoxidizes membrane material 04；
Step L04：Referring to Fig. 5, seed layer and filling metallic copper 05 are deposited in through-hole structure, and planarization process is filled out
Fill 05 top of metallic copper；
Step L05：Referring to Fig. 6, removing hard mask layer and being partially filled with metallic copper 05；
Step L06：Referring to Fig. 7, removal class aoxidizes membrane material 04.
Here, during removing class oxidation membrane material, the diluted HF of generally use (DHF) carries out wet etching, so
And actual tests confirm, DHF is more than the etch rate of low-K dielectric material BDII the etch rate of class oxidation film, in shape
Cause the low-K dielectric material BDII of other parts that can also be etched away during at the air-gap, or even whole BDII is carved
Eating away, as shown in figure 8, the top of low K dielectric layer, the part adjacent with the side wall of through-hole structure are corroded, it is badly damaged
Through-hole structure.
Invention content
In order to overcome problem above, the present invention is intended to provide a kind of forming method of subsequent interconnection technique hollow air-gap, with
The adjacent region of side wall of the phase in low K dielectric layer and with through-hole structure forms air-gap, it is ensured that low K dielectric layer is not by serious rotten
Eating away.
It is to achieve the goals above, of the invention to provide a kind of forming method of subsequent interconnection technique hollow air-gap,
Including：
Step 01：One semiconductor substrate with post-channel interconnection film layer structure is provided；The post-channel interconnection film layer structure
It is followed successively by low K dielectric layer and hard mask layer from bottom to top；
Step 02：Through lithography and etching technique, through-hole knot is etched in the low K dielectric layer and the hard mask layer
Structure；
Step 03：It is etched, the side wall of the through-hole structure in the low K dielectric layer is modified, is formed it into
Class aoxidizes membrane material；
Step 04：Seed layer is deposited in the through-hole structure, and fills metallic copper；
Step 05：It is filled at the top of metallic copper described in planarization process；
Step 06：The hard mask layer is thinned downwards；
Step 07：Removal is located at the hard mask layer at the top of class oxidation membrane material, exposes the class oxidation film
The top of material；
Step 08：Remove the class oxidation membrane material；
Step 09：The hard mask layer after removal is thinned.
Preferably, the hard mask layer is multilayered structure, and the step 06 includes：The multilayered structure is thinned downwards and protects
Stay the bottom of the multilayered structure.
Preferably, the material of the hard mask layer includes metallic compound or dielectric material.
Preferably, it in the step 05, is filled at the top of metallic copper described in planarization process, makes the top of the filling metallic copper
Portion is higher than the bottom of the multilayered structure, less than the top of the bottom of the multilayered structure.
Preferably, in the step 06, the thining method used is dry etch process.
Preferably, in the step 06, the thickness of the hard mask layer after being thinned is
Preferably, in the step 07, the minimizing technology used is wet-chemical chamber method.
Preferably, the liquid that the wet-chemical chamber method uses for phosphoric acid, the temperature used for 150-170 DEG C, use
Etching speed isThe etch period used is 2-5min.
Preferably, in the step 08, the class is removed using hydrofluoric acid solution and aoxidizes membrane material.
Preferably, in the step 08, in the hydrofluoric acid solution, the concentration ratio of water and hydrofluoric acid is 50:1~200:1,
The time of removal is 2-10min.
A kind of forming method of subsequent interconnection technique hollow air-gap of the present invention, by the way that hard mask layer is thinned, and
The hard mask layer at the top of class oxidation membrane material is etched away, to which class oxidation membrane material to be exposed, falls class to remove
Oxidation film；Due to there is the protection of hard mask layer, during removing class oxidation film, the top of low K dielectric layer and through-hole structure
The adjacent part of side wall will not be removed, so as to avoid the damage to through-hole structure, and further reduced follow-up system
The K values of standby device.
Description of the drawings
Fig. 1 is the flow diagram of the existing method for forming air-gap
Fig. 2-7 is the corresponding schematic diagram of each preparation process of the existing method for forming air-gap
Fig. 8 is the flow diagram of the method for the formation air-gap of the preferred embodiment of the present invention
Fig. 9-18 is corresponding to each preparation process of the method for the formation air-gap of the above-mentioned preferred embodiment of the present invention
Schematic diagram
Specific implementation mode
To keep present disclosure more clear and easy to understand, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
As previously mentioned, when usually preparing air-gap in low K dielectric layer, it can be rotten by the other parts of low K dielectric layer
Eating away, badly damaged through-hole structure；For this purpose, the present invention provides a kind of forming method of air-gap, it is applied to post-channel interconnection
In technique, by the way that hard mask layer is thinned, and the hard mask layer at the top of class oxidation membrane material is etched away, thus by class
Oxidation membrane material is exposed, and falls class oxidation film to remove；Due to there is the protection of hard mask layer, in the mistake of removal class oxidation film
Cheng Zhong, the top of low K dielectric layer, the part adjacent with the side wall of through-hole structure will not be removed.
Below with reference to attached drawing 8-18 and specific embodiment to the formation side of the subsequent interconnection technique hollow air-gap of the present invention
Method is described in further detail.Wherein, Fig. 8 is that the flow of the method for the formation air-gap of the preferred embodiment of the present invention is shown
It is intended to；Fig. 9-18 is showing corresponding to each preparation process of the method for the formation air-gap of the above-mentioned preferred embodiment of the present invention
It is intended to.It should be noted that attached drawing is all made of very simplified form, using non-accurate ratio, and only to conveniently, clearly
Achieve the purpose that aid in illustrating the present embodiment.
Referring to Fig. 8, the method for the formation air-gap of the present embodiment, includes the following steps：
Step 01：Referring to Fig. 9, providing a semiconductor substrate with post-channel interconnection film layer structure；Post-channel interconnection film
Layer structure is followed successively by low K dielectric layer and hard mask layer from bottom to top；
Specifically, the material of low K dielectric layer 1 can be, but not limited to as BDII；Semiconductor substrate can be with before any
The semiconductor substrate of road technique, for example, with source-drain electrode, grid, fleet plough groove isolation structure etc., the invention is not limited in this regard.
Post-channel interconnection film layer is located at the surface of semiconductor substrate.Hard mask layer can be multilayered structure, the material of hard mask layer can with but
It is not limited to include metallic compound or dielectric material, multilayered structure can be, but not limited to successively from the bottom up as silicon oxynitride layer
2 and titanium nitride layer 3.Titanium nitride layer 2 can be, but not limited to be formed for physical vaporous deposition, thickness can be, but not limited to forSilicon oxynitride layer 3 can be, but not limited to be formed for chemical vapour deposition technique, thickness can be, but not limited to for
Step 02：Through lithography and etching technique, through-hole structure is etched in low K dielectric layer and hard mask layer；
Specifically, may include two processes：
First, referring to Fig. 10, coating a layer photoresist on hard mask layer, through lithography and etching technique, patterning is hard
Mask layer；
Secondly, 1 is please referred to Fig.1, using patterned hard mask layer as mask, continues etching low K dielectric layer 1 downwards, to
Through-hole structure is etched in low K dielectric layer 1 and hard mask layer；
Finally, it can be, but not limited to remove photoresist using wet clean process.
Step 03：Please refer to Fig.1 2, it is etched, the side wall of the through-hole structure in low K dielectric layer 1 is modified, it is made
It forms class and aoxidizes membrane material 4；
Specifically, modified method may be used but be not limited to dry etching method, specific technical process is ability
Field technique personnel know, repeat no more herein.Be formed by class oxidation membrane material 4 thickness be
Step 04：3 are please referred to Fig.1, seed layer is deposited in through-hole structure, and fills metallic copper 5；
Specifically, the depositing technics of seed layer can be, but not limited to as gas-phase deposition, the filling of metallic copper 5 can with but
It is not limited to copper electroplating technology.Since those skilled in the art could be aware that the concrete technology of seed layer deposit and copper electroplating technology
Process, the present invention repeat no more this.
Step 05：4 are please referred to Fig.1, planarization process fills 5 top of metallic copper；
Specifically, chemical mechanical polishing method may be used to grind 5 top of filling metallic copper；Here, due to hard mask layer
For multilayered structure, planarization process fills 5 top of metallic copper, and the top of filling metallic copper 5 is made to be higher than the bottom of multilayered structure, low
In the top of the bottom of multilayered structure；It that is to say：So that the top of filling metallic copper 5 is higher than the bottom of silicon oxynitride layer 2, is less than nitrogen
The top of silicon oxide layer 2；In this way, when removal is located at the hard mask layer at 4 top of class oxidation membrane material in subsequent step 07,
The hard mask layer of side wall close to through-hole structure can be made to be more prone to be removed, for example, using chemical corrosion method, due to
Side-walls close to through-hole structure are unobstructed, and the hard mask layer after being thinned is easy to be corroded here.
Step 06：5 are please referred to Fig.1, hard mask layer is thinned downwards；
Specifically, the thinned method used can be, but not limited to as dry etch process；Here, since hard mask layer is
The multilayered structure that silicon oxynitride layer 2 and titanium nitride layer 3 form, then the step be specially：Downward thinned layer structure simultaneously retains more
The bottom of layer structure, that is to say and get rid of titanium nitride layer 3, and retain silicon oxynitride layer 2.Certainly, in other implementations of the present invention
In example, titanium nitride layer 3 and certain thickness silicon nitride layer 2 can also be got rid of, and remains with a thin layer of silicon oxynitride layer 2.
Thinned purpose：First, in order to which the removal process of subsequent step 07 is easy to carry out；Second is that retaining one layer of silicon oxynitride layer 2 can make
For the protective layer for removing when class aoxidizes membrane material 4 in subsequent step 08.As a result, hard mask layer be thinned after thickness be contemplated that
Aoxidize the influence of membrane material 4 to follow-up removal class, in the present embodiment, the thickness of the hard mask layer after being thinned can be
Step 07：6 are please referred to Fig.1, removal is located at the hard mask layer at the top of 4 material of class oxidation film, exposes class oxidation film
The top of material 4；
Specifically, the hard mask layer at 4 top of wet-chemical chamber method removal class oxidation membrane material may be used；Since chemistry is carved
Erosion is isotropic, and hard mask layer is thinned, and is exposed positioned at the part of through-hole structure side wall, therefore, hard mask
Layer can be easy to be corroded positioned at the part of through-hole structure side wall, form an opening herein, thus by class below
The top of oxidation membrane material 4 is exposed；Used liquid can be phosphoric acid, and the temperature used can be 150-170 DEG C, adopt
Etching speed can beThe etch period used can be 2-5min.During this, can only
Corroded at the top of liquid alignment class oxidation membrane material, or the edge of the hard mask layer close to through-hole structure is corroded；It is all
It is that can class be aoxidized the method that the hard mask layer at the top of membrane material etches away to can be applied to the present invention.
Step 08：7 are please referred to Fig.1, removal class aoxidizes membrane material 4；
Specifically, since the part that hard mask layer is located at through-hole structure side wall forms an opening class is aoxidized membrane material
4 tops are exposed, so class oxidation membrane material 4 can be removed by the opening；Hydrofluoric acid solution removal class oxygen may be used
Change membrane material 4；In hydrofluoric acid solution, the concentration ratio of water and hydrofluoric acid can be H2O:HF=50:1~200:1, the time of removal
Can be 2-10min.
Step 09：8 are please referred to Fig.1, the hard mask layer after removal is thinned.
Specifically, the minimizing technology of hard mask layer can be, but not limited to for using dry etching remove, the present invention to this not
It is restricted.
In conclusion the present invention a kind of subsequent interconnection technique hollow air-gap forming method, by hard mask layer into
Row is thinned, and etches away the hard mask layer at the top of class oxidation membrane material, to which class oxidation membrane material is exposed, so as to
Get rid of class oxidation film；Due to there is the protection of hard mask layer, during removing class oxidation film, the top of low K dielectric layer, with
The part that the side wall of through-hole structure is adjacent will not be removed, and so as to avoid the damage to through-hole structure, and be further decreased
The K values of the device of follow-up preparation.
Although the present invention disclosed with preferred embodiment it is as above, the right embodiment illustrate only for the purposes of explanation and
, it is not limited to the present invention, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry changes and retouches, and the protection domain that the present invention is advocated should be subject to described in claims.
Claims (10)
1. a kind of forming method of subsequent interconnection technique hollow air-gap, which is characterized in that including：
Step 01：One semiconductor substrate with post-channel interconnection film layer structure is provided；The post-channel interconnection film layer structure is under
It is followed successively by low K dielectric layer and hard mask layer upwards；Hard mask layer is multilayered structure and includes metal compound layer；
Step 02：Through lithography and etching technique, through-hole structure is etched in the low K dielectric layer and the hard mask layer；
Step 03：It is etched, the side wall of the through-hole structure in the low K dielectric layer is modified, class oxygen is formed it into
Change membrane material, the hard mask layer is not modified；
Step 04：Seed layer is deposited in the through-hole structure, and fills metallic copper；
Step 05：It is filled at the top of metallic copper described in planarization process；
Step 06：The hard mask layer is thinned downwards, removes metal compound layer；
Step 07：Removal is located at the hard mask layer at the top of class oxidation membrane material, exposes the class oxidation membrane material
Top；
Step 08：The class oxidation membrane material is removed, while remaining hard mask layer is injury-free；
Step 09：The hard mask layer after removal is thinned.
2. the forming method of air-gap according to claim 1, which is characterized in that the hard mask layer is multilayered structure,
The step 06 includes：The multilayered structure is thinned downwards and retains the bottom of the multilayered structure.
3. the forming method of air-gap according to claim 2, which is characterized in that the material of the hard mask layer includes gold
Belong to compound or dielectric material.
4. the forming method of air-gap according to claim 2, which is characterized in that in the step 05, planarization process
At the top of the filling metallic copper, so that the top of the filling metallic copper is higher than the bottom of the multilayered structure, be less than the multilayer
The top of the bottom of structure.
5. the forming method of air-gap according to claim 1, which is characterized in that in the step 06, use is thinned
Method is dry etch process.
6. the forming method of air-gap according to claim 1, which is characterized in that in the step 06, the institute after being thinned
The thickness for stating hard mask layer is
7. the forming method of air-gap according to claim 1, which is characterized in that in the step 07, the removal of use
Method is wet-chemical chamber method.
8. the forming method of air-gap according to claim 7, which is characterized in that the medicine that the wet-chemical chamber method uses
Liquid is phosphoric acid, the temperature used for 150-170 DEG C, the etching speed that uses forThe etch period used for
2-5min。
9. the forming method of air-gap according to claim 1, which is characterized in that in the step 08, using hydrofluoric acid
Solution removes the class and aoxidizes membrane material.
10. the forming method of air-gap according to claim 9, which is characterized in that in the step 08, the hydrofluoric acid
In solution, the concentration ratio of water and hydrofluoric acid is 50:1~200:1, the time of removal is 2-10min.
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|---|---|---|---|---|
| CN101009266A (en) * | 2006-01-27 | 2007-08-01 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN101399222A (en) * | 2007-09-24 | 2009-04-01 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor elements having air gap |
| CN103367234A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
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| US8298911B2 (en) * | 2009-03-26 | 2012-10-30 | Samsung Electronics Co., Ltd. | Methods of forming wiring structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101009266A (en) * | 2006-01-27 | 2007-08-01 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN101399222A (en) * | 2007-09-24 | 2009-04-01 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor elements having air gap |
| CN103367234A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
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