CN104167224B - The method for reducing DRAM soft errors - Google Patents

Abstract

The invention discloses a kind of methods for reducing DRAM soft errors, this method being capable of active detecting soft error, intelligence reduces the incidence of soft error, so that the wrong digit in DRAM is maintained within the scope of DRAM error correction capability, until not having, an error has occurred, and DRAM restores normal condition, so as to improve the reliability of memory, availability and serviceability, this method can be used for providing the field of key task program and service for numerous clients, have a wide range of application, strong applicability.

Description

The method for reducing DRAM soft errors

Technical field

The present invention relates to a kind of design of calculator memory and application field more particularly to a kind of sides for reducing DRAM soft errors Method.

Background technology

At present, the reliability (reliability) of server, availability (availability) and serviceability (serviceability) the problem of being most important for contemporary IT enterprises, because these servers are needed for numerous visitors Family provides key task program (mission-critical applications) and service, such as database, corporate resources rule (ERP), User Resource Management (CRM), business intelligence application and high-end transacter etc. are drawn, once these application programs Failure is delivered, loss will be extremely expensive caused by server system is shut down.Therefore Intel Company manages in device chip and adds at which Extensive and powerful RAS functions are entered, error detection, correction, inhibition are provided for all processors, memory, I/O data paths And restore function, so as to which system be made more to tend to safety and stability.So-called RAS is exactly reliability (reliability), availability (availability) and the abbreviation of serviceability (serviceability), wherein.Reliability is exactly that solve data complete Property the problem of, availability is exactly to ensure that system no shutdown is run under performance minimal degradation, and how serviceability aiming at leading It is dynamic to handle already existing or potential erroneous components with passively simplified.RAS functional flow diagrams are as shown in Figure 1.Normal condition Lower system can carry out wrong prevention, Function detection and marked erroneous be carried out to data under error condition, if these mistakes It can correct, then carry out error correcting and be allowed to be restored to normal condition.Grave error will be isolated (mistake inhibition) simultaneously Record, then carry out system recovery, system and BIOS, firmware and operating system cooperate with restore or restart into So as to be restored under normal condition, system can not also shut down journey by being isolated or substituting defect firmware or increase hardware resource Lower completion reconfigures, and is restored to normal condition.

And memory (DRAM) mistake is to lead to the most common hardware error of computer crashes.Google companies and Toronto University announce a result of study show the data error rate of DRAM memory modules to be significantly larger than people's it is contemplated that and More likely become the arch-criminal of system in case of system halt and service disruption.This research employs up to a million Google servers, The result shows that there is about 8.2% to receive the shadow that can be corrected mistake in all DIMM (Dual-Inline-Memory-Modules) It rings, an average DIMM will occur correct mistake for 3700 times every year.This report is pointed out:" we have found EMS memory error for the first time Generally existing.About 1/3 at least encounters an EMS memory error every year in all equipment in use, and what is occurred every year on average corrects mistake It is mistaken for 22000 times.The data that are obtained in different platform are different, and the equipment of some platforms about 50% is by can correct mistake Influence, some be only 12%~27%." mistake can be generally divided into two kinds, soft error (soft error) and hard error (hard error)." soft error " problem refers to the chip interior caused by the nuclear particle for forming the radiation of earth low intensity background The change of charge storage state although this change will not generate physical damage to chip, will generate wrong data and cause The temporary derangement of equipment.It is more sensitive to the influence of background radiation in itself that the size of transistor constantly becomes each transistor of short metre for poems that contains relatively few syllables, And chip complexity increase substantially also imply that on chip certain part by influence of a soft error probability substantially It improves.Soft error is can be modified by reprogram.But in many cases, computer hardware used in us is really It is that can damage.Heat or manufacturing defect can cause component to wear over time, lead to electronics from a transistor It leaks into another transistor or the chip for being intended to transmission electric current is caused to break down.These are exactly so-called " hard error " (hard error).Hard error is cannot be by rewriteeing come modified.The scientist for designing next-generation computer chip carries on a shoulder pole very much The problem of heart " soft error ", this is because a very great factor：Power.In the feelings that next-generation super computer starts to reach the standard grade Under condition, they will possess more chips and smaller component.As transistor becomes less and less, these computers will need to get over Carry out more energy, particle could be prevented to impact it.

There are erasable (patrol scrub) process of inspection, Error Checking and Correcting for the RAS functions of EMS memory error (ECC), fine granularity memory mirror etc..When memory is read out detecting that the wrong and mistake is amendable, then will repair Data after just are write back so as to guarantee data integrity in memory, this process is just named inspection erasable process.ECC functions are to pass through Outer in original data bit that additional check bit is added to realize error detection and correction, ECC functions can allow mistake, and can By error correction, system to be enable to continue normally to operate, will not be interrupted because of mistake.If some critical applications Higher data reliability is needed, memory mirror allows for storing data in two different memory blocks, and almost can Enough handle all EMS memory errors, it is clear that this is using twice of memory size as cost.

Chinese patent (publication number：CN103365731A a kind of method for reducing processor soft error rate) is disclosed.Including： Prediction model construction step builds prediction model using the method for machine learning, processor can with low overhead be reduced to predict The processor best configuration of soft error rate；Recognizer segment step in program operation process, program is divided into several continuous Usability of program fragments；Statistical nature obtaining step within a bit of time of usability of program fragments initial launch, obtains the system of usability of program fragments Count feature；Best configuration prediction steps by the statistical nature input prediction model of acquisition, predict usability of program fragments and handle accordingly Device best configuration is as prediction result；Regulating step according to prediction result, adjusts the configuration of processor component, so as to keeping or In the case that person improves power dissipation ratio of performance, the soft error rate of processor is reduced.The invention is matched by dynamic regulation processor component It puts, reduce the purpose of processor soft error rate with realizing low overhead.

Although above-mentioned patent discloses the method for reducing processor soft error rate, but its technical solution for taking and this hair The method of bright taken reduction DRAM soft errors simultaneously differs.

Invention content

In view of the above problems, the present invention discloses a kind of method for reducing DRAM soft errors, to overcome the prior art In wrong data led to the problem of due to DRAM soft errors and cause the temporary derangement of equipment.

To achieve these goals, the application describes a kind of method for reducing DRAM soft errors, applied to department of computer science In system, wherein, include the following steps：

Step S1 carries out DRAM error detection to obtain the wrong digit of data in the DRAM；

Step S2, judges whether the wrong digit of data in the DRAM reaches early warning value, if it is not, then carrying out error correcting So that the DRAM restores normal condition, if so, carrying out step S3；

Step S3 increases charging voltage and/or improves refreshing frequency so that the wrong digit of data is small in the DRAM In the early warning value, continue step S2.

The method of above-mentioned reduction DRAM soft errors, wherein, maximum of the early warning value less than or equal to the DRAM is entangled Misplace number.

The method of above-mentioned reduction DRAM soft errors, wherein, the maximum error correction digit of the DRAM is less than or equal to described The highest error detection digit of DRAM.

The method of above-mentioned reduction DRAM soft errors, wherein, the department of computer science when the DRAM is in normal condition It unites and the data in the DRAM is carried out with wrong prevention.

The method of above-mentioned reduction DRAM soft errors, wherein, in the step S1, when the DRAM is in error condition When, it carries out DRAM error detection and marked erroneous is to obtain the wrong digit of data in the DRAM.

The method of above-mentioned reduction DRAM soft errors, wherein, in the step S3, increase charging voltage to after increasing Charging voltage is A times of former charging voltage, and refreshing frequency of the raising refreshing frequency to after increasing is a times of former refreshing frequency；

Wherein, the value of A and a is all higher than 1.

The method of above-mentioned reduction DRAM soft errors, wherein, in the step S2, the DRAM restores normal condition and includes The charging voltage reverts to former charging voltage, and the refreshing frequency reverts to former refreshing frequency.

The method of above-mentioned reduction DRAM soft errors, wherein, the DRAM is the memory of the computer system, and should DRAM includes a storage unit being made of NMOS transistor and capacitance, wordline and bit line；

The wordline is connect with the grid of the NMOS transistor, and the source electrode of the bit line and the NMOS transistor connects It connects, and the drain electrode of the NMOS transistor passes through the capacity earth；

Wherein, by increasing the source voltage of the NMOS transistor and/or improving the refreshing frequency of the capacitance, so that The wrong digit for obtaining data in the DRAM is less than the early warning value.

Foregoing invention has the following advantages that or advantageous effect：

It is disclosed by the invention it is a kind of reduce DRAM soft errors method, this method can active detecting soft error, intelligence drop The incidence of low soft error so that the wrong digit in DRAM is maintained within the scope of the error correcting capability of DRAM, until not having An error has occurred, and DRAM restores normal condition, so as to improve the reliability of memory (reliability), availability (availability) and serviceability (serviceability), this method can be used for providing key task for numerous clients Program and the field of service, have a wide range of application, strong applicability.

Specific description of the drawings

Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer Shape and advantage will become more apparent.Identical label indicates identical part in whole attached drawings.Not can according to than Example draws attached drawing, it is preferred that emphasis is shows the purport of the present invention.

Fig. 1 is the flow diagram of RAS functions in background of invention；

Fig. 2 is the structure diagram of DRAM memory cell in the embodiment of the present invention；

Fig. 3 is the structure diagram that DRAM memory cell charging voltage is improved in the embodiment of the present invention；

The flow diagram of the method for DRAM soft errors is reduced in Fig. 4 embodiment of the present invention.

Specific embodiment

The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention It is fixed.

The present embodiment is related to a kind of method for reducing DRAM soft errors, and applied in computer system, the DRAM is calculates The memory of machine system, the computer system can carry out the data in DRAM wrong prevention under normal condition, and this method include Following steps：

Step 1: carrying out DRAM error detection and marked erroneous is to obtain the wrong digit of data in DRAM.

Step 2: judge whether the wrong digit of data in DRAM reaches early warning value, if it is not, then by above computer system Error correcting is carried out so that DRAM restores normal condition (reverts to former charging voltage, refreshing frequency is restored including charging voltage For former refreshing frequency), if so, carrying out step 3.

Wherein, above-mentioned early warning value can be set according to specific detection demand, but the early warning value must be less than or equal to DRAM most Big error correction digit, and the maximum error correction digit of the DRAM must be less than or equal to the highest error detection digit of DRAM.

Step 3: increase charging voltage and/or improve refreshing frequency so that the wrong digit of data is less than in advance in DRAM Alert value, continues step 2.

Preferably, increase the A times of (A that charging voltage of the charging voltage to after increasing is former charging voltage in step 3> 1) a times of (a that refreshing frequency of the refreshing frequency to after increasing is former refreshing frequency, is improved>1).

Specifically, 4 present invention of attached drawing reduces the flow diagram of the method for DRAM soft errors, as shown in Figure 4：

In normal state, computer system can carry out the data in DRAM wrong prevention, but under error condition It must carry out DRAM detections and marked erroneous is to obtain the wrong digit n (error detection (n in corresponding diagram 4 of data in DRAM Position)), if these mistakes can be corrected, then computer system can carry out error correcting so that DRAM restores normal condition. Assuming that the highest error detection digit of DRAM is N, and DRAM can correct M therein, the i.e. highest correction digit of system It it is M, it is clear that M≤N.Assuming that in a certain section of time range, the data in a certain sector address space in DRAM are in error detection The wrong digit n that Shi Faxian is detected has continuously reached early warning value m (m≤M), i.e. n >=m, and n≤M, illustrates the number in the address It is higher according to the probability that soft error occurs, then the present invention can be taken to be directed to the solution of soft error, on the one hand can improve brush On the other hand new frequency can increase charging voltage, the storage unit in DRAM is made to restore to normal shape so as to correct soft error State.Above-mentioned early warning value m is related with the maximum error correction digit M of DRAM, and can be by system or the user configuration numerical value.By one section If the wrong digit n detected still reaches early warning value m after time, then on the one hand can continue with increased refreshing frequency brush Newly, on the other hand can continue to charge with increased charging voltage, until the wrong digit n that detected is less than early warning value m.Through System can be restored to normal condition after a period of time, and refresh cycle and charging voltage are also restored to normal condition.

In addition, illustrating the present invention can be made by improving refreshing frequency and/or increasing charging voltage reduction soft error The principle that storage unit in DRAM is restored to normal condition is as follows：

As shown in Fig. 2 the storage unit of a memory dram, the storage unit being made of NMOS transistor and capacitance, Wordline and bit line are formed, wherein, the grid connection of wordline and NMOS transistor, the source electrode connection of bit line and NMOS transistor, and The drain electrode of the NMOS transistor passes through capacity earth；The storage unit according to capacitance whether store charge store data " 1 " and “0”.When data are written into capacitance, wordline WL remains high level, and bit line BL is filled for high level Vdd to capacitance during one writing Electricity, bit line BL makes capacitance discharge for low level when writing " 0 "；When reading data from capacitance, wordline WL remains high level, electricity Hold to bit line BL and charge, by sense amplifier so as to read the data preserved in capacitance.When wordline WL is low level, charge It is stored in capacitance.Because of electric leakage, the charge of storage can gradually decrease, in order to keep data integrity, the storage unit of DRAM Have to periodic refresh.For DRAM, Q ends in fig. 2 will usually occur for soft error, when Q ends by external particles or Person's other conditions influence, such as alpha ray, it may occur that charge variation, if charge Q is largely lost in or generates a large amount of additional Charge, then the storage state of the storage unit may can change, and become " 0 " by " 1 " or become " 1 " by " 0 ".Thus It is found that in order to reduce the occurrence probability of soft error, can take increases charging voltage Vdd to A*Vdd sizes (i.e. increase NMOS crystal The source voltage of pipe), wherein A ＞ 1, preferred 1.1≤A≤1.5 (such as 1.1,1.2,1.3 or 1.5 etc.), as shown in Figure 3. The increase of charging voltage means that the charge Q of capacitance storage proportional can also increase, so as to influence probability of the external event to Q ends Also it can substantially reduce, so as to reduce soft error probability.The method that another kind reduces soft error occurrence probability is exactly to improve to refresh frequency Rate (improves refreshing frequency) by controlling the grid voltage of NMOS tube.Assuming that the original refreshing frequencys of DRAM are F, improve and refresh frequency Rate is to a*F, wherein a ＞ 1, preferred 2≤a≤4 (such as 2,3,3.5 or 4 etc.), for each unit, during refresh interval Between shorten, it is meant that flush to next time come before, the variation (including losing and increasing) of capacitive charge storage can also be reduced, Therefore influence probability of the external event to Q ends can also reduce, so as to reduce soft error probability.

With specific embodiment, the invention will be further elaborated below：

Assuming that DRAM error detection is able to detect that 8bit error bits, and can correct 7bit mistakes, it is assumed that early warning value m is 6bit.If find that detection error bit continuously reaches when carrying out error detection to a certain sector address space in the range of sometime 6bit is more, illustrates that the storage unit in next time range in the sector address space is subject to extraneous grain Son interferes and soft error occurs, and in order to reduce soft error incidence, is done using this solution for DRAM soft errors of the present invention Method takes following two modes to be modified：(1) increase self-refresh frequency, at present the refresh cycle universal DRAM be generally 64ms, then the refresh cycle can be reduced to 32ms or 16ms etc.；(2) increase the charging voltage of capacitance, if traditional charging Voltage is 1.8V, then can improve to 2.1V or 2.4V etc..It is improved by way of increasing self-refresh frequency and charging voltage The stability of DRAM memory cell, until the error bit detected is less than 6bit.After a period of time, DRAM can restore to just Under normal state, i.e. the refresh cycle restores to 64ms, and charging voltage is also restored to 1.8V.As it can be seen that the present invention is this soft for DRAM The solution of mistake can active detecting simultaneously can intelligently reduce soft error incidence, be maintained at the wrong digit in DRAM Within the scope of DRAM error correction capability, the data stability and reliability of DRAM are improved.

In conclusion a kind of method for reducing DRAM soft errors disclosed by the invention, this method being capable of active detecting soft error Accidentally, intelligence reduces the incidence of soft error so that and the wrong digit in DRAM is maintained within the scope of DRAM error correction capability, Until not having, an error has occurred, and DRAM restores normal condition, so as to improve the reliability of memory, availability and serviceability, This method can be used for providing the field of key task program and service for numerous clients, have a wide range of application, strong applicability.

It should be appreciated by those skilled in the art that those skilled in the art combine the prior art and above-described embodiment can be with Realize the change case, this will not be repeated here.Such change case does not affect the essence of the present invention, not superfluous herein It states.

Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field It applies；Any those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above Methods and technical content technical solution of the present invention is made many possible changes and modifications or be revised as equivalent variations etc. Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention In the range of technical solution protection.

Claims (5)

1. a kind of method for reducing DRAM soft errors, applied in computer system, which is characterized in that include the following steps：

Step S1 carries out DRAM error detection to obtain the wrong digit of data in the DRAM；

Step S2, judges whether the wrong digit of data in the DRAM reaches early warning value, if it is not, then carry out error correcting so that The DRAM restores normal condition, and when the DRAM is in normal condition the computer system to the number in the DRAM According to wrong prevention is carried out, if so, carrying out step S3；

Step S3 increases charging voltage and/or improves refreshing frequency so that the wrong digit of data is less than institute in the DRAM Early warning value is stated, continues step S2；

Wherein, the early warning value is less than or equal to the maximum error correction digit of the DRAM, and the maximum error correction digit of the DRAM Highest error detection digit less than or equal to the DRAM.

2. the method for DRAM soft errors is reduced as described in claim 1, which is characterized in that in the step S1, when described When DRAM is in error condition, carries out DRAM error detection and marked erroneous is to obtain the wrong digit of data in the DRAM.

3. the method for DRAM soft errors is reduced as described in claim 1, which is characterized in that in the step S3, increase is filled Charging voltage of the piezoelectric voltage to after increasing is A times of former charging voltage, and it is original to improve refreshing frequency of the refreshing frequency to after increasing A times of refreshing frequency；

Wherein, the value of A and a is all higher than 1.

4. the method for DRAM soft errors is reduced as claimed in claim 3, which is characterized in that in the step S2, the DRAM Restore normal condition and revert to former charging voltage including the charging voltage, the refreshing frequency reverts to former refreshing frequency.

5. the method for reducing DRAM soft errors such as claim 1-4 any one of them, which is characterized in that the DRAM is described The memory of computer system, and the DRAM includes a storage unit being made of NMOS transistor and capacitance, wordline and bit line；

The wordline is connect with the grid of the NMOS transistor, and the bit line is connect with the source electrode of the NMOS transistor, and The drain electrode of the NMOS transistor passes through the capacity earth；

Wherein, by increasing the source voltage of the NMOS transistor and/or improving the refreshing frequency of the capacitance, so that institute The wrong digit for stating data in DRAM is less than the early warning value.