CN104167224A - Method for reducing DRAM soft error - Google Patents
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Abstract
The invention discloses a method for reducing DRAM soft error. The method can actively detect the soft error and intelligently reduce occurrence rate of the soft error, so that error digits can be maintained within a range of DRAM error correction capacity until no error appears and DRAM returns to a normal state, thereby increasing reliability, usability and serviceability of a memory. The method can be used for providing key task procedures and service fields for customers, and has a wide application scope and high applicability.
Description
Technical field
The present invention relates to a kind of calculator memory design and application field, relate in particular to a kind of method of the DRAM of reduction soft error.
Background technology
At present, the reliability of server (reliability), availability (availability) and serviceability (serviceability) are vital problems for contemporary IT enterprises, because these servers need to provide mission critical program (mission-critical applications) and service for numerous clients, database for example, Enterprise Resources Planning (ERP), User Resource Management (CRM), business intelligence application and high-end transacter etc., once these application programs are paid unsuccessfully, server system is shut down and the loss that causes will be extremely expensive.Therefore Intel Company has added extensive and powerful RAS function in its processor chips, for all processors, internal memory, I/O data path provide error-detecting, correction, inhibition and restore funcitons, thereby makes system more be tending towards safety and stability.So-called RAS is exactly the abbreviation of reliability (reliability), availability (availability) and serviceability (serviceability), wherein.Reliability is exactly the problem that solves data integrity, and availability is guaranteed system no shutdown operation exactly under performance minimal degradation, and serviceability is exactly for how initiatively and passively to simplify and to process wrong assembly that existed or potential.RAS functional flow diagram as shown in Figure 1.Under normal condition, system can be carried out mistake prevention, under error condition, data is carried out to Function detection marked erroneous, if these mistakes can be revised, carries out so error correcting and makes it to return to normal condition.Grave error will be isolated (mistake inhibition) and record, then carry out system recovery, thereby system and BIOS, firmware and operating system collaborative work return under normal condition to recover or to restart process, system also can or increase hardware resource by isolation or replace defective firmware and complete and reconfigure under not shutting down, and returns to normal condition.
And internal memory (DRAM) mistake is the modal hard error that causes computer crashes.The result of study that Google company and University of Toronto announce shows, the data error rate of DRAM memory modules will be far away higher than people's anticipation, and more likely become the arch-criminal of system in case of system halt and service disruption.This research has adopted up to a million Google servers, result shows have about 8.2% to be subject to the impact that can correct mistakes in all DIMM (Dual-Inline-Memory-Modules), and an average DIMM will occur can correct mistakes for 3700 times every year.This report is pointed out: " we find EMS memory error ubiquity first.In all equipment in uses, about 1/3 at least runs into EMS memory error every year one time, and correcting mistakes of occurring is every year on average 22000 times.The data that draw in different platform are different, and the equipment of some platform nearly 50% is subject to the impact that can correct mistakes, and what have is only 12%～27%." mistake can be divided into two kinds, soft error (soft error) and hard error (hard error) conventionally." soft error " problem, refers to the change of the chip internal charge storage state being caused by the nuclear particle that forms the background radiation of earth low-intensity, although this change can not produce physical damage to chip, will produce misdata and cause the temporary derangement of equipment.Transistorized size constantly diminishes and makes each transistor itself more responsive on the impact of background radiation, and increasing substantially of chip complexity also means that on chip, certain part is significantly improved by the probability of the impact of a soft error.Soft error can be by programming correction again.But the computer hardware that in many cases, we use can damage really exactly.Heat or manufacturing defect can cause parts As time goes on to wear and tear, and cause electronics to leak into another transistor from a transistor, or cause the chip that is intended to transmission current to break down.These " hard error " (hard error) that are exactly so-called.Hard error can not be revised by rewriteeing.The scientist who is designing computer chip of future generation worries the problem of " soft error " very much, and this is because a very great factor: power.In the situation that super computer of future generation starts to reach the standard grade, they will have more chip and less parts.Along with transistor becomes more and more less, these computers will need increasing energy, could stop particle to impact it.
For the RAS function of EMS memory error, patrol and examine erasable (patrol scrub) process, Error Checking and Correcting (ECC), fine granularity memory mirror etc.Mistake when internal memory is read, detected and this mistake is amendable, thereby so revised data are write back in internal memory and guaranteed data integrity, this process is just the erasable process of patrolling and examining.ECC function is to realize error detection and correction by additional extra check bit in original data bit, and ECC function can be allowed mistake, and can make system be continued normal operation error correction, can not interrupt because of mistake.If some critical applications need higher data reliability, memory mirror just allows to store data in two different storage blocks, and almost can process all EMS memory error, and obviously this take twice memory size as cost.
Chinese patent (publication number: CN103365731A) disclose a kind of method that reduces processor soft error rate.Comprise: forecast model construction step, use the method for machine learning to build forecast model, predict the processor best configuration that can reduce to low expense processor soft error rate; Recognizer fragment step, in program operation process, is divided into some continuous usability of program fragments by program; Statistical nature obtaining step, within a bit of time of usability of program fragments initial launch, obtains the statistical nature of usability of program fragments; Best configuration prediction steps, by the statistical nature input prediction model obtaining, dopes the corresponding processor best configuration of usability of program fragments as predicting the outcome; Regulating step, according to predicting the outcome, regulates processor component configuration, thereby in the situation that keeping or improve power dissipation ratio of performance, reduces the soft error rate of processor.This invention is by dynamic adjustments processor component configuration, realizes low expense and reduce the object of processor soft error rate.
Although above-mentioned patent discloses the method that reduces processor soft error rate, the method for the reduction DRAM soft error that its technical scheme of taking is taked with the present invention is not identical.
Summary of the invention
For the problem of above-mentioned existence, the present invention discloses a kind of method of the DRAM of reduction soft error, to overcome in prior art because DRAM soft error produces misdata and cause the problem of the temporary derangement of equipment.
To achieve these goals, the application has recorded a kind of method of the DRAM of reduction soft error, is applied in computer system, wherein, comprises the steps:
Step S1, carries out DRAM error-detecting to obtain the wrong figure place of data in described DRAM;
Step S2, judges in described DRAM, whether the wrong figure place of data reaches early warning value, if not, carries out error correcting so that described DRAM recovers normal condition, if so, carries out step S3;
Step S3, increases charging voltage and/or improves refreshing frequency so that the wrong figure place of data is less than described early warning value in described DRAM, proceeds step S2.
The method of above-mentioned reduction DRAM soft error, wherein, described early warning value is less than or equal to the maximum error correction figure place of described DRAM.
The method of above-mentioned reduction DRAM soft error, wherein, the maximum error correction figure place of described DRAM is less than or equal to the highest error-detecting figure place of described DRAM.
The method of above-mentioned reduction DRAM soft error, wherein, when computer system described in described DRAM is during in normal condition is carried out mistake prevention to the data in described DRAM.
The method of above-mentioned reduction DRAM soft error, wherein, in described step S1, when described DRAM is during in error condition, carries out DRAM error-detecting marked erroneous to obtain the wrong figure place of data in described DRAM.
The method of above-mentioned reduction DRAM soft error, wherein, in described step S3, increases A that charging voltage to the charging voltage after increasing is former charging voltage doubly, improves a that refreshing frequency to the refreshing frequency after increasing is former refreshing frequency doubly;
Wherein, the value of A and a is all greater than 1.
The method of above-mentioned reduction DRAM soft error, wherein, in described step S2, described DRAM recovers normal condition and comprises that described charging voltage reverts to former charging voltage, and described refreshing frequency reverts to former refreshing frequency.
The method of above-mentioned reduction DRAM soft error, wherein, the internal memory that described DRAM is described computer system, and this DRAM comprises a storage unit consisting of nmos pass transistor and electric capacity, word line and bit line;
Described word line is connected with the grid of described nmos pass transistor, and described bit line is connected with the source electrode of described nmos pass transistor, and the drain electrode of this nmos pass transistor is by described capacity earth;
Wherein, by increasing the source class voltage of described nmos pass transistor and/or improving the refreshing frequency of described electric capacity, so that the wrong figure place of data is less than described early warning value in described DRAM.
Foregoing invention tool has the following advantages or beneficial effect:
A kind of method that reduces DRAM soft error disclosed by the invention, the method can active detecting soft error, intelligence reduces the incidence of soft error, make within wrong figure place in DRAM remains on the error correcting limit of power of DRAM, until there is no wrong generation, DRAM recovers normal condition, thereby reliability (reliability), availability (availability) and the serviceability (serviceability) of internal memory have been improved, the method can be used for providing for numerous clients the field of mission critical program and service, applied range, applicability is strong.
Concrete accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, the present invention and feature thereof, profile and advantage will become more apparent.In whole accompanying drawings, identical mark is indicated identical part.Can proportionally not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the schematic flow sheet of RAS function in background technology of the present invention;
Fig. 2 is the structural representation of DRAM storage unit in the embodiment of the present invention;
Fig. 3 is the structural representation that improves DRAM storage unit charging voltage in the embodiment of the present invention;
In Fig. 4 embodiment of the present invention, reduce the schematic flow sheet of the method for DRAM soft error.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
The present embodiment relates to a kind of method of the DRAM of reduction soft error, is applied in computer system, and the internal memory that this DRAM is computer system, under normal condition, this computer system can be carried out mistake prevention to the data in DRAM, and the method comprises the steps:
Step 1, carry out DRAM error-detecting marked erroneous to obtain the wrong figure place of data in DRAM.
Step 2, judge in DRAM, whether the wrong figure place of data reaches early warning value, if not, by above-mentioned computer system, carry out error correcting and (comprise that charging voltage reverts to former charging voltage so that DRAM recovers normal condition, refreshing frequency reverts to former refreshing frequency), if so, carry out step 3.
Wherein, above-mentioned early warning value can be according to concrete detection requirements set, but this early warning value must be less than or equal to the maximum error correction figure place of DRAM, and the maximum error correction figure place of this DRAM must be less than or equal to the highest error-detecting figure place of DRAM.
Step 3, increase charging voltage and/or raising refreshing frequency, so that the wrong figure place of data is less than early warning value in DRAM, are proceeded step 2.
Preferably, in step 3, increase A that charging voltage to the charging voltage after increasing is former charging voltage doubly (A>1), improve a that refreshing frequency to the refreshing frequency after increasing is former refreshing frequency doubly (a>1).
Concrete, accompanying drawing 4 the present invention reduce the schematic flow sheet of the method for DRAM soft error, as shown in Figure 4:
Under normal condition, computer system can be carried out mistake prevention to the data in DRAM, but under error condition, must carry out DRAM detection marked erroneous with the wrong figure place n (error-detecting in corresponding diagram 4 (n position)) of data in obtaining DRAM, if these mistakes can be corrected, computer system can be carried out error correcting so that DRAM recovers normal condition so.The highest error-detecting figure place of supposing DRAM is N, and DRAM can correct M position wherein, and the highest correction figure place of system is M position, obviously M≤N.Suppose in a certain section of time range, the data in a certain sector address space in DRAM find that when error-detecting the wrong figure place n detecting has reached early warning value m (m≤M) continuously, be n >=m, and n≤M, the probability that data generation soft error in this address is described is higher, can take the present invention is directed to so the solution of soft error, can improve refreshing frequency on the one hand, can increase charging voltage on the other hand, thereby revise soft error, make the storage unit in DRAM return to normal condition.Above-mentioned early warning value m is relevant with the maximum error correction figure place M of DRAM, and can configure this numerical value by system or user.If the wrong figure place n through detecting after a period of time still reaches early warning value m, the refreshing frequency that can continue to increase so on the one hand refreshes, the charging voltage charging that can continue to increase on the other hand, until the wrong figure place n detecting is lower than early warning value m.Through system after a period of time, can return under normal condition, refresh cycle and charging voltage also return to normal condition.
In addition, illustrating the present invention can reduce soft error to make storage unit in DRAM return to the principle of normal condition as follows by improving refreshing frequency and/or increasing charging voltage:
As shown in Figure 2 be the storage unit of a memory dram, the storage unit consisting of nmos pass transistor and electric capacity, word line and bit line form, and wherein, word line is connected with the grid of nmos pass transistor, bit line is connected with the source electrode of nmos pass transistor, and capacity earth is passed through in the drain electrode of this nmos pass transistor; According to electric capacity, whether stored charge is stored data " 1 " and " 0 " to this storage unit.When data writing in electric capacity, word line WL remains high level, during one writing bit line BL be high level Vdd to capacitor charging, while writing " 0 ", bit line BL is that low level makes capacitor discharge; When reading out data from electric capacity, word line WL remains high level, and electric capacity charges to bit line BL, thereby by sense amplifier, reads the data of preserving in electric capacity.When word line WL is low level, charge storage is in electric capacity.Because electric leakage, the electric charge of storage can reduce gradually, and in order to keep data integrity, the storage unit of DRAM must periodic refresh.Concerning DRAM, soft error will occur in the Q end in Fig. 2 conventionally, when Q end is subject to external particles or the impact of other conditions, alpha ray for example, may there is charge variation, if charge Q runs off in a large number or produces a large amount of additional charge, the store status of this storage unit just may change so, by " 1 ", is become " 0 " or is become " 1 " by " 0 ".Hence one can see that, in order to reduce the occurrence probability of soft error, can take to increase charging voltage Vdd to A*Vdd size (increasing the source class voltage of nmos pass transistor), wherein A > 1, preferred 1.1≤A≤1.5 (such as 1.1,1.2,1.3 or 1.5 etc.), as shown in Figure 3.The increase of charging voltage means that the charge Q of capacitance stores also can proportionally increase, thereby external event is on the affecting probability and also can greatly reduce of Q end, thereby reduces soft error probability.The another kind of way that reduces soft error occurrence probability improves refreshing frequency (improving refreshing frequency by controlling the grid voltage of NMOS pipe) exactly.Suppose that the original refreshing frequency of DRAM is F, improve refreshing frequency to a*F, wherein a > 1, preferred 2≤a≤4 (such as 2,3,3.5 or 4 etc.), concerning each unit, the refresh interval time shortens, mean upper once refresh arrival before, the variation of capacitive charge storage (comprise loss and increase) also can reduce, so external event is on the affecting probability and also can reduce of Q end, thereby reduces soft error probability.
With specific embodiment, the invention will be further elaborated below:
Suppose that DRAM error-detecting can detect 8bit error bit, and can revise 7bit mistake, suppose that early warning value m is 6bit.If find to detect error bit while error-detecting being carried out in a certain sector address space in scope sometime, reached continuously 6bit or more, explanation storage unit in this sector address space in ensuing time range is disturbed and generation soft error by foreign particles easily, in order to reduce soft error incidence, adopt this solution for DRAM soft error of the present invention, take following two kinds of modes to revise: (1) increases self-refresh frequency, the general refresh cycle of DRAM is generally 64ms at present, can reduce so the refresh cycle to 32ms or 16ms etc.; (2) increase the charging voltage of electric capacity, if traditional charging voltage is 1.8V, can be increased to 2.1V or 2.4V etc. so.By increasing the mode of self-refresh frequency and charging voltage, improve the stability of DRAM storage unit, until the error bit detecting is lower than 6bit.Through after a period of time, DRAM can return under normal condition, and the refresh cycle returns to 64ms, and charging voltage also returns to 1.8V.Visible, this solution for DRAM soft error of the present invention can active detecting and can intelligence be reduced soft error incidence, makes within wrong figure place in DRAM remains on DRAM error correcting limit of power, has improved data stability and the reliability of DRAM.
In sum, a kind of method that reduces DRAM soft error disclosed by the invention, the method can active detecting soft error, and intelligence reduces the incidence of soft error, makes within wrong figure place in DRAM remains on DRAM error correcting limit of power, until there is no wrong generation, DRAM recovers normal condition, thereby has improved reliability, availability and the serviceability of internal memory, and the method can be used for providing for numerous clients the field of mission critical program and service, applied range, applicability is strong.
It should be appreciated by those skilled in the art that those skilled in the art, realizing described variation example in conjunction with prior art and above-described embodiment, do not repeat at this.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. reduce a method for DRAM soft error, be applied to, in computer system, it is characterized in that, comprise the steps:
Step S1, carries out DRAM error-detecting to obtain the wrong figure place of data in described DRAM;
Step S2, judges in described DRAM, whether the wrong figure place of data reaches early warning value, if not, carries out error correcting so that described DRAM recovers normal condition, if so, carries out step S3;
Step S3, increases charging voltage and/or improves refreshing frequency so that the wrong figure place of data is less than described early warning value in described DRAM, proceeds step S2.
2. the method for reduction DRAM soft error as claimed in claim 1, is characterized in that, described early warning value is less than or equal to the maximum error correction figure place of described DRAM.
3. the method for reduction DRAM soft error as claimed in claim 2, is characterized in that, the maximum error correction figure place of described DRAM is less than or equal to the highest error-detecting figure place of described DRAM.
4. the method for reduction as claimed in claim 1 DRAM soft error, is characterized in that, when computer system described in described DRAM is during in normal condition, the data in described DRAM is carried out to mistake and prevents.
5. the method for reduction as claimed in claim 1 DRAM soft error, is characterized in that, in described step S1, when described DRAM is during in error condition, carries out DRAM error-detecting marked erroneous to obtain the wrong figure place of data in described DRAM.
6. the method for reduction as claimed in claim 1 DRAM soft error, it is characterized in that, in described step S3, increase A that charging voltage to the charging voltage after increasing is former charging voltage doubly, improve a that refreshing frequency to the refreshing frequency after increasing is former refreshing frequency doubly;
Wherein, the value of A and a is all greater than 1.
7. the method for reduction DRAM soft error as claimed in claim 6, is characterized in that, in described step S2, described DRAM recovers normal condition and comprises that described charging voltage reverts to former charging voltage, and described refreshing frequency reverts to former refreshing frequency.
8. the method for the reduction DRAM soft error as described in claim 1-7 any one, is characterized in that, the internal memory that described DRAM is described computer system, and this DRAM comprises a storage unit consisting of nmos pass transistor and electric capacity, word line and bit line;
Described word line is connected with the grid of described nmos pass transistor, and described bit line is connected with the source electrode of described nmos pass transistor, and the drain electrode of this nmos pass transistor is by described capacity earth;
Wherein, by increasing the source class voltage of described nmos pass transistor and/or improving the refreshing frequency of described electric capacity, so that the wrong figure place of data is less than described early warning value in described DRAM.
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Cited By (4)
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| CN107636623A (en) * | 2015-06-30 | 2018-01-26 | 惠普发展公司，有限责任合伙企业 | The period is scrubbed in inspection based on power state |
| CN112088364A (en) * | 2018-06-29 | 2020-12-15 | 国际商业机器公司 | Using a machine learning module to determine whether to perform error checking of a memory cell |
| WO2022151674A1 (en) * | 2021-01-15 | 2022-07-21 | 长鑫存储技术有限公司 | Method for measuring self-refresh frequency |
| US11929130B2 (en) | 2020-09-30 | 2024-03-12 | Changxin Memory Technologies, Inc. | Method and device for testing sr cycle as well as method and device for testing ar number |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107636623A (en) * | 2015-06-30 | 2018-01-26 | 惠普发展公司，有限责任合伙企业 | The period is scrubbed in inspection based on power state |
| CN112088364A (en) * | 2018-06-29 | 2020-12-15 | 国际商业机器公司 | Using a machine learning module to determine whether to perform error checking of a memory cell |
| US11929130B2 (en) | 2020-09-30 | 2024-03-12 | Changxin Memory Technologies, Inc. | Method and device for testing sr cycle as well as method and device for testing ar number |
| WO2022151674A1 (en) * | 2021-01-15 | 2022-07-21 | 长鑫存储技术有限公司 | Method for measuring self-refresh frequency |
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| CN104167224B (en) | 2018-06-29 |
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