CN104166523A - Storage and method for increasing data loading rate of computer system - Google Patents
Storage and method for increasing data loading rate of computer system Download PDFInfo
- Publication number
- CN104166523A CN104166523A CN201410390837.1A CN201410390837A CN104166523A CN 104166523 A CN104166523 A CN 104166523A CN 201410390837 A CN201410390837 A CN 201410390837A CN 104166523 A CN104166523 A CN 104166523A
- Authority
- CN
- China
- Prior art keywords
- memory block
- data
- computer system
- memory
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention relates to the field of the computer information technology, in particular to a storage and a method for increasing the data loading rate of a computer system. Part of startup loaded operating system programs or application programs are stored in a storage area, supporting programming operation, in the internal storage, so that the data loading rate of the system is increased, and meanwhile the data loading power consumption of the system is reduced.
Description
Technical field
The present invention relates to computer information technology field, relate in particular to a kind of storer and improve computer system the method that loads data rate.
Background technology
In traditional computer system stores hard disk, when user presses after key, power supply just starts to mainboard and the power supply of other hardware devices, processor starts initialization, then start to carry out BIOS (Basic Input/Output System, basic I/O) program, complete the initialization of power-on self-test and other hardware.After end, processor starts the ad-hoc location load operation system program from disk, import internal memory (DRAM) by the operating system program in disk, again by high-speed cache in internal memory importing tablet, high-speed cache can be divided into again L3 level, L2 level, L1 level, finally transfers to processor to process and return data or instruction again.
Storage system in computer system is just as a pyramid structure, as shown in Figure 1, toward pyramid top (as the direction of arrow in figure 1), memory capacity is less, and speed is faster, price is also higher, contrary, toward pyramid bottom (as the direction of arrow in figure 2), memory capacity is larger, speed is slower, and price is also lower.Disk is a kind of storer of machinery read-write, thereby read or write speed is well below the dominant frequency of processor, and this is also to cause one of slow-footed reason of system boot.And because each start process is all directed into identical operating system program in internal memory and high-speed cache again, and because internal memory need to constantly refresh to keep data, the electric leakage of high-speed cache is also very serious, thereby consumes a large amount of power consumptions.User's application program launching process and operating system are also similar, this conventional Starting mode one side disk reading speed has limited the speed of system loads data, cause system power dissipation very large by the storer of internal memory and these volatibility of high-speed cache on the other hand, this is that those skilled in the art are reluctant to see.
Summary of the invention
For the problem of above-mentioned existence, the present invention discloses a kind of storer and improves computer system the method that loads data rate.
A kind of storer, is applied in computer system, and wherein, described computing system comprises processor and external memory storage, stores the master data and the auxiliary data that after described computer system powers on, need loading in described external memory storage, and described storer comprises:
The first memory block, after powering on for described computer system, the described auxiliary data that processor need load from described external memory storage described in buffer memory;
The second memory block, supports programming operation, and by described programming operation by extremely described the second memory block of described primary data store;
Wherein, after described computer system powers on, the master data of described processor load store in described the second memory block and be stored in the auxiliary data in described external memory storage.
Above-mentioned storer, wherein, the physical address space of described the second memory block is physical address space continuous or that disperse.
Above-mentioned storer, wherein, before described the second memory block is programmed, the refreshing frequency of described the first memory block is less than the refreshing frequency of described the second memory block, and described the second memory block comprises the poorest storage unit in described storer.
Above-mentioned storer, wherein, described data comprise operating system program and/or application program.
A kind of method that improves computer system loading data rate, wherein, described computing system comprises high-speed cache on internal memory, processor, external memory storage and sheet, and described internal memory comprises the first memory block and support the second memory block of programming operation, and described method comprises the steps:
Step S1: the data that after in advance described computer system being powered on, described processor need load from described external memory storage are divided into master data and auxiliary data, and described master data is stored to described the second memory block by described programming operation;
Step S2: after described computer system powers on, described processor is loaded on described the first memory block by described auxiliary data from described external memory storage;
Step S3, continues the auxiliary data that is stored in the master data in described the second memory block and be stored in described the first memory block to be all loaded on described upper high-speed cache.
Above-mentioned raising computer system loads the method for data rate, wherein, before described the second memory block is programmed, the refreshing frequency of described the first memory block is less than the refreshing frequency of described the second memory block, and described the second memory block comprises the poorest storage unit in described internal memory.
Above-mentioned raising computer system loads the method for data rate, and wherein, described data comprise operating system program and/or application program;
Above-mentioned raising computer system loads the method for data rate, and wherein, in described step S1, the data that after by self-learning module, described computer system being powered on, described processor need load from described external memory storage are divided into master data and auxiliary data;
Described self-learning module realizes by software or hardware.
Above-mentioned raising computer system loads the method for data rate, and wherein, described programming operation is one-off programming, and described one-off programming is supported in described the first memory block;
Wherein, when being stored in described master data in described the second memory block while thering is the version of renewal, rejudge by described self-learning module whether the described master data that is stored in described the second memory block is hot operating systems program and/or hot application program, if, by the data of described renewal version by program storage in the part storage area of described the first memory block, and be inefficacy by the data markers being stored in described the second memory block, if not, the data in described the second memory block are directly labeled as to inefficacy.
Above-mentioned raising computer system loads the method for data rate, and wherein, described step S3 also comprises:
To be stored in the described primary data store of part in described the second memory block to described the first memory block, continue the part described master data of load store in described the first memory block to high-speed cache on described.
Above-mentioned raising computer system loads the method for data rate, and wherein, the physical address space of described the second memory block is physical address space continuous or that disperse.
Foregoing invention tool has the following advantages or beneficial effect:
Support in the memory block of programming operation to internal memory by operating system program or application storage that part start is loaded, thereby in having improved the speed of system loads data, reduced the power consumption of system loads data.
Concrete brief description of the drawings
By reading the detailed description of non-limiting example being done with reference to the following drawings, the present invention and feature thereof, profile and advantage will become more apparent.In whole accompanying drawings, identical mark is indicated identical part.Can proportionally not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the storage system schematic diagram in conventional computer system;
Fig. 2 is internal storage structure schematic diagram of the present invention;
Fig. 3 is that memory of the present invention region is divided and the schematic diagram that is related to of the poorest storage unit;
Fig. 4 is storage area partition structure schematic diagram in internal memory of the present invention;
Fig. 5 is the present invention's storage area inner structure able to programme schematic diagram;
Fig. 6 is the method schematic diagram that the present invention improves operating system program loading speed;
Fig. 7 is the method schematic diagram that the present invention improves application program loading speed;
Fig. 8 is the method schematic diagram that the present invention improves operating system or application program loading speed;
Fig. 9 is the process flow diagram that the present invention improves the method for computer system loading data rate.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
One can realize the able to programme of storer based on high-k dielectric metal gate (HKMG, High K Metal Gate) DRAM technique.HKMG technique is exactly to use the material of high-k to substitute SiO
2as gate dielectric layer, DRAM technique based on HKMG can make the storage unit in DRAM can realize one-off programming (OTP as fuse (fuse), one time programmable) and repeatedly programming (MTP, multi-time programmable).By this one-off programming or repeatedly programming, can make these storage unit without refreshing, the retention time extends greatly, thereby has reduced the power consumption of system.
The present embodiment provides a kind of storer, is applied in computer system, and this computing system comprises processor and external memory storage, stores the master data and the auxiliary data that after computer system powers on, need loading in external memory storage.Concrete, this storer comprises: the first memory block and the second memory block (logically this storer being divided into the first memory block and the second memory block), after the first memory block powers on for computer system, the auxiliary data that cache processor need load from external memory storage; Programming operation (support one-time programming or repeatedly programming) is supported in the second memory block, and by programming operation by primary data store to this second memory block; Wherein, after computer system starting powers on, the master data of processor load store in the second memory block and be stored in the auxiliary data in external memory storage.
Preferably, before described the second memory block is programmed, the refreshing frequency of the first memory block is less than the refreshing frequency of the second memory block.
Preferably, the second memory block comprises the poorest storage unit in storer.
This storer can be used as on internal memory (Main Memory) or sheet high-speed cache (Cache) and uses, and need to regularly refresh that (refresh cycle is t); And in this storer, each storage unit supports one-time programming even repeatedly to programme; And after programming, (T is far longer than t) not need refresh operation also can keep the programming value T time; For one-time programming, again without any need for refresh operation.As shown in Figure 2, storer A of the present invention is logically divided into the first memory block B and the second memory block C, wherein, the first memory block B is a part of original storage area A, the second memory block C is another part of original storage area A, has just become by one-time programming or the memory block of repeatedly programming.In an embodiment of the present invention, the physical address space of the second memory block C can be continuous, also can disperse.
As shown in Figure 9: the present embodiment has also been recorded a kind of method that improves computer system loading data rate, this computing system comprises internal memory, processor, high-speed cache on external memory storage and sheet, in an embodiment of the present invention, utilize storer in above-described embodiment internal memory as this computer system, certainly, in other embodiments of the invention, also can utilize storer in above-described embodiment as high-speed cache on what sheet of certain one-level of computer system or certain, its embodiment with utilize the storer in above-described embodiment roughly the same as the embodiment of the internal memory of this computer system, at this, just it will not go into details, this internal memory comprises the second memory block of the first memory block and support programming operation in the present embodiment, concrete the method comprises the steps:
Step S1: after in advance computer system being powered on, the data (these data comprise operating system program and/or application program) that processor need load from external memory storage are divided into master data and auxiliary data, and master data is stored to the second memory block by programming operation, preferably, by self-learning module, the computer system data that preprocessor need load from external memory storage that power on are divided into master data and auxiliary data.
Step S2: after computer system powers on, processor just auxiliary data is loaded on the first memory block from external memory storage, this is because master data is stored in internal memory, so after computer system powers on, processor only need be loaded on auxiliary data in the first memory block.
Step S3, continues the auxiliary data that is stored in the master data in the second memory block and be stored in the first memory block to be all loaded on high-speed cache on sheet.Preferably, by behind part primary data store to the first memory block being stored in the second memory block, continue this part master data in the first memory block of load store to high-speed cache on sheet.
Wherein, master data comprises part operation system (hot operating systems) and/or the user's some or all of user application that be most interested in or that frequently called (hot application program) that each start preprocessor can load, the second memory block C can store the part operation system that each start preprocessor can load, also can store some or all of user application that user is most interested in or that frequently called, auxiliary data comprises other data except master data.The master data being stored in the second memory block C is by computing machine, within a period of time, (this period of time can be one day by self-learning module, two days or one week etc., concrete, can arrange according to demand) thus the analysis of starting up operation system and application program called and self study determines which part starting up operation system program or user application are stored in the second memory block C, the data that processor need load during by computer system starting by self-learning module are divided into master data and auxiliary data, this self-learning module can realize by software or hardware.
In an embodiment of the present invention, the second memory block C can cover the poorest storage unit (tail bits) in this storer, and after the second memory block C is programmed, the refresh time of the first memory block B just can improve like this, refreshes power consumption thereby reduce.As shown in Figure 3, the second memory block C has covered the tail end distributive province in storer, and the first memory block B concentrates on the storage unit of distribution, after to the second memory block C programming, the first memory block B just can bring up to T2 (wherein T2 is much larger than T1) by T1 by the refresh cycle, ordinate in Fig. 2 represents cumulative probability, and horizontal ordinate represents retention time/ms.
As shown in Figure 4, the second memory block C by C0, C1 until Cn-1 form, C0, C1 until minimum base unit corresponding to Cn-1 for refreshing bundle (refresh bundle), can be for example all storage unit on a bit lines (WL), all storage unit on also can multiple bit lines etc.The poorest storage unit (i.e. the poorest storage unit) of data hold time in memory array be positioned at C0, C1 ..., in array in Cn-1, as shown in Figure 5.In the second memory block C, also can comprise those containing row or the row of poor storage unit.The benefit of doing is like this to improve the performance of system.For example, in the second memory block C, store starting up operation system information, due to C0, C1 until Cn-1 may be in physical distribution disperses very much, processor performance in the time of load operation system information will decline so, in order to improve system performance, the second memory block C also can comprise those containing row or the row of poor storage unit, for example this section of continuous amount of physical memory of the C0 to C1 in Fig. 4, tundish has contained or not the storage area of poor storage unit, if this part address space is being deposited starting up operation system information, so in the time that processor loads this part continuous address space data, the performance of system can obviously improve.
For one-off programming (OTP), after the information being programmed in the second memory block C lost efficacy, these information will can not accessed by processor.So-called inefficacy, the corresponding content in nonvolatile memory of information in the second memory block C has been updated exactly, the hot operating systems and/or the hot running program correspondence that are stored in the second memory block C (have for example had the version of renewal in nonvolatile memory, application program QQ2013 storage of versions is in the second memory block, but the content in nonvolatile memory that this application program QQ is corresponding has been updated, as be updated to QQ2014 version), if upgrade the data of version or starting up operation system program or be the most invoked hot application program (can judge by self-learning module) in a period of time, be programmed in storer in other physical address, become the second new memory block C, because the second memory block C is one-off programming, thereby old data will lose efficacy, and can not accessed by processor again, if the data of upgrading in nonvolatile memory are after self-learning module statistics, and be no longer starting up operation system program or the most frequent invoked program (being no longer hot operating systems program or hot application program) in a period of time, the start hot operating systems program that recent statistics can be gone out or the most frequent invoked hot application storage are in other physical address in novel storer, also or no longer programme, because the refreshable high speed access region area of main memory (Main Memory) self (i.e. the first memory block B) is too small not, the benefit now obtaining refreshes exactly power consumption and greatly reduces.
For can repeatedly programme (MTP), the information being stored in the second memory block C can be by self-learning module regular update, that is to say, after in starting up operation system or user application, the most frequent invoked part changes, self-learning module updates stored in the information in the second memory block C by analysis meeting.
Concrete, the operating system loading for start, after the self study of a period of time, every subsystem operating system that preprocessor need to load that powers on is divided into two parts by self-learning module, Do and Dp, and the program information Dp that the most frequently loads and call after processor is powered at every turn writes in the second memory block C in internal memory of the present invention, as shown in Figure 6 by programming operation.And in the time of computer system starting next time, only a part of Do of operating system need be imported to internal memory by for example disk of external memory storage or solid state hard disc, another part Dp of operating system is without import to internal memory from external memory storage again, thereby greatly save system start-up time, also reduced the power consumption that imports Dp from external memory storage.
Application programs, after the self study of a period of time, self-learning module is also divided into two parts by application program, Eo and Ep, and the application information Ep that processor is the most frequently called writes in the second memory block C in internal memory of the present invention, as shown in Figure 7 by programming.And instantly when this application program of one-shot, only a part of Eo of this application program need be imported to internal memory by for example disk of external memory storage or solid state hard disc, another part Ep of application program is without import to internal memory from external memory storage again, thereby greatly save the start-up time of application program, also reduced the power consumption that imports Ep from external memory storage.The contrast of sort memory of the present invention and traditional DRAM internal memory is as shown in table 1.Visible, storer contrast convential memory of the present invention, application one-time programming and repeatedly programming technique can improve the refresh cycle of storer, and refresh power consumption and also can greatly reduce.
| ? | Tradition DRAM internal memory | Sort memory of the present invention is as internal memory |
| Refresh cycle | Short | Long |
| Refresh power consumption | Larger | Low |
Table 1
This raising computer system of the present invention loads the method for data rate and the method contrast of traditional computer loading data rate is as shown in table 2, the method of this raising computer system of visible the present invention loading speed can reduce the power consumption of system greatly, improves the speed of system loads data.
Table 2
In addition, because the poorest storage unit distribution may be more discrete, the part operation system program Dp or the application program Ep that cause being stored in the second memory block C also relatively disperse, thereby strengthen the difficulty of processor to its addressing, the hit rate that for example may reduce high-speed cache, causes system performance to decrease.Now, can be by being first directed in the first relatively continuous memory block B of address space in internal memory being stored in most of operating system program Dp in the second memory block C or application program Ep, then in importing tablet in high-speed cache, as shown in Figure 8.Obviously the speed that, data second memory block C from internal memory is imported to the first memory block B is also far longer than the speed that imports internal memory from external memory storage.
Lifting one below specifically should be used for further setting forth.
Supposing has 80 storage blocks in the novel storer internal memory for a 4GB, and the refresh cycle can be 64ms.Suppose to keep data capability to be positioned at 20 storage blocks wherein lower than the poorest storage unit of 512ms, using these 20 storage blocks as programmable the second memory block C, capacity has 1GB, remains 60 storage blocks as the first memory block B.After the second memory block C able to programme is programmed, the refresh cycle can be increased to 512ms, compares the refresh cycle of the 64ms of traditional DRAM internal memory, has improved 8 times, that is to say and has refreshed power-dissipation-reduced 8 times.If the half information in the operating system that needs to load by powering on is stored in programmable the second memory block C, so every subsystem powers on and imports power consumption and can reduce again one times, and system also can double start-up time.Method advantage compared with traditional approach of this raising computing machine loading of the present invention data rate is as shown in table 3.
| Contrast | Advantage |
| Refresh power consumption | Reduce by 8 times |
| Refresh cycle | Improve 8 times |
| Data importing power consumption | Reduce by 1 times |
| System toggle speed | Improve 1 times |
Table 3
It should be appreciated by those skilled in the art that those skilled in the art, realizing described variation example in conjunction with prior art and above-described embodiment, do not repeat at this.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (11)
1. a storer, be applied in computer system, it is characterized in that, described computing system comprises processor and external memory storage, in described external memory storage, store the master data and the auxiliary data that after described computer system powers on, need loading, described storer comprises:
The first memory block, after powering on for described computer system, the described auxiliary data that processor need load from described external memory storage described in buffer memory;
The second memory block, supports programming operation, and by described programming operation by extremely described the second memory block of described primary data store;
Wherein, after described computer system powers on, the master data of described processor load store in described the second memory block and be stored in the auxiliary data in described external memory storage.
2. storer as claimed in claim 1, is characterized in that, the physical address space of described the second memory block is physical address space continuous or that disperse.
3. storer as claimed in claim 1, it is characterized in that, before described the second memory block is programmed, the refreshing frequency of described the first memory block is less than the refreshing frequency of described the second memory block, and described the second memory block comprises the poorest storage unit in described storer.
4. storer as claimed in claim 1, is characterized in that, described data comprise operating system program and/or application program.
5. one kind is improved the method for computer system loading data rate, it is characterized in that, described computing system comprises high-speed cache on internal memory, processor, external memory storage and sheet, and described internal memory comprises the first memory block and support the second memory block of programming operation, and described method comprises the steps:
Step S1: the data that after in advance described computer system being powered on, described processor need load from described external memory storage are divided into master data and auxiliary data, and described master data is stored to described the second memory block by described programming operation;
Step S2: after described computer system powers on, described processor is loaded on described the first memory block by described auxiliary data from described external memory storage;
Step S3, continues the auxiliary data that is stored in the master data in described the second memory block and be stored in described the first memory block to be all loaded on described upper high-speed cache.
6. improve as claimed in claim 5 the method that computer system loads data rate, it is characterized in that, before described the second memory block is programmed, the refreshing frequency of described the first memory block is less than the refreshing frequency of described the second memory block, and described the second memory block comprises the poorest storage unit in described internal memory.
7. improve as claimed in claim 5 the method that computer system loads data rate, it is characterized in that, described data comprise operating system program and/or application program.
8. improve as claimed in claim 7 the method that computer system loads data rate, it is characterized in that, in described step S1, the data that after by self-learning module, described computer system being powered on, described processor need load from described external memory storage are divided into master data and auxiliary data;
Described self-learning module realizes by software or hardware.
9. improve as claimed in claim 8 the method that computer system loads data rate, it is characterized in that, described programming operation is one-off programming, and described one-off programming is supported in described the first memory block;
Wherein, when being stored in described master data in described the second memory block while thering is the version of renewal, rejudge by described self-learning module whether the described master data that is stored in described the second memory block is hot operating systems program and/or hot application program, if, by the data of described renewal version by program storage in the part storage area of described the first memory block, and be inefficacy by the data markers being stored in described the second memory block, if not, the data in described the second memory block are directly labeled as to inefficacy.
10. improve as claimed in claim 5 the method that computer system loads data rate, it is characterized in that, described step S3 also comprises:
To be stored in the described primary data store of part in described the second memory block to described the first memory block, continue the part described master data of load store in described the first memory block to high-speed cache on described.
11. improve the method for computer system loading data rate as claimed in claim 5, it is characterized in that, the physical address space of described the second memory block is physical address space continuous or that disperse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410390837.1A CN104166523B (en) | 2014-08-08 | 2014-08-08 | A kind of memory and the method for improving computer system loading data rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410390837.1A CN104166523B (en) | 2014-08-08 | 2014-08-08 | A kind of memory and the method for improving computer system loading data rate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104166523A true CN104166523A (en) | 2014-11-26 |
| CN104166523B CN104166523B (en) | 2018-04-20 |
Family
ID=51910364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410390837.1A Active CN104166523B (en) | 2014-08-08 | 2014-08-08 | A kind of memory and the method for improving computer system loading data rate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104166523B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708542A (en) * | 2015-07-17 | 2017-05-24 | 中兴通讯股份有限公司 | Code loading method and device of embedded operating system |
| CN108306913A (en) * | 2017-01-12 | 2018-07-20 | 中兴通讯股份有限公司 | A kind of data processing method, device, computer readable storage medium and terminal |
| WO2021238249A1 (en) * | 2020-05-28 | 2021-12-02 | 浪潮电子信息产业股份有限公司 | Data storage method, apparatus, and device, and readable storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1784486A (en) * | 2003-04-17 | 2006-06-07 | 宝洁公司 | Volatile material delivery method |
| CN102202129A (en) * | 2010-03-23 | 2011-09-28 | 广州盛华信息技术有限公司 | Method for loading mobile phone operating system |
| CN103593324A (en) * | 2013-11-12 | 2014-02-19 | 上海新储集成电路有限公司 | Quick-start and low-power-consumption computer system-on-chip with self-learning function |
| US20140156810A1 (en) * | 2012-05-15 | 2014-06-05 | Tencent Technology (Shenzhen) Company Limited | Method and system for loading file in webgame |
| CN103927203A (en) * | 2014-03-26 | 2014-07-16 | 上海新储集成电路有限公司 | Computer system and control method |
-
2014
- 2014-08-08 CN CN201410390837.1A patent/CN104166523B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1784486A (en) * | 2003-04-17 | 2006-06-07 | 宝洁公司 | Volatile material delivery method |
| CN102202129A (en) * | 2010-03-23 | 2011-09-28 | 广州盛华信息技术有限公司 | Method for loading mobile phone operating system |
| US20140156810A1 (en) * | 2012-05-15 | 2014-06-05 | Tencent Technology (Shenzhen) Company Limited | Method and system for loading file in webgame |
| CN103593324A (en) * | 2013-11-12 | 2014-02-19 | 上海新储集成电路有限公司 | Quick-start and low-power-consumption computer system-on-chip with self-learning function |
| CN103927203A (en) * | 2014-03-26 | 2014-07-16 | 上海新储集成电路有限公司 | Computer system and control method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708542A (en) * | 2015-07-17 | 2017-05-24 | 中兴通讯股份有限公司 | Code loading method and device of embedded operating system |
| CN108306913A (en) * | 2017-01-12 | 2018-07-20 | 中兴通讯股份有限公司 | A kind of data processing method, device, computer readable storage medium and terminal |
| WO2021238249A1 (en) * | 2020-05-28 | 2021-12-02 | 浪潮电子信息产业股份有限公司 | Data storage method, apparatus, and device, and readable storage medium |
| US11698730B2 (en) | 2020-05-28 | 2023-07-11 | Inspur Electronic Information Industry Co., Ltd. | Data storage method, apparatus, and device, and readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104166523B (en) | 2018-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11625321B2 (en) | Apparatuses and methods for memory address translation during block migration using depth mapping table based on mapping state | |
| US20120159040A1 (en) | Auxiliary Interface for Non-Volatile Memory System | |
| CN106462410B (en) | Apparatus and method for accelerating boot time zeroing of memory | |
| US10878880B2 (en) | Selective volatile memory refresh via memory-side data valid indication | |
| CN105808455B (en) | Memory access method, storage-class memory and computer system | |
| US20060181949A1 (en) | Operating system-independent memory power management | |
| US20170052727A1 (en) | System and method for reducing power consumption of memory | |
| US20040268031A1 (en) | System and method for managing data in memory for reducing power consumption | |
| KR102525229B1 (en) | Memory module and system including the same | |
| TWI224728B (en) | Method and related apparatus for maintaining stored data of a dynamic random access memory | |
| US20140068172A1 (en) | Selective refresh with software components | |
| CN100377086C (en) | Method for realizing operating procedure directly from file system in embedded system | |
| CN105607862A (en) | Solid state disk capable of combining DRAM (Dynamic Random Access Memory) with MRAM (Magnetic Random Access Memory) and being provided with backup power | |
| CN105608013B (en) | A kind of the storage card control chip and storage card of integrated MRAM | |
| CN104166523A (en) | Storage and method for increasing data loading rate of computer system | |
| CN104995611A (en) | Systems and methods for accessing memory | |
| CN100377118C (en) | Built-in file system realization based on SRAM | |
| US20150277541A1 (en) | L2 cache retention mode | |
| US20190114177A1 (en) | Data storage device and method for operating non-volatile memory | |
| CN105653468B (en) | A kind of storage device using MRAM | |
| CN105608014B (en) | A kind of storage device using MRAM | |
| US11106559B2 (en) | Memory controller and memory system including the memory controller | |
| CN108062203B (en) | Flash memory data management method and device and memory | |
| CN101938594A (en) | Volume saving method for digital television set top box | |
| TWI453747B (en) | Method for managing a plurality of blocks of a flash memory, and associated memory device and controller thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |