CN104158535A - Frequency and voltage convertor - Google Patents
Frequency and voltage convertor Download PDFInfo
- Publication number
- CN104158535A CN104158535A CN201410352497.3A CN201410352497A CN104158535A CN 104158535 A CN104158535 A CN 104158535A CN 201410352497 A CN201410352497 A CN 201410352497A CN 104158535 A CN104158535 A CN 104158535A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- level
- significant level
- switch
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a frequency and voltage convertor. The frequency and voltage convertor comprises a constant-current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first voltage storage, a second voltage storage and a third voltage storage, wherein the first switch, the second switch, the third switch, the fourth switch and the fifth switch are switched on or switched off under the control of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal and a fifth clock signal, so that voltages corresponding to the input clock signals are generated.
Description
Technical field
The present invention relates to a kind of transducer, more particularly, relate to a kind of FV convertor.
Background technology
FV convertor is widely used in the control procedure of the control appliances such as velocity pick-up, tachometer, cruise.Therefore, the conversion accuracy of FV convertor directly affects the control precision of control appliance.Yet the FV convertor of using at present is easily subject to the impact of technique, supply voltage, ambient temperature in the course of the work, thus the conversion accuracy that impact is voltage by frequency inverted.
Therefore, need the high FV convertor of a kind of conversion accuracy.
Summary of the invention
The object of the present invention is to provide a kind of FV convertor, thereby improve the conversion accuracy that is voltage by frequency inverted.
The invention provides a kind of FV convertor, comprise: constant-current source, the first switch, second switch, the 3rd switch, the 4th switch, the 5th switch, the first voltage memory, second voltage memory, tertiary voltage memory, wherein, the first link of the first switch is connected to constant-current source, the second link ground connection of the first switch, the control end of the first switch receives the first clock signal, the first link of second switch is connected to constant-current source, the second link of second switch is connected to the first end of the first voltage memory, the second end ground connection of the first voltage memory, the control end of second switch receives second clock signal, the first link of the 3rd switch is connected to constant-current source, the second link of the 3rd switch is connected to the first end of second voltage memory, the second end ground connection of second voltage memory, the control end of the 3rd switch receives the 3rd clock signal, the first link of the 4th switch is connected to the first end of second voltage memory, the second link of the 4th switch is connected to the first end of tertiary voltage memory, the second end ground connection of tertiary voltage memory, the control end of the 4th switch receives the 4th clock signal, the first link of the 5th switch is connected to the first end of second voltage memory, the second link ground connection of the 5th switch, the control end of the 5th switch receives the 5th clock signal.
Alternatively, the first end of tertiary voltage memory is as output, the significant level conducting of the first clock signal that the first switching response receives in the control end of the first switch, the significant level conducting of the second clock signal that second switch receives in response to the control end of second switch, the significant level conducting of the 3rd clock signal that the 3rd switching response receives in the control end of the 3rd switch, the significant level conducting of the 4th clock signal that the 4th switching response receives in the control end of the 4th switch, the significant level conducting of the 5th clock signal that the 5th switching response receives in the control end of the 5th switch.
Alternatively, also comprise: clock circuit, signal based on input produces the first clock signal, second clock signal, 3rd clock signal, 4th clock signal, 5th clock signal, wherein, the first clock signal has identical frequency to the 5th clock signal, and the first clock signal circulates to time started and the end time of the significant level of the 5th clock signal according to following order: the significant level of end time < first clock signal of the significant level of end time < the 3rd clock signal of the significant level of time started < first clock signal of the significant level of end time < the 3rd clock signal of the significant level of the 5th clock signal time started≤time started of significant level of end time < the 5th clock signal of significant level of end time < the 4th clock signal of significant level of second clock signal, and, the significant level of second clock signal time started≤end time of significant level of the 5th clock signal, or, the time started of the significant level of time started < the 3rd clock signal of the significant level of the end time < second clock signal of the significant level of the 5th clock signal, and, the time started of the significant level of time started < first clock signal of the significant level of end time < the 4th clock signal of the significant level of the 3rd clock signal, or, the significant level of the first clock signal time started≤the 4th clock signal significant level time started≤end time of significant level of second clock signal, or, the end time of the significant level of time started < the 4th clock signal of the significant level of end time < the 4th clock signal of the significant level of second clock signal, wherein, the first clock signal comprises respectively significant level and non-effective level to each cycle of the 5th clock signal, the first switching response disconnects in the non-effective level of the first clock signal that the control end of the first switch receives, second switch disconnects in response to the non-effective level of the second clock signal that the control end of second switch receives, 3rd switching response disconnects in the non-effective level of the 3rd clock signal that the control end of the 3rd switch receives, 4th switching response disconnects in the non-effective level of the 4th clock signal that the control end of the 4th switch receives, 5th switching response disconnects in the non-effective level of the 5th clock signal that the control end of the 5th switch receives.
Alternatively, the significant level of the first clock signal is a kind of in high level and low level, the non-effective level of the first clock signal is the another kind in high level and low level, the significant level of second clock signal is a kind of in high level and low level, the non-effective level of second clock signal is the another kind in high level and low level, the significant level of the 3rd clock signal is a kind of in high level and low level, the non-effective level of the 3rd clock signal is the another kind in high level and low level, the significant level of the 4th clock signal is a kind of in high level and low level, the non-effective level of the 4th clock signal is the another kind in high level and low level, the significant level of the 5th clock signal is a kind of in high level and low level, the non-effective level of the 5th clock signal is the another kind in high level and low level.
Alternatively, the frequency of the first clock signal to the five clock signals is monotonic functional relationship with the frequency of the signal of inputting respectively.
Alternatively, described clock circuit comprises: phase-shifting unit, utilize the signal of input to produce the 6th identical clock signal of frequency, the 7th clock signal, the 8th clock signal, wherein, the duty ratio of the 6th clock signal to the eight clock signals is identical, and the time started of the significant level of the 7th clock signal is within the duration of the significant level of the 6th clock signal, the time started of the significant level of the 8th clock signal is within the duration of the significant level of the 7th clock signal, and between the time started of the significant level of the time started of the significant level of the 6th clock signal and the 7th clock signal interval greater than 0 and be less than the 6th clock signal cycle 1/3rd, between the time started of the significant level of the time started of the significant level of the 7th clock signal and the 8th clock signal interval greater than 0 and be less than the 6th clock signal cycle 1/3rd, frequency-halving circuit, the 6th clock signal is carried out to n two divided-frequency and produce the 9th clock signal, the 6th clock signal is carried out to n+2 two divided-frequency and produce the tenth clock signal, the 7th clock signal is carried out to n+1 the two divided-frequency signal that n+1 two divided-frequency obtains the 7th clock signal, described n+1 two divided-frequency signal carried out oppositely producing the 11 clock signal, the 7th clock signal is carried out to n+2 the two divided-frequency signal that n+2 two divided-frequency obtains the 7th clock signal, n+2 two divided-frequency signal of the 7th clock signal carried out oppositely producing the 12 clock signal, the 8th clock signal is carried out to n+1 two divided-frequency and produce the 13 clock signal, the 8th clock signal is carried out to n+2 the two divided-frequency signal that n+2 two divided-frequency obtains the 8th clock signal, n+2 two divided-frequency signal of the 8th clock signal carried out oppositely producing the first clock signal, wherein, n is more than or equal to 0 integer, n+2 two divided-frequency signal of the 7th clock signal is the 3rd clock signal, n+2 two divided-frequency signal of the 8th clock signal is the 14 clock signal, the first logical operation circuit, the tenth clock signal and the 14 clock signal that frequency-halving circuit is produced are carried out logic OR computing, to export second clock signal, the second logical operation circuit, the 12 clock signal and the 13 clock signal that frequency-halving circuit is produced are carried out logic and operation, to export the 4th clock signal, the 3rd logical operation circuit, the 9th clock signal, the 11 clock signal, the 12 clock signal that frequency-halving circuit is produced are carried out logic and operation, to export the 5th clock signal.
Alternatively, each cycle of the 6th clock signal to the eight clock signals comprises respectively significant level and non-effective level, wherein, the significant level of the 6th clock signal to the eight clock signals is high level, and the non-effective level of the 6th clock signal to the eight clock signals is low level.
Alternatively, described phase-shifting unit comprises: frequency divider, and the signal of input is carried out to m frequency division and produce the 15 clock signal, wherein, m is greater than 1 integer; Phase shifter, carries out phase shift to the 15 clock signal and produces the 6th clock signal, the 7th clock signal, the 8th clock signal.
Alternatively, described phase-shifting unit comprises: phase shifter, the signal of input is carried out to phase shift and produce the 16 clock signal, the 17 clock signal, the 18 clock signal, wherein, the duty ratio of the 16 clock signal to the 18 clock signals is identical with the duty ratio of the signal of input, and the time started of the significant level of the 17 clock signal is within the duration of the significant level of the 16 clock signal, the time started of the significant level of the 18 clock signal is within the duration of the significant level of the 17 clock signal, and between the time started of the time started of the significant level of the 16 clock signal and the significant level of the 17 clock signal interval greater than 0 and be less than the 16 clock signal cycle 1/3rd, between the time started of the time started of the significant level of the 17 clock signal and the significant level of the 18 clock signal interval greater than 0 and be less than the 16 clock signal cycle 1/3rd, frequency divider, carries out m frequency division to the 16 clock signal and produces the 6th clock signal, the 17 clock signal is carried out to m frequency division and produce the 7th clock signal, the 18 clock signal is carried out to m frequency division and produce the 8th clock signal, and wherein, m is greater than 1 integer.
Alternatively, each cycle of the 16 clock signal to the 18 clock signals comprises respectively significant level and non-effective level, wherein, the significant level of the 16 clock signal to the 18 clock signals is high level, and the non-effective level of the 16 clock signal to the 18 clock signals is low level.
Alternatively, also comprise the 6th switch, wherein, the first link of the 6th switch is connected with the second link, described the first link and the second link are connected to the first end of tertiary voltage memory, the control end of the 6th switch receives the 19 clock signal, and wherein, the 19 clock signal is the reverse signal of the 4th clock signal.
According to FV convertor of the present invention, can utilize the significant level time started of each clock signal and the set time between the duration poor, eliminate technique, supply voltage and the impact of environmental factor on conversion accuracy.In addition,, according to the present invention, can eliminate the impact of switch overshoot of the current source of FV convertor.
By part in ensuing description set forth the present invention other aspect and/or advantage, some will be clearly by descriptions, or can pass through enforcement of the present invention and learn.
Accompanying drawing explanation
By the detailed description of carrying out below in conjunction with accompanying drawing, above and other objects of the present invention, feature and advantage will become apparent, wherein:
Fig. 1 illustrates according to the circuit diagram of the FV convertor of exemplary embodiment of the present invention.
Fig. 2 illustrates the example of the oscillogram of the first clock signal according to exemplary embodiment of the present invention, second clock signal, the 3rd clock signal, the 4th clock signal, the 5th clock signal.
Fig. 3 illustrates according to the circuit diagram of the FV convertor of another exemplary embodiment of the present invention.
Fig. 4 illustrates according to the circuit diagram of the clock circuit in the FV convertor of Fig. 3 of exemplary embodiment of the present invention.
Embodiment
Now, describe more fully with reference to the accompanying drawings different example embodiment, wherein, some exemplary embodiments are shown in the drawings, and wherein, identical label represents identical parts all the time.
Fig. 1 illustrates according to the circuit diagram of the FV convertor of exemplary embodiment of the present invention.
As shown in Figure 1, according to the circuit 100 of FV convertor of the present invention, comprise: constant-current source Ic, the first interrupteur SW 1, second switch SW2, the 3rd interrupteur SW 3, the 4th interrupteur SW 4, the 5th interrupteur SW 5, the first voltage memory C1, second voltage memory C2, tertiary voltage memory C3.
The first link of the first interrupteur SW 1 is connected to constant-current source Ic, the second link ground connection of the first interrupteur SW 1, the first link of second switch SW2 is connected to constant-current source Ic, the second link of second switch SW2 is connected to the first end of the first voltage memory C1, the second end ground connection of the first voltage memory C1, the first link of the 3rd interrupteur SW 3 is connected to constant-current source Ic, the second link of the 3rd interrupteur SW 3 is connected to the first end of second voltage memory C2, the second end ground connection of second voltage memory C2, the first link of the 4th interrupteur SW 4 is connected to the first end of second voltage memory C2, the second link of the 4th interrupteur SW 4 is connected to the first end of tertiary voltage memory C3, the second end ground connection of tertiary voltage memory C3, the first link of the 5th interrupteur SW 5 is connected to the first end of second voltage memory C2, the second link ground connection of the 5th interrupteur SW 5, the first end of tertiary voltage memory C3 is as the output of the circuit 100 of FV convertor, output voltage V out.
The control end of the first interrupteur SW 1 receives the first clock signal F1, and the first interrupteur SW 1 conducting under the control of the significant level of the first clock signal F1, makes constant-current source Ic ground connection.The control end of second switch SW2 receives second clock signal F2, and second switch SW2 conducting under the control of the significant level of second clock signal F2, makes constant-current source Ic charge to the first voltage memory C1.The control end of the 3rd interrupteur SW 3 receives the 3rd clock signal F3, and the 3rd interrupteur SW 3 conductings under the control of the significant level of the 3rd clock signal F3, make constant-current source Ic charge to second voltage memory C2.The control end of the 4th interrupteur SW 4 receives the 4th clock signal F4, the 4th interrupteur SW 4 conductings under the control of the significant level of the 4th clock signal F4, thus make second voltage memory C2 and tertiary voltage memory C3 share electric charge.The control end of the 5th interrupteur SW 5 receives the 5th clock signal F5, and the 5th interrupteur SW 5 conductings under the control of the significant level of the 5th clock signal F5, make second voltage memory C2 through the 5th interrupteur SW 5 electric discharges.
Here, the first clock signal F1 to the five clock signal F5 that the first interrupteur SW 1 to the control end of the 5th interrupteur SW 5 receives comprise respectively significant level and non-effective level in each cycle.
Specifically, the non-effective level of the first clock signal F1 that the first interrupteur SW 1 can receive in response to the control end of the first interrupteur SW 1 disconnects, to disconnect being connected between constant-current source Ic and ground.As example, the first interrupteur SW 1 can be transmission gate or field-effect transistor (for example, NMOS pipe or PMOS pipe).Should be appreciated that, according to the difference of the implementation of the first interrupteur SW 1, the significant level of the first clock signal F1 can be a kind of in high level and low level, and correspondingly, the non-effective level of the first clock signal F1 can be the another kind in high level and low level.
The non-effective level of the second clock signal F2 that second switch SW2 can receive in response to the control end of second switch SW2 disconnects, to stop the charging of constant-current source Ic to the first voltage memory C1.As example, second switch SW2 can be transmission gate or field-effect transistor (for example, NMOS pipe or PMOS pipe).Should be appreciated that, according to the difference of the implementation of second switch SW2, the significant level of second clock signal F2 can be a kind of in high level and low level, and correspondingly, the non-effective level of second clock signal F2 can be the another kind in high level and low level.
The non-effective level of the 3rd clock signal F3 that the 3rd interrupteur SW 3 can receive in response to the control end of the 3rd interrupteur SW 3 disconnects, to stop the charging of constant-current source Ic to second voltage memory C2.As example, the 3rd interrupteur SW 3 can be transmission gate or field-effect transistor (for example, NMOS pipe or PMOS pipe).Should be appreciated that, according to the difference of the implementation of the 3rd interrupteur SW 3, the significant level of the 3rd clock signal F3 can be a kind of in high level and low level, and correspondingly, the non-effective level of the 3rd clock signal F3 can be the another kind in high level and low level.
The non-effective level of the 4th clock signal F4 that the 4th interrupteur SW 4 can receive in response to the control end of the 4th interrupteur SW 4 disconnects, and with the electric charge stopping between second voltage memory C2 and tertiary voltage memory C3, shares.As example, the 4th interrupteur SW 4 can be transmission gate or field-effect transistor (for example, NMOS pipe or PMOS pipe).Should be appreciated that, according to the difference of the implementation of the 4th interrupteur SW 4, the significant level of the 4th clock signal F4 can be a kind of in high level and low level, and correspondingly, the non-effective level of the 4th clock signal F4 can be the another kind in high level and low level.
The non-effective level of the 5th clock signal F5 that the 5th interrupteur SW 5 can receive in response to the control end of the 5th interrupteur SW 5 disconnects, so that second voltage memory C2 stops electric discharge.As example, the 5th interrupteur SW 5 can be transmission gate or field-effect transistor (for example, NMOS pipe or PMOS pipe).Should be appreciated that, according to the difference of the implementation of the 5th interrupteur SW 5, the significant level of the 5th clock signal F5 can be a kind of in high level and low level, and correspondingly, the non-effective level of the 5th clock signal F5 can be the another kind in high level and low level.
In addition, in the circuit 100 of FV convertor, when the 4th interrupteur SW 4 realizes by field-effect transistor, and when the physical size of the physical size of the 4th interrupteur SW 4 and the 3rd capacitor C3 is close, in order to reduce the impact of the 4th interrupteur SW 4 clock feed-through effects, can at the first end of tertiary voltage memory C3, add the 6th switch (not shown) as the switch of redundancy.The 6th switch can be the field-effect transistor (NMOS pipe or PMOS pipe) identical with the 4th switch.At this moment, the source electrode of the 6th switch (the first link with in the second link one) and drain electrode (the first link with in the second link another) can be connected, and make the source electrode after connection and drain to be connected to the first end of the 3rd memory C3, and the grid (control end) that makes the 6th switch receives the reverse signal (hereinafter referred to as the 19 clock signal) of the 4th clock signal F4, thereby reduce the impact of clock feed-through effect.
Should be appreciated that, for making the control end of the 6th switch receive the 19 clock signal, can in the circuit 100 of FV convertor, add reverser.Here, reverser can receive the 4th clock signal F4, and the 4th clock signal F4 receiving is reverse, and exports the 4th reverse clock signal F4 as the 19 clock signal.
Optimization, voltage frequency converter circuit receives the first clock signal of F1 100 F5 to fifth clock signal with the same frequency, and the first clock signal F1 to fifth clock signal F5 effective level of start time and end time in the following order cycle: the second clock signal the beginning of F2 the effective level of time & lt;The clock signal the end of the effective level of F5 5 time & lt;The third clock signal the beginning of the effective level of F3 time & lt;The first clock signal the end of the effective level of F1 time & lt;The third clock signal the end of the effective level of F3 time & lt;The first clock signal the start time & lt; the effective level of F1The second clock signal F2 the effective level of the end time of the clock signal the beginning of the F4 the effective level of 4 or less time & lt;The fourth clock signal the end of the effective level of F4 time & lt;The clock signal F5 5 effective level start time.
Described above and comprised in the time started of significant level and the one-period of end time of the first clock signal F1 to the five clock signal F5, the time started of significant level of the first clock signal F1 to the five clock signal F5 and the appearance of end time order.Yet first the time started that the invention is not restricted to the significant level of second clock signal F2 occurs.Due to the first clock signal F1 to the five clock signal F5 appearance that all circulates, therefore should be appreciated that, according to the difference of cycle dividing mode, the describing mode of said sequence there will be variation, but essence is identical technically.
For example, when first the end time of the significant level of the 5th clock signal F5 occurs, the time started of the significant level of second clock signal F2 finally occurs, namely, the significant level of the time started < second clock signal F2 of the significant level of the end time < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of the time started < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of the 5th clock signal F5 end time≤time started of significant level of time started < second clock signal F2 of significant level of end time < the 5th clock signal F5 of significant level of time started < the 4th clock signal F4 of significant level of the 4th clock signal F4.
In addition, should also be understood that no matter how the cycle divides, within two time starteds of significant level and the cycle of end time that all comprise the first clock signal F1 to the five clock signal F5, will inevitably deposit superincumbent order situation.
In addition, in the present invention, the time started of significant level and the order of end time of the first clock signal F1 to the five clock signal F5 are not limited to above preferred embodiment.In another embodiment, the first clock signal F1 that the circuit 100 of FV convertor receives has identical frequency to the 5th clock signal F5, and the first clock signal F1 circulates to time started and the end time of the significant level of the 5th clock signal F5 according to following order: the significant level of the end time < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of the time started < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of the 5th clock signal F5 time started≤time started of significant level of end time < the 5th clock signal F5 of significant level of end time < the 4th clock signal F4 of significant level of second clock signal F2,
And, the end time of the significant level of time started≤five's clock signal F5 of the significant level of second clock signal F2, or, the time started of the significant level of time started < the 3rd clock signal F3 of the significant level of the end time < second clock signal F2 of the significant level of the 5th clock signal F5;
And, the time started of the significant level of the time started < first clock signal F1 of the significant level of end time < the 4th clock signal F4 of the significant level of the 3rd clock signal F3, or, the end time of the significant level of time started≤second clock signal F2 of the significant level of time started≤four's clock signal F4 of the significant level of the first clock signal F1, or, the end time of the significant level of time started < the 4th clock signal F4 of the significant level of end time < the 4th clock signal F4 of the significant level of second clock signal F2.
Fig. 2 illustrates the example of the oscillogram of the first clock signal according to exemplary embodiment of the present invention, second clock signal, the 3rd clock signal, the 4th clock signal, the 5th clock signal.
As shown in Figure 2, the first clock signal F1 to the five clock signal F5 have identical frequency, and the significant level of the first clock signal F1 to the five clock signal F5 is high level, the non-effective level of the first clock signal F1 to the five clock signal F5 is low level.In addition, time started and the end time of the significant level of the first clock signal F1 to the five clock signal F5 circulate according to following order: the time started of the significant level of end time < the 5th clock signal F5 of the significant level of time started < the 4th clock signal F4 of the significant level of end time=four's clock signal F4 of the significant level of time started=second clock signal F2 of the significant level of the end time < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of the time started < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of time started=five's clock signal F5 of the significant level of second clock signal F2.
At t1 constantly, the first interrupteur SW 1 in the circuit 100 shown in Fig. 1 and second switch SW2 respectively in response to the first clock signal F1 and second clock signal F2 in high level (that is, significant level) and conducting.The 3rd interrupteur SW 3 to the 5th interrupteur SW 5 disconnects in low level (that is, non-effective level) in response to the 3rd clock signal F3 to the five clock signal F5 respectively.Now, constant-current source Ic ground connection, the first voltage memory C1 discharges by the first interrupteur SW 1 and second switch SW2.
At t2 constantly, the 3rd clock signal F3 saltus step is high level (that is, significant level), the 3rd interrupteur SW 3 conductings, and the first interrupteur SW 1 and second switch SW2 are in conducting state, and the 4th interrupteur SW 4 and the 5th interrupteur SW 5 are in off-state.Now, constant-current source Ic ground connection, the first voltage memory C1 and second voltage memory C2 electric discharge.
At t3 constantly, the first clock signal F1 saltus step is low level (that is, non-effective level), and the first interrupteur SW 1 disconnects, and second switch SW2 and the 3rd interrupteur SW 3 are in conducting state, and the 4th interrupteur SW 4 and the 5th interrupteur SW 5 are in off-state.Now, constant-current source Ic starts the first voltage memory C1 and second voltage memory C2 charging.
At t4 constantly, the 3rd clock signal F3 saltus step is low level (that is, non-effective level), and the 3rd interrupteur SW 3 disconnects, and second switch SW2 is in conducting state, and the first interrupteur SW 1, the 4th interrupteur SW 4 and the 5th interrupteur SW 5 are in off-state.Now, constant-current source Ic continues the first voltage memory C1 charging.
At t5 constantly, the first clock signal F1 saltus step is high level, the first interrupteur SW 1 conducting; The saltus step of second clock signal is low level (that is, non-effective level), and second switch SW2 disconnects; The 4th clock signal F4 saltus step is high level (that is, significant level), the 4th interrupteur SW 4 conductings; The 3rd interrupteur SW 3 and the 5th interrupteur SW 5 are in off-state.Now, constant-current source Ic ground connection, second voltage memory C2 and tertiary voltage memory C3 share electric charge.
At t6 constantly, the 4th clock signal F4 jumps to low level (that is, non-effective level), and the 4th interrupteur SW 4 disconnects, and the first interrupteur SW 1 is in conducting state, and second switch SW2, the 3rd interrupteur SW 3 and the 5th interrupteur SW 5 are in off-state.Now, the shared electric charge of second voltage memory C2 and tertiary voltage memory C3 finishes.
At t7 constantly, the 5th clock signal F5 jumps to high level (that is, significant level), the 5th interrupteur SW 5 conductings, and the first interrupteur SW 1 is in conducting state, and second switch SW2 to the four interrupteur SW 4 are in off-state.Now, second voltage memory C2 is by the 5th interrupteur SW 5 electric discharges.
As the above analysis, in the first clock signal F1 to the five clock signal F5 frequencies constant in the situation that, initial stage of operation at the circuit 100 shown in Fig. 1, at second clock signal F2 during first in significant level, the first interrupteur SW 1 and second switch SW2 conducting, constant-current source Ic ground connection, to eliminate the impact of switch connection immediate current overshoot on the circuit 100 shown in Fig. 1.The 3rd clock signal F3 first during significant level in corresponding with the △ t time period during in, constant-current source Ic charges to second voltage memory C2.In the 4th clock signal F4 is first during significant level, second voltage memory C2 shares electric charge with tertiary voltage memory C3 first, and the voltage of tertiary voltage memory C3 is since 0 increase, and correspondingly, the voltage Vout of output rises since 0.In the 5th clock signal F5 is first during significant level, second voltage memory C2 is by the 5th interrupteur SW 5 electric discharges.
When the 3rd clock signal F3 is during again in significant level, because the frequency of the first clock signal F1 to the five clock signal F5 is constant, △ t is constant, and the charging interval of second voltage memory C2 is constant, thereby the voltage of second voltage memory C2 is constant.At the 4th clock signal F4, during again in significant level, second voltage memory C2 and tertiary voltage memory C3 share electric charge again, thereby make the voltage of tertiary voltage memory C3 continue to increase, and correspondingly, the voltage Vout of output continues rising.At the 5th clock signal F5, again during significant level, second voltage memory C2 is again by the 5th interrupteur SW 5 electric discharges.After this, circuit 100 shown in Fig. 1 is shared the sequential loop charging of electric charge, second voltage memory C2 electric discharge, shared, discharging action according to second voltage memory C2 charging, second voltage memory C2 and tertiary voltage memory C3, finally, the voltage of tertiary voltage memory C3 is by the voltage that is stabilized in second voltage memory C2 and charges within the △ t time.Therefore, the voltage Vout of the 100 final outputs of the circuit shown in Fig. 1 can represent the charging voltage of second voltage memory C1 within the △ t time.
Because the charging interval is longer, the voltage at voltage memory two ends is also just larger.Therefore, the △ t time is longer, and the voltage that second voltage memory C2 charging produces is also just larger.Correspondingly, the voltage Vout of 100 outputs of the circuit shown in Fig. 1 is also just larger.Due to the frequency dependence of △ t and the first clock signal F1 to the five clock signal F5, more △ t is less for frequency, and the voltage Vout of output is also just less, and the less △ of frequency t is larger, and the voltage Vout of output is also just larger.The voltage Vout that therefore, can export by FV convertor represents the frequency of the first clock signal F1 to the five clock signal F5 of input.
Should be appreciated that, the first voltage memory C1 in the circuit 100 of the FV convertor shown in Fig. 1 can be capacitor or other can realize the device of store voltages, second voltage memory C2 in the circuit 100 of the FV convertor shown in Fig. 1 can be capacitor or other can realize the device of store voltages, and the tertiary voltage memory C3 in the circuit 100 of the FV convertor shown in Fig. 1 can be capacitor or other can realize the device of store voltages.
Fig. 3 illustrates according to the circuit diagram of the FV convertor of another exemplary embodiment of the present invention.
As shown in Figure 3, except the circuit 100 shown in Fig. 1 (being designated hereinafter simply as circuit 100), according to FV convertor of the present invention, also comprise clock circuit 200.
Specifically, clock circuit 200 can utilize the signal Fin of outside input to produce five the first clock signal F1, second clock signal F2, the 3rd clock signal F3, the 4th clock signal F4, the 5th clock signal F5 that frequency is identical.
In addition, time started and the end time of the significant level of the first clock signal F1 to the five clock signal F5 circulate according to following order: the time started of the significant level of end time < the 5th clock signal F5 of the significant level of end time < the 4th clock signal F4 of the significant level of time started≤second clock signal F2 of the significant level of the end time < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of the time started < first clock signal F1 of the significant level of end time < the 3rd clock signal F3 of the significant level of the 5th clock signal F5,
And, the end time of the significant level of time started≤five's clock signal F5 of the significant level of second clock signal F2, or, the time started of the significant level of time started < the 3rd clock signal F3 of the significant level of the end time < second clock signal F2 of the significant level of the 5th clock signal F5;
And, the time started of the significant level of the time started < first clock signal F1 of the significant level of end time < the 4th clock signal F4 of the significant level of the 3rd clock signal F3, or, the end time of the significant level of time started≤second clock signal F2 of the significant level of time started≤four's clock signal F4 of the significant level of the first clock signal F1, or, the end time of the significant level of time started < the 4th clock signal F4 of the significant level of end time < the 4th clock signal F4 of the significant level of second clock signal F2.
In addition, the frequency of the first clock signal F1 to the five clock signal F5 is monotonic functional relationship with the frequency of the signal Fin inputting respectively, for example, the first clock signal F1 to the five clock signal F5 are monotonic increase with the increase of frequency of the signal Fin of input, or the frequency of the first clock signal F1 to the five clock signal F5 with the increase of the frequency of input signal Fin monotone decreasing.
From above-mentioned analysis, the pass of the voltage Vout of the frequency of the first clock signal F1 to the five clock signal F5 and circuit 100 outputs is: the frequency of the first clock signal F1 to the five clock signal F5 is larger, the voltage Vout of output is less, the frequency of the first clock signal F1 to the five clock signal F5 is less, and the voltage Vout of output is larger.And the frequency of the first clock signal F1 to the five clock signal F5 that clock circuit 200 produces is monotonic functional relationship with the frequency of the signal Fin inputting respectively, the frequency that therefore, can represent with the output voltage V out of the FV convertor shown in Fig. 3 the signal Fin of input.
In one example, the frequency of the first frequency of clock signal F1 to the five clock signal F5 and the signal Fin of input is monotonically increasing functional relation, when the frequency of the signal Fin inputting increases, the frequency of the first clock signal F1 to the five clock signal F5 that clock circuit 200 produces correspondingly increases, and because the output voltage V out of circuit 100 reduces with the increase of the frequency of the first clock signal F1 to the five clock signal F5, therefore, the voltage Vout of FV convertor output will correspondingly reduce.
In another example, the frequency of the first frequency of clock signal F1 to the five clock signal F5 and the signal Fin of input is the functional relation of monotone decreasing, when the frequency of the signal Fin inputting increases, the frequency of the first clock signal F1 to the five clock signal F5 that clock circuit 200 produces correspondingly reduces, and due to the output voltage V out of circuit 100 reducing and increase with the frequency of the first clock signal F1 to the five clock signal F5, therefore, the voltage Vout of FV convertor output will correspondingly increase.
Should be appreciated that, because the output voltage V out of circuit 100 could accurately represent the frequency of input signal after stable, therefore frequency inverted precision constant for frequency according to the FV convertor of Fig. 1 of the present invention and Fig. 3 or the big or small longer input signal of holding time of frequency (the first clock signal F1 to the five clock signal F5, or signal Fin) is higher.
Fig. 4 illustrates according to the circuit diagram of the clock circuit 200 in the FV convertor of Fig. 3 of exemplary embodiment of the present invention.
As shown in Figure 4, clock circuit 200 of the present invention comprises: phase-shifting unit 210, frequency-halving circuit 220, the first logical operation circuit 230, the second logical operation circuit 240, the 3rd logical operation circuit 250.
Phase-shifting unit 210 utilizes the signal Fin of input to produce identical the 6th clock signal F6, the 7th clock signal F7, the 8th clock signal F8 of frequency.Here, the phase relation of the 6th clock signal F6 to the eight clock signal F8 is: the duty ratio of the 6th clock signal F6 to the eight clock signal F8 is identical, and the time started of the significant level of the 7th clock signal F7 is within the duration of the significant level of the 6th clock signal F6, the time started of the significant level of the 8th clock signal F8 is within the duration of the significant level of the 7th clock signal F7, and between the time started of the significant level of the time started of the significant level of the 6th clock signal F6 and the 7th clock signal F7 interval greater than 0 and be less than the 6th clock signal F6 cycle 1/3rd, between the time started of the significant level of the time started of the significant level of the 7th clock signal F7 and the 8th clock signal F8 interval greater than 0 and be less than the 6th clock signal F6 cycle 1/3rd.
Specifically, each cycle of the 6th clock signal F6 to the eight clock signal F8 comprises respectively significant level and non-effective level.For example, the significant level of the 6th clock signal F6 to the eight clock signal F8 is high level, and the non-effective level of the 6th clock signal F6 to the eight clock signal F8 is low level.
As example, phase-shifting unit 210 can be realized by phase shifter, to produce above-mentioned the 6th clock signal F6 to the eight clock signal F8.
As another example, phase-shifting unit 210 can comprise frequency divider (not shown) and phase shifter (not shown), and the output of frequency divider is connected to the input of phase shifter.Frequency divider carries out m (m is greater than 1 integer) frequency division to the signal Fin of outside input and produces the 15 clock signal, and phase shifter carries out phase shift to the 15 clock signal and produces the 6th clock signal F6, the 7th clock signal F7, the 8th clock signal F8.
As another example, phase-shifting unit 210 can comprise frequency divider (not shown) and phase shifter (not shown), and the output of phase shifter is connected to the input of frequency divider.Phase shifter carries out phase shift to the signal Fin of input and produces the 16 clock signal, the 17 clock signal, the 18 clock signal, here, the phase relation of the 16 clock signal to the 18 clock signals is: the duty ratio of the 16 duty ratio of clock signal to the 18 clock signals and the signal Fin of input is identical, and the time started of the significant level of the 17 clock signal is within the duration of the significant level of the 16 clock signal, the time started of the significant level of the 18 clock signal is within the duration of the significant level of the 17 clock signal, and between the time started of the time started of the significant level of the 16 clock signal and the significant level of the 17 clock signal interval greater than 0 and be less than the 16 clock signal cycle 1/3rd, between the time started of the time started of the significant level of the 17 clock signal and the significant level of the 18 clock signal interval greater than 0 and be less than the 16 clock signal cycle 1/3rd.Afterwards, frequency divider carries out m frequency division to the 16 clock signal and produces the 6th clock signal F6, the 17 clock signal is carried out to m frequency division and produce the 7th clock signal F7, the 18 clock signal is carried out to m frequency division and produce the 8th clock signal F8.
Specifically, each cycle of the 16 clock signal to the 18 clock signals comprises respectively significant level and non-effective level.For example, the significant level of the 16 clock signal to the 18 clock signals is high level, and the non-effective level of the 16 clock signal to the 18 clock signals is low level.
By the frequency divider in phase-shifting unit 210, the signal Fin of input is carried out to m frequency division, thereby can expand the scope of the frequency that FV convertor can change.
220 couples of the 6th clock signal F6 of frequency-halving circuit carry out the inferior two divided-frequency of n (n is more than or equal to 0 integer) and produce the 9th clock signal F9, the 6th clock signal F6 is carried out to n+2 two divided-frequency and produce the tenth clock signal F10, the 7th clock signal F7 is carried out to n+1 the two divided-frequency signal that n+1 two divided-frequency obtains the 7th clock signal F7, described n+1 two divided-frequency signal carried out oppositely producing the 11 clock signal F11, the 7th clock signal F7 is carried out to n+2 the two divided-frequency signal that n+2 two divided-frequency obtains the 7th clock signal F7, n+2 the two divided-frequency signal of the 7th clock signal F7 carried out oppositely producing the 12 clock signal F12, the 8th clock signal F8 is carried out to n+1 two divided-frequency and produce the 13 clock signal F13, the 8th clock signal F8 is carried out to n+2 the two divided-frequency signal that n+2 two divided-frequency obtains the 8th clock signal F8, n+2 the two divided-frequency signal of the 8th clock signal F8 carried out oppositely producing the first clock signal F1.Here, n+2 two divided-frequency signal of the 7th clock signal is the 3rd clock signal F3, and n+2 two divided-frequency signal of the 8th clock signal is the 14 clock signal F14.
Take below n=1 as example illustrates above-mentioned frequency-halving circuit 220.With reference to Fig. 4, frequency-halving circuit 220 can carry out 1 two divided-frequency by 2201 couples of the 6th clock signal F6 of two-divider and produce the 9th clock signal F9, by two-divider 2201, 2202 and 2203 couples of the 6th clock signal F6 carry out 3 two divided-frequencies and produce the tenth clock signal F10, by two-divider 2204 and 2205 couples of the 7th clock signal F7, carry out 2 two divided-frequency signals that 2 two divided-frequencies obtain the 7th clock signal F7, by 2207 pairs of described 2 two divided-frequency signals of reverser, carry out oppositely producing the 11 clock signal F11, by two-divider 2204, 2205 and 2206 couples of the 7th clock signal F7 carry out 3 two divided-frequency signals that 3 two divided-frequencies obtain the 7th clock signal F7, 3 two divided-frequency signals by 2208 couples of the 7th clock signal F7 of reverser carry out oppositely producing the 12 clock signal F12, by two-divider 2209 and 2210 couples of the 8th clock signal F8, carry out 2 two divided-frequencies and produce the 13 clock signal F13, by two-divider 2209, 2210 and 2211 couples of the 8th clock signal F8 carry out 3 two divided-frequency signals that 3 two divided-frequencies obtain the 8th clock signal F8, 3 two divided-frequency signals by 2212 couples of the 8th clock signal F8 of reverser carry out oppositely producing the first clock signal F1, and 3 two divided-frequency signals of the 7th clock signal F7 are the 3rd clock signal F3, 3 two divided-frequency signals of the 8th clock signal F8 are the 14 clock signal F14.
Should be appreciated that, can adopt various two-dividers.For example, two-divider can be realized by d type flip flop.For example, the data input pin of d type flip flop is connected with the oppisite phase data output of d type flip flop, the input using the clock signal input terminal of d type flip flop as two-divider, the output using the data output end of d type flip flop as two-divider.Be further appreciated that because d type flip flop has oppisite phase data output, so carrying out the anti-phase signal obtaining and can the oppisite phase data output by d type flip flop bring in output in the aforementioned embodiment.Simultaneously, when realizing above-described embodiment with d type flip flop, because d type flip flop has two outputs (data output end and oppisite phase data output), for example, so the connected mode of circuit (: when the 6th clock signal F6 is carried out to 3 two divided-frequencies generation the tenth clock signal F10 can be selected voluntarily, the data output end of the first d type flip flop can be connected with the clock signal input terminal of the second d type flip flop, the data output end of the second d type flip flop is connected with the clock signal input terminal of 3d flip-flop, data output end at 3d flip-flop produces the tenth clock signal F10, or, the oppisite phase data output of the first d type flip flop is connected with the clock signal input terminal of the second d type flip flop, the oppisite phase data output of the second d type flip flop is connected with the clock signal input terminal of 3d flip-flop, data output end at 3d flip-flop produces the tenth clock signal F10).Certainly, the circuit that two-divider also can be realized divide-by-two function by other is realized.
Should be appreciated that, frequency-halving circuit is also not limited only to realize by two-divider, also can be by 2
nfrequency divider carries out n the two divided-frequency signal of n two divided-frequency generation the 6th clock signal F6 to the 6th clock signal F6, i.e. the 9th clock signal F9, by n the two divided-frequency signal of the 6th clock signal F6 being carried out to 2 two divided-frequencies, produce the tenth clock signal F10, by 2
n+1frequency divider carries out to the 7th clock signal F7 n+1 the two divided-frequency signal that n+1 two divided-frequency obtains the 7th clock signal F7, described n+1 two divided-frequency signal carried out oppositely producing the 11 clock signal F11, n+1 the two divided-frequency signal of the 7th clock signal F7 carried out to n+2 the two divided-frequency signal that 1 two divided-frequency obtains the 7th clock signal F7, i.e. the 3rd clock signal, n+2 the two divided-frequency signal of the 7th clock signal F7 carried out oppositely producing the 12 clock signal F12, by 2
n+1frequency divider carries out n+1 the two divided-frequency signal of n+1 two divided-frequency generation the 8th clock signal F8 to the 8th clock signal F8, i.e. the 13 clock signal F13, n+1 the two divided-frequency signal of the 8th clock signal F8 carried out to n+2 the two divided-frequency signal that 1 two divided-frequency obtains the 8th clock signal F8, the 14 clock signal F14, carries out oppositely producing the first clock signal F1 to n+2 the two divided-frequency signal of the 8th clock signal F8.
The first logical operation circuit 230 is two inputs or door.The tenth clock signal F10 and the 14 clock signal F14 that the first logical operation circuit 230 produces frequency-halving circuit 220 carry out logic OR computing, to export second clock signal F2.
The second logical operation circuit 240 is two inputs and door.The 12 clock signal F12 and the 13 clock signal F13 that the second logical operation circuit 240 produces frequency-halving circuit carry out logic and operation, to export the 4th clock signal F4.
The 3rd logical operation circuit 250 is two inputs and door.The 9th clock signal F9, the 11 clock signal F11, the 12 clock signal F12 that the 3rd logical operation circuit 250 produces frequency-halving circuit carry out logic and operation, to export the 5th clock signal F5.
Above-mentioned clock circuit 220 adopts the mode of digital logical operation to produce the first clock signal F1 to the five clock signal F5, the waveform of the first clock signal F1 to the five clock signal F5 that produce is not vulnerable to the impact of technique, supply voltage, ambient temperature, and the time started of the significant level of the first clock signal F1 to the five clock signal F5 keeps the stable time difference, thereby the first interrupteur SW 1 effectively in control circuit 100, to the 5th conducting of interrupteur SW 5 or the time of disconnection, has been avoided the impact of constant-current source Ic switch overshoot.
According to FV convertor of the present invention, utilize constant-current source Ic to charge to second voltage memory C2, the first interrupteur SW 1 in the first clock signal F1 to the five clock signal F5 control circuits 100 that and frequency identical by frequency fixed is simultaneously to conducting or the disconnection of the 5th interrupteur SW 5, make the voltage of second voltage memory C2 corresponding with the time of charging, namely corresponding with the frequency of clock signal, thus can by frequency inverted, be accurately voltage.And the conversion accuracy of FV convertor is not vulnerable to the impact of technique, supply voltage, ambient temperature.
Although specifically shown with reference to its exemplary embodiment and described the utility model, but it should be appreciated by those skilled in the art, in the situation that do not depart from the spirit and scope of the present utility model that claim limits, can carry out the various changes in form and details to it.
Claims (10)
1. a FV convertor, comprising: constant-current source, the first switch, second switch, the 3rd switch, the 4th switch, the 5th switch, the first voltage memory, second voltage memory, tertiary voltage memory,
Wherein, the first link of the first switch is connected to constant-current source, the second link ground connection of the first switch, the control end of the first switch receives the first clock signal, the first link of second switch is connected to constant-current source, the second link of second switch is connected to the first end of the first voltage memory, the second end ground connection of the first voltage memory, the control end of second switch receives second clock signal, the first link of the 3rd switch is connected to constant-current source, the second link of the 3rd switch is connected to the first end of second voltage memory, the second end ground connection of second voltage memory, the control end of the 3rd switch receives the 3rd clock signal, the first link of the 4th switch is connected to the first end of second voltage memory, the second link of the 4th switch is connected to the first end of tertiary voltage memory, the second end ground connection of tertiary voltage memory, the control end of the 4th switch receives the 4th clock signal, the first link of the 5th switch is connected to the first end of second voltage memory, the second link ground connection of the 5th switch, the control end of the 5th switch receives the 5th clock signal.
2. FV convertor as claimed in claim 1, wherein, the first end of tertiary voltage memory is as output, the significant level conducting of the first clock signal that the first switching response receives in the control end of the first switch, the significant level conducting of the second clock signal that second switch receives in response to the control end of second switch, the significant level conducting of the 3rd clock signal that the 3rd switching response receives in the control end of the 3rd switch, the significant level conducting of the 4th clock signal that the 4th switching response receives in the control end of the 4th switch, the significant level conducting of the 5th clock signal that the 5th switching response receives in the control end of the 5th switch,
Wherein, the significant level of the first clock signal is a kind of in high level and low level, the non-effective level of the first clock signal is the another kind in high level and low level, the significant level of second clock signal is a kind of in high level and low level, the non-effective level of second clock signal is the another kind in high level and low level, the significant level of the 3rd clock signal is a kind of in high level and low level, the non-effective level of the 3rd clock signal is the another kind in high level and low level, the significant level of the 4th clock signal is a kind of in high level and low level, the non-effective level of the 4th clock signal is the another kind in high level and low level, the significant level of the 5th clock signal is a kind of in high level and low level, the non-effective level of the 5th clock signal is the another kind in high level and low level.
3. FV convertor as claimed in claim 1, also comprises:
Clock circuit, signal based on input produces the first clock signal, second clock signal, 3rd clock signal, 4th clock signal, 5th clock signal, wherein, the first clock signal has identical frequency to the 5th clock signal, and the first clock signal circulates to time started and the end time of the significant level of the 5th clock signal according to following order: the significant level of end time < first clock signal of the significant level of end time < the 3rd clock signal of the significant level of time started < first clock signal of the significant level of end time < the 3rd clock signal of the significant level of the 5th clock signal time started≤time started of significant level of end time < the 5th clock signal of significant level of end time < the 4th clock signal of significant level of second clock signal,
And, the end time of the significant level of time started≤five's clock signal of the significant level of second clock signal, or, the time started of the significant level of time started < the 3rd clock signal of the significant level of the end time < second clock signal of the significant level of the 5th clock signal
And, the time started of the significant level of time started < first clock signal of the significant level of end time < the 4th clock signal of the significant level of the 3rd clock signal, or, the end time of the significant level of time started≤second clock signal of the significant level of time started≤four's clock signal of the significant level of the first clock signal, or, the end time of the significant level of time started < the 4th clock signal of the significant level of end time < the 4th clock signal of the significant level of second clock signal,
Wherein, each cycle of the first clock signal to the five clock signals comprises respectively significant level and non-effective level, the non-effective level of the first clock signal that the first switching response receives in the control end of the first switch disconnects, the non-effective level of the second clock signal that second switch receives in response to the control end of second switch disconnects, the non-effective level of the 3rd clock signal that the 3rd switching response receives in the control end of the 3rd switch disconnects, the non-effective level of the 4th clock signal that the 4th switching response receives in the control end of the 4th switch disconnects, the non-effective level of the 5th clock signal that the 5th switching response receives in the control end of the 5th switch disconnects.
4. FV convertor as claimed in claim 3, wherein, the frequency of the first clock signal to the five clock signals is monotonic functional relationship with the frequency of the signal of input respectively.
5. FV convertor as claimed in claim 3, wherein, described clock circuit comprises:
Phase-shifting unit, utilize the signal of input to produce the 6th identical clock signal of frequency, the 7th clock signal, the 8th clock signal, wherein, the duty ratio of the 6th clock signal to the eight clock signals is identical, and the time started of the significant level of the 7th clock signal is within the duration of the significant level of the 6th clock signal, the time started of the significant level of the 8th clock signal is within the duration of the significant level of the 7th clock signal, and between the time started of the significant level of the time started of the significant level of the 6th clock signal and the 7th clock signal interval greater than 0 and be less than the 6th clock signal cycle 1/3rd, between the time started of the significant level of the time started of the significant level of the 7th clock signal and the 8th clock signal interval greater than 0 and be less than the 6th clock signal cycle 1/3rd,
Frequency-halving circuit, the 6th clock signal is carried out to n two divided-frequency and produce the 9th clock signal, the 6th clock signal is carried out to n+2 two divided-frequency and produce the tenth clock signal, the 7th clock signal is carried out to n+1 the two divided-frequency signal that n+1 two divided-frequency obtains the 7th clock signal, described n+1 two divided-frequency signal carried out oppositely producing the 11 clock signal, the 7th clock signal is carried out to n+2 the two divided-frequency signal that n+2 two divided-frequency obtains the 7th clock signal, n+2 two divided-frequency signal of the 7th clock signal carried out oppositely producing the 12 clock signal, the 8th clock signal is carried out to n+1 two divided-frequency and produce the 13 clock signal, the 8th clock signal is carried out to n+2 the two divided-frequency signal that n+2 two divided-frequency obtains the 8th clock signal, n+2 two divided-frequency signal of the 8th clock signal carried out oppositely producing the first clock signal, wherein, n is more than or equal to 0 integer, n+2 two divided-frequency signal of the 7th clock signal is the 3rd clock signal, n+2 two divided-frequency signal of the 8th clock signal is the 14 clock signal,
The first logical operation circuit, the tenth clock signal and the 14 clock signal that frequency-halving circuit is produced are carried out logic OR computing, to export second clock signal;
The second logical operation circuit, the 12 clock signal and the 13 clock signal that frequency-halving circuit is produced are carried out logic and operation, to export the 4th clock signal;
The 3rd logical operation circuit, the 9th clock signal, the 11 clock signal, the 12 clock signal that frequency-halving circuit is produced are carried out logic and operation, to export the 5th clock signal.
6. FV convertor as claimed in claim 5, wherein, each cycle of the 6th clock signal to the eight clock signals comprises respectively significant level and non-effective level, wherein, the significant level of the 6th clock signal to the eight clock signals is high level, and the non-effective level of the 6th clock signal to the eight clock signals is low level.
7. FV convertor as claimed in claim 6, wherein, described phase-shifting unit comprises:
Frequency divider, carries out m frequency division to the signal of input and produces the 15 clock signal, and wherein, m is greater than 1 integer;
Phase shifter, carries out phase shift to the 15 clock signal and produces the 6th clock signal, the 7th clock signal, the 8th clock signal.
8. FV convertor as claimed in claim 6, wherein, described phase-shifting unit comprises:
Phase shifter, the signal of input is carried out to phase shift and produce the 16 clock signal, the 17 clock signal, the 18 clock signal, wherein, the duty ratio of the 16 clock signal to the 18 clock signals is identical with the duty ratio of the signal of input, and the time started of the significant level of the 17 clock signal is within the duration of the significant level of the 16 clock signal, the time started of the significant level of the 18 clock signal is within the duration of the significant level of the 17 clock signal, and between the time started of the time started of the significant level of the 16 clock signal and the significant level of the 17 clock signal interval greater than 0 and be less than the 16 clock signal cycle 1/3rd, between the time started of the time started of the significant level of the 17 clock signal and the significant level of the 18 clock signal interval greater than 0 and be less than the 16 clock signal cycle 1/3rd,
Frequency divider, carries out m frequency division to the 16 clock signal and produces the 6th clock signal, the 17 clock signal is carried out to m frequency division and produce the 7th clock signal, the 18 clock signal is carried out to m frequency division and produce the 8th clock signal, and wherein, m is greater than 1 integer.
9. FV convertor as claimed in claim 8, wherein, each cycle of the 16 clock signal to the 18 clock signals comprises respectively significant level and non-effective level, wherein, the significant level of the 16 clock signal to the 18 clock signals is high level, and the non-effective level of the 16 clock signal to the 18 clock signals is low level.
10. FV convertor as claimed in claim 1, also comprise the 6th switch, wherein, the first link of the 6th switch is connected with the second link, described the first link and the second link are connected to the first end of tertiary voltage memory, the control end of the 6th switch receives the 19 clock signal, and wherein, the 19 clock signal is the reverse signal of the 4th clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410352497.3A CN104158535B (en) | 2014-07-23 | 2014-07-23 | FV convertor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410352497.3A CN104158535B (en) | 2014-07-23 | 2014-07-23 | FV convertor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104158535A true CN104158535A (en) | 2014-11-19 |
| CN104158535B CN104158535B (en) | 2017-06-16 |
Family
ID=51883960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410352497.3A Active CN104158535B (en) | 2014-07-23 | 2014-07-23 | FV convertor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104158535B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811966A (en) * | 2016-02-26 | 2016-07-27 | 上海华虹宏力半导体制造有限公司 | Frequency-to-voltage circuit |
| CN116094526A (en) * | 2022-12-31 | 2023-05-09 | 成都电科星拓科技有限公司 | Method and device for converting pulse frequency into voltage |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85102705A (en) * | 1985-04-01 | 1986-09-17 | 中国科学院大连化学物理研究所 | Voltage-frequency converter |
| CN1677967A (en) * | 2004-03-30 | 2005-10-05 | 鼎芯通讯（上海）有限公司 | Binary frequency-shift key-controlled demodulator and frequency voltage conversion circuit |
| US20070075710A1 (en) * | 2005-06-03 | 2007-04-05 | Kirk Hargreaves | Methods and systems for detecting a capacitance using sigma-delta measurement techniques |
| CN101082640A (en) * | 2006-06-01 | 2007-12-05 | 瓦孔厄伊公司 | Measurement of the current of a frequency converter |
| US20090108914A1 (en) * | 2007-10-31 | 2009-04-30 | Chiphomer Technology Limited | Adaptive capacitive touch sense control circuit |
| CN102193033A (en) * | 2010-03-08 | 2011-09-21 | 上海海栎创微电子有限公司 | Self-capacitance change measuring circuit with quick response |
-
2014
- 2014-07-23 CN CN201410352497.3A patent/CN104158535B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85102705A (en) * | 1985-04-01 | 1986-09-17 | 中国科学院大连化学物理研究所 | Voltage-frequency converter |
| CN1677967A (en) * | 2004-03-30 | 2005-10-05 | 鼎芯通讯（上海）有限公司 | Binary frequency-shift key-controlled demodulator and frequency voltage conversion circuit |
| US20070075710A1 (en) * | 2005-06-03 | 2007-04-05 | Kirk Hargreaves | Methods and systems for detecting a capacitance using sigma-delta measurement techniques |
| CN101082640A (en) * | 2006-06-01 | 2007-12-05 | 瓦孔厄伊公司 | Measurement of the current of a frequency converter |
| US20090108914A1 (en) * | 2007-10-31 | 2009-04-30 | Chiphomer Technology Limited | Adaptive capacitive touch sense control circuit |
| CN102193033A (en) * | 2010-03-08 | 2011-09-21 | 上海海栎创微电子有限公司 | Self-capacitance change measuring circuit with quick response |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811966A (en) * | 2016-02-26 | 2016-07-27 | 上海华虹宏力半导体制造有限公司 | Frequency-to-voltage circuit |
| CN105811966B (en) * | 2016-02-26 | 2019-06-04 | 上海华虹宏力半导体制造有限公司 | Frequency turns potential circuit |
| CN116094526A (en) * | 2022-12-31 | 2023-05-09 | 成都电科星拓科技有限公司 | Method and device for converting pulse frequency into voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104158535B (en) | 2017-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108445734B (en) | Clock pulse frequency multiplication, frequency multiplication and digital pulse generation circuit and time-to-digital converter | |
| US8350631B1 (en) | Relaxation oscillator with low power consumption | |
| CN103036537A (en) | Generation method for phase interpolator and multiphase interpolation device and interpolation clock | |
| US9618963B2 (en) | Power management apparatus and multi-source energy harvesting system using the same | |
| CN104579254A (en) | Relaxation oscillator | |
| CN109314521A (en) | Asynchronous clock for time alternation type gradually-appoximant analog-digital converter generates | |
| CN104205641A (en) | System for a clock shifter circuit | |
| CN104038219A (en) | Apparatus and method for reducing sampling circuit timing mismatch | |
| CN103178835B (en) | Crystal oscillator and the method that crystal oscillator acceleration is vibrated | |
| CN103138560A (en) | Frequency jitter system | |
| CN110518896B (en) | Clock generating circuit and chip for providing arbitrary frequency and duty ratio | |
| CN103905185A (en) | Pulse generator applied to distributing continuous variable quantum secret keys | |
| CN104104386A (en) | Frequency voltage switching circuit and oscillator | |
| CN104158535A (en) | Frequency and voltage convertor | |
| CN103208980A (en) | Window voltage comparison device | |
| CN101621288B (en) | Circuit for converting PWM output mode into PFM output mode | |
| US8947146B2 (en) | Pulse-based flip flop | |
| CN110785931A (en) | Oscillator circuit with comparator delay cancellation | |
| US7898311B2 (en) | Phase shifting circuit which produces phase shift signal regardless of frequency of input signal | |
| CN106208675A (en) | DC/DC controller based on digital delay circuit | |
| CN101517896B (en) | A/d converter | |
| CN111867183A (en) | LED drive circuit, power frequency square wave signal sampling circuit and method | |
| CN104917492A (en) | CMOS oscillator | |
| CN103259415A (en) | Constant current switching power supply and constant current controller thereof | |
| CN103580605A (en) | Method for generating signal and signal generation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |